NB7V72MMNHTBG

1.8 V/2.5 V Differential 2 x 2 Crosspoint Switch with CML Outputs Clock/Data Buffer/Translator Multi−Level Inputs w/ Internal Termination NB7V72M www.onsemi.com MARKING DIAGRAM* Description The NB7V72M is a high bandwidth, low voltage, fully differential 2 x 2 crosspoint switch with CML outputs. The NB7V72M design is optimized for low skew and minimal jitter as it produces two identical copies of Clock or Data operating up to 5 GHz or 6.5 Gb/s, respectively. As such, the NB7V72M is ideal for SONET, GigE, Fiber Channel, Backplane and other clock/data distribution applications. The differential IN/IN inputs incorporate internal 50 W termination resistors and will accept LVPECL, CML, or LVDS logic levels (see Figure 10). The 16 mA differential CML outputs provide matching internal 50 W terminations and produce 400 mV output swings when externally terminated with a 50 W resistor to VCC (see Figure 11). The NB7V72M is the 1.8 V/2.5 V CML version of the NB7L72M and is offered in a low profile 3x3 mm 16−pin QFN package. Application notes, models, and support documentation are available at www.onsemi.com. The NB7V72M is a member of the GigaComm™ family of high performance clock products. 1 1 QFN−16 MN SUFFIX CASE 485G Maximum Input Data Rate > 6.5 Gb/s Data Dependent Jitter < 15 ps pk−pk Maximum Input Clock Frequency > 5 GHz Random Clock Jitter < 0.8 ps RMS, Max 150 ps Typical Propagation Delay 30ps Typical Rise and Fall Times Differential CML Outputs, 400 mV peak−to−peak, typical Operating Range: VCC = 1.71 V to 2.625 V with GND = 0 V Internal 50 W Input Termination Resistors QFN−16 Package, 3mm x 3mm −40°C to +85°C Ambient Operating Temperature These are Pb−Free Devices NB7V 72M ALYWG G A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. Features • • • • • • • • • • • • 16 + SEL0 IN0 VT0 0 IN0 1 0 IN1 VT1 + IN1 1 Q0 Q0 Q1 Q1 SEL1 Figure 1. Logic Diagram ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. © Semiconductor Components Industries, LLC, 2009 May, 2021 − Rev. 2 1 Publication Order Number: NB7V72M/D NB7V72M VT0 16 IN0 1 IN0 2 SEL0 GND VCC 15 14 Exposed Pad (EP) Table 1. INPUT/OUTPUT SELECT TRUTH TABLE 13 12 Q0 11 Q0 SEL0* SEL1* Q0 Q1 L L IN0 IN0 L H IN0 IN1 H L IN1 IN0 H H IN1 IN1 NB7V72M IN1 3 10 Q1 IN1 4 9 Q1 *Defaults HIGH when left open 5 VT1 6 7 SEL1 GND 8 VCC Figure 2. Pin Configuration (Top View) Table 2. PIN DESCRIPTION Pin Name I/O 1 IN0 LVPECL, CML, LVDS Input Noninverted Differential Input. (Note 1) Description 2 IN0 LVPECL, CML, LVDS Input Inverted Differential Input. (Note 1) 3 IN1 LVPECL, CML, LVDS Input Inverted Differential Input. (Note 1) 4 IN1 LVPECL, CML, LVDS Input Noninverted Differential Input. (Note 1) 5 VT1 − 6 SEL1 LVCMOS Input 7 GND 8 VCC − 9 Q1 CML Output Noninverted Differential Output. (Note 1) 10 Q1 CML Output Inverted Differential Output. (Note 1) 11 Q0 CML Output Inverted Differential Output. (Note 1) 12 Q0 CML Output Noninverted Differential Output. (Note 1) 13 VCC − Positive Supply Voltage 14 GND − Negative Supply Voltage 15 SEL0 LVCMOS Input 16 VT0 − Internal 50 W Termination Pin for IN0 and IN0 − EP − The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is electrically connected to the die, and is recommended to be electrically and thermally connected to GND on the PC board. Internal 50 W Termination Pin for IN1 and IN1 Input Select logic pin for IN0 or IN1 Inputs to Q1 output. See Table 1, Input/Output Select Truth Table; pin defaults HIGH when left open. Negative Supply Voltage Positive Supply Voltage Input Select logic pin for IN0 or IN1 Inputs to Q0 output. See Table 1, Input/Output Select Truth Table; pin defaults HIGH when left open. 1. In the differential configuration when the input termination pins (VT0, VT1) are connected to a common termination voltage or left open, and if no signal is applied on INx/INx input, then the device will be susceptible to self−oscillation. 2. All VCC and GND pins must be externally connected to a power supply for proper operation. www.onsemi.com 2 NB7V72M Table 3. ATTRIBUTES Characteristics Value ESD Protection Human Body Model Machine Model > 4 kV > 200 V RPU − Input Pullup Resistor 75 kΩ Moisture Sensitivity 16−QFN Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 210 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC Positive Power Supply GND = 0 V 3.0 V VIN Positive Input Voltage GND = 0 V −0.5 to VCC +0.5 V Differential Input Voltage |IN − IN| 1.89 V IIN Input Current Through RT (50 Ω Resistor) ±40 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) (Note 3) QFN−16 QFN−16 42 35 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) (Note 3) QFN−16 4 °C/W Tsol Wave Solder 265 °C VINPP 0 lfpm 500 lfpm Pb−Free Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. www.onsemi.com 3 NB7V72M Table 5. DC CHARACTERISTICS, Multi−Level Inputs VCC = 1.71 V to 2.625 V, GND = 0 V, TA = −40°C to +85°C (Note 4) Symbol Characteristic Min Typ Max Unit VCC = 2.5 V VCC = 1.8 V 120 80 145 110 170 140 mA VCC = 2.5 V VCC = 1.8 V VCC – 40 2460 1760 VCC – 20 2480 1780 VCC 2500 1800 mV VCC = 2.5 V VCC = 1.8 V VCC – 650 1850 1150 VCC – 400 2100 1400 VCC – 300 2200 1500 mV 1050 VCC − 100 mV VCC mV POWER SUPPLY CURRENT ICC Power Supply Current (Inputs and Outputs Open) CML OUTPUTS VOH Output HIGH Voltage (Note 5) VOL Output LOW Voltage (Note 5) DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE−ENDED (Note 6) (Figures 5 and 7) Vth Input Threshold Reference Voltage Range (Note 7) VIH Single−Ended Input HIGH Voltage Vth + 100 VIL Single−Ended Input LOW Voltage GND Vth − 100 mV Single−Ended Input Voltage (VIH − VIL) 200 VCC − GND mV VISE DIFFERENTIAL DATA/CLOCK INPUTS DRIVEN DIFFERENTIALLY (Figures 6 and 8) (Note 8) VIHD Differential Input HIGH Voltage (INn, INn) 1100 VCC mV VILD Differential Input LOW Voltage (INn, INn) GND VCC − 100 mV VID Differential Input Voltage (INn, INn) (VIHD − VILD) 100 1200 mV Input Common Mode Range (Differential Configuration, Note 9) (Figure 9) 1050 VCC − 50 mV IIH Input HIGH Current INn, INn (VTIN/VTIN Open) −150 150 mA IIL Input LOW Current INn, INn (VTIN/VTIN Open) −150 150 mA VCMR CONTROL INPUTS (SEL0, SEL1) VIH Input HIGH Voltage for Control Pins VCC x 0.65 VCC mV VIL Input LOW Voltage for Control Pins GND VCC x 0.35 mV IIH Input HIGH Current −150 20 150 mA IIL Input LOW Current −150 5 150 mA Internal Input Termination Resistor 40 50 60 W Internal Output Termination Resistor 40 50 60 W TERMINATION RESISTORS RTIN RTOUT NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 4. Input and output parameters vary 1:1 with VCC. 5. CML outputs loaded with 50 W to VCC for proper operation. 6. Vth, VIH, VIL, and VISE parameters must be complied with simultaneously. 7. Vth is applied to the complementary input when operating in single−ended mode. 8. VIHD, VILD, VID, and VCMR parameters must be complied with simultaneously. 9. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input signal. www.onsemi.com 4 NB7V72M Table 6. AC CHARACTERISTICS VCC = 1.71 V to 2.625 V, GND = 0 V, TA = −40°C to 85°C (Note 10) Symbol Characteristic fMAX Min Maximum Input Clock Frequency fDATAMAX VOUTPP tPLH, tPHL VCC = 2.5 V VCC = 1.8 V 6.5 Output Voltage Amplitude (@ VINPPmin) fin ≤ 5 GHz (See Figures 3 and 10, Note 11) 200 400 110 150 INn/INn to Qn/Qn Propagation Delay Temperature Coefficient tSKEW Output Clock Duty Cycle (Reference Duty Cycle = 50%) fin ≤ 5GHz tjitter RJ – Output Random Jitter (Note 13) fin ≤ 5 GHz DJ – Deterministic Jitter (Note 14) ≤ 9 Gbps tr,, tf mV 200 50 tDC 45 Input Voltage Swing (Differential Configuration) (Note 15) 100 Output Rise/Fall Times @ 1 GHz (20% − 80%), Qn, Qn 20 Unit Gbps Output−to−Output Skew (within device) (Note 12) Device−to−Device Skew (tpdmax – tpdmin) VINPP Max GHz Maximum Operating Data Rate (PRBS23) Propagation Delay to Differential Outputs, @ 1GHz, Measured at Differential Cross−point tPLH TC Typ 5 4.5 ps Dfs/°C 30 50 ps 50 55 % 0.5 0.8 10 ps RMS ps pk−pk 1200 mV 50 ps 30 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 10. Measured using a 400 mV source, 50% duty cycle clock source. All output loading with external 50 W to VCC. Input edge rates w40 ps (20% − 80%). 11. Output voltage swing is a single−ended measurement operating in differential mode. 12. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when the delays are measured from cross−point of the inputs to the cross−point of the outputs. 13. Additive RMS jitter with 50% duty cycle clock signal. 14. Additive Peak−to−Peak data dependent jitter with input NRZ data at PRBS23. 15. Input voltage swing is a single−ended measurement operating in differential mode. OUTPUT VOLTAGE AMPLITUDE (mV) 500 450 VCC Q AMP (mV) 400 350 INn 300 50 W VTn 250 200 50 W INn 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 fin, Clock Input Frequency (GHz) Figure 3. CLOCK Output Voltage Amplitude (VOUTPP) vs. Input Frequency (fin) at Ambient Temperature (Typ) Figure 4. Input Structure www.onsemi.com 5 NB7V72M IN VIH Vth IN VIL IN IN Vth Figure 5. Differential Input Driven Single−Ended VCC Vthmax Figure 6. Differential Inputs Driven Differentially VIHmax VILmax VIH Vth VIL Vth VILD VILmin GND Figure 7. Vth Diagram VCC Figure 8. Differential Inputs Driven Differentially VIHDmax VCMmax IN VILDmax IN VCMR IN GND VIHD IN VIHmin Vthmin VCMmin VID = |VIHD(IN) − VILD(IN)| IN VINPP = VIH(IN) − VIL(IN) IN VIHDtyp VID = VIHD − VILD Q VILDtyp VOUTPP = VOH(Q) − VOL(Q) Q VIHDmin tPHL VILDmin tPLH Figure 9. VCMR Diagram Figure 10. AC Reference Measurement NB7V72M Receiver VCC VCC (Receiver) 50 W 50 W Q 50 W 50 W Q 16 mA GND Figure 11. Typical CML Output Structure and Termination www.onsemi.com 6 NB7V72M VCC 50 W Z = 50 W DUT Driver Device 50 W Q D Receiver Device Z = 50 W Q D Figure 12. Typical Termination for CML Output Driver and Device Evaluation VCC VCC ZO = 50 W LVPECL Driver NB7V72M ZO = 50 W IN 50 W VT = VCC − 2 V ZO = 50 W VCC VCC LVDS Driver 50 W GND GND VCC VCC CML Driver VCC NB7V72M ZO = 50 W IN 50 W VT = VCC ZO = 50 W Differential Driver 50 W GND Figure 14. LVDS Interface VCC IN GND 50 W IN Figure 13. LVPECL Interface ZO = 50 W 50 W VT = Open ZO = 50 W IN GND NB7V72M IN NB7V72M IN 50 W VT = VREFAC* ZO = 50 W 50 W IN GND GND GND Figure 16. Capacitor−Coupled Differential Interface (VT Connected to External VREFAC) Figure 15. Standard 50 W Load CML Interface *VREFAC bypassed to ground with a 0.01 mF capacitor www.onsemi.com 7 NB7V72M ORDERING INFORMATION Device Package Shipping† NB7V72MMNHTBG QFN−16 (Pb−free) 100 / Tape & Reel NB7V72MMNTXG QFN−16 (Pb−free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. GigaComm is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. www.onsemi.com 8 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QFN16 3x3, 0.5P CASE 485G ISSUE G 1 SCALE 2:1 DATE 08 OCT 2021 GENERIC MARKING DIAGRAM* XXXXX XXXXX ALYWG G XXXXX A L Y W G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON04795D QFN16 3X3, 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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