NB7VQ58M 1.8V / 2.5V / 3.3V Differential 2:1 Clock/Data Multiplexer / Translator with CML Outputs
w/ Selectable Input Equalizer Multi−Level Inputs w/ Internal Termination
Description
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The NB7VQ58M is a high performance differential 2−to−1 Clock or Data multiplexer with a selectable Equalizer receiver. When placed in series with a Clock /Data path operating up to 7 GHz or 10.7 Gb/s, respectively, the NB7VQ58M inputs will compensate the degraded signal transmitted across an FR4 PCB backplane or cable interconnect. Therefore, the serial data rate is increased by reducing Inter −Symbol Interference (ISI) caused by losses in copper interconnect or long cables. The EQualizer ENable pin (EQEN) allows the INn/INn inputs to either flow through or bypass the Equalizer section. Control of the Equalizer function is realized by setting EQEN; When EQEN is set Low, the INn / INn inputs bypass the Equalizer. When EQEN is set High, the INn / INn inputs flow through the Equalizer. The default state at startup is LOW. As such, the NB7VQ58M is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock/Data distribution applications. The differential inputs incorporate internal 50 W termination resistors that are accessed through the VT pin. This feature allows the NB7VQ58M to accept various logic level standards, such as LVPECL, CML or LVDS. The NB7VQ58M produces minimal Clock or Data jitter operating up to 7 GHz or 10.7 Gb/s, respectively. The 16 mA differential CML outputs provide matching internal 50 W terminations and 400 mV output swings when externally terminated with a 50 W resistor to VCC. The NB7VQ58M is offered in a low profile 3mm x 3 mm 16−pin QFN package and is a member of the GigaComm™ family of high performance Clock / Data products. Application notes, models, and support documentation are available at www.onsemi.com.
Features
1 QFN−16 MN SUFFIX CASE 485G A L Y W G
NB7V Q58M ALYW G G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package
(Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D.
SIMPLIFIED BLOCK DIAGRAM
VCC EQ
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet.
• • • • • • •
Maximum Input Data Rate > 10.7 Gb/s Data Dependent Jitter < 15 ps Maximum Input Clock Frequency > 7 GHz Random Clock Jitter < 0.8 ps RMS Selectable Input Equalization 180 ps Typical Propagation Delay 35 ps Typical Rise and Fall Times
• Differential CML Outputs, 400 mV Peak−to−Peak, • • •
Typical Operating Range: VCC = 1.71 V to 3.6 V with GND = 0V Internal 50 W Input Termination Resistors This is a Pb−Free Device
© Semiconductor Components Industries, LLC, 2009
August, 2009 − Rev. 0
1
Publication Order Number: NB7VQ58M/D
NB7VQ58M
Exposed Pad (EP) Multi−Level Inputs LVPECL, LVDS, CML IN0 50 W VT0 50 W IN0 IN1 50 W VT1 50 W IN1 SEL 75 kW 0
VT0 GND GND VCC 16 IN0 1 IN0 IN1 2 NB7VQ58M 3 15 14 13 12 Q
11 GND 10 GND 9 Q
2:1 Mux 1 VCC EQ
0
2:1 Mux 1
Q Q
IN1 4 5 6 7 8
VT1 SEL EQEN VCC
EQEN (Equalizier Enable) VCC GND 75 kW
Figure 1. Pin Configuration (Top View) Table 1. EQualizer ENable FUNCTION
EQEN 0 1 Function INn / INn Inputs By−pass the EQualizer section Inputs flow through the EQualizer
Figure 2. Detailed Block Diagram Table 2. SELect FUNCTION TRUTH TABLE
SEL L H Q D0 D1 Q D0 D1
Table 3. PIN DESCRIPTION
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 − Name IN0 IN0 IN1 IN1 VT1 SEL EQEN VCC Q GND GND Q VCC GND GND VT0 EP I/O LVPECL, CML, LVDS Input LVPECL, CML, LVDS Input LVPECL, CML, LVDS Input LVPECL, CML, LVDS Input − LVTTL/LVCMOS Input LVCMOS Input − CML Output − − CML Output − − − − − Noninverted Differential Input (Note 1) Inverted Differential Input (Note 1) Noninverted Differential Input (Note 1) Inverted Differential Input (Note 1) Internal 50 W Termination Pin for IN1/IN1 SEL Input. Low for IN0 inputs, High for IN1 inputs. (Note 1) Pin will default HIGH when left open (has internal pullup resistor) Equalizer Enable Input; pin will default LOW when left open (has internal pulldown resistor) Positive Supply Voltage (Note 2) Inverted Differential Output Negative Supply Voltage Negative Supply Voltage Noninverted Differential Output Positive Supply Voltage (Note 2) Negative Supply Voltage Negative Supply Voltage Internal 50 W Termination Pin for IN0/IN0 The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is electrically connected to the die, and must be electrically and thermally connected to GND on the PC board. Description
1. In the differential configuration when the input termination pins (VT0, VT1) are connected to a common termination voltage or left open, and if no signal is applied on IN0/IN0, IN1/IN1 inputs, then the device will be susceptible to self−oscillation. Q/Q outputs have internal 50 W source termination resistors. 2. All VCC and GND pins must be externally connected to a power supply for proper operation.
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NB7VQ58M
Table 4. ATTRIBUTES
Characteristics ESD Protection RPU − SEL Input Pull−up Resistor Moisture Sensitivity (Note 3) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. QFN−16 Oxygen Index: 28 to 34 Human Body Model Machine Model Value > 2 kV > 200 V 25 kW Level 1 UL 94 V−0 @ 0.125 in 312
Table 5. MAXIMUM RATINGS
Symbol VCC VIN VINPP IOUT IIN TA Tstg qJA qJC Tsol Parameter Positive Power Supply Positive Input Voltage Differential Input Voltage |INn − INn| Output Current Input Current Through RT (50 W Resistor) Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction−to−Ambient) (Note 4) Thermal Resistance (Junction−to−Case) (Note 4) Wave Solder Pb−Free 0 LFPM 500 LFPM QFN−16 QFN−16 QFN−16 Continuous Surge Condition 1 GND = 0 V GND = 0 V Condition 2 Rating 4.0 −0.5 to VCC +0.5 1.89 34 40 $40 −40 to +85 −65 to +150 42 35 4 265 Unit V V V mA mA °C °C °C/W °C/W °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB7VQ58M
Table 6. DC CHARACTERISTICS POSITIVE CML OUTPUT (VCC = 1.71 V to 3.6 V; GND = 0 V; TA = −40°C to 85°C) (Note 5)
Symbol POWER SUPPLY CURRENT ICC VOH Power Supply Current (Inputs and Outputs Open) 100 150 mA Characteristic Min Typ Max Unit
CML OUTPUTS (Note 6) Output HIGH Voltage VCC = 3.3 V VCC = 2.5 V VCC = 1.8 V VCC = 3.3 V VCC = 2.5 V VCC = 1.8 V VCC – 30 3270 2470 1770 VCC – 500 2800 2000 1300 VCC – 5 3295 2495 1795 VCC – 400 2900 2100 1400 VCC 3300 2500 1800 VCC – 300 3000 2200 1500 mV
VOL
Output LOW Voltage
mV
DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED (Note 7) (Figures 6 & 8) Vth VIH VIL VISE VIHD VILD VID VCMR IIH IIL VIH VIL IIH IIL RTIN RTOUT Input Threshold Reference Voltage Range (Note 8) Single−ended Input HIGH Voltage Single−ended Input LOW Voltage Single−ended Input Voltage (VIH − VIL) Differential Input HIGH Voltage Differential Input LOW Voltage Differential Input Voltage (VIHD − VILD) Input Common Mode Range (Differential Configuration, Note 10) (Figure 10) Input HIGH Current (VTn Open) Input LOW Current (VTn Open) 1050 Vth + 100 GND 200 VCC − 100 VCC Vth − 100 1200 mV mV mV mV
DIFFERENTIAL IN0/IN0, IN1/IN1, INPUTS DRIVEN DIFFERENTIALLY (Figures 7 & 9) (Note 9) 1100 GND 100 1050 −150 −150 VCC VCC − 100 1200 VCC − 50 150 150 mV mV mV mV mA mA
CONTROL INPUT (SEL, EQEN) Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current VCC x 0.65 GND −150 −200 VCC VCC x 0.35 +150 +200 mV mV mA mA
TERMINATION RESISTORS Internal Input Termination Resistor Internal Output Termination Resistor 45 45 50 50 55 55 W W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary 1:1 with VCC. 6. CML outputs loaded with 50 W to VCC for proper operation. 7. Vth, VIH, VIL and VISE parameters must be complied with simultaneously. 8. Vth is applied to the complementary input when operating in single−ended mode. 9. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. 10. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input signal.
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NB7VQ58M
Table 7. AC CHARACTERISTICS (VCC = 1.71 V to 3.6 V; GND = 0 V; TA = −40°C to 85°C) (Note 11)
Symbol fMAX fDATAMAX fSEL VOUTPP tPLH, tPHL tPLH TC tskew tDC tJITTER Maximum Input Clock Frequency Maximum Operating Data Rate (PRBS23) Maximum Toggle Frequency, SEL Output Voltage Amplitude EQEN = 0 or 1 (Note 12) (Figures 3 and 11) Propagation Delay to Differential Outputs, @ 1 GHz, measured at differential cross−point EQEN = 0 or 1 Propagation Delay Temperature Coefficient Device − Device skew (tpdmax – tpdmin) Output Clock Duty Cycle (Reference Duty Cycle = 50%) RMS Random Clock Jitter (Note 13) Peak−to−Peak Data Dependent Jitter (Note 14) fin v 5.0 GHz fin v 7.0 GHz fin v 7.0 GHz fin v 10.7 Gbps EQEN = 0 (v 3” FR4) EQEN = 1 (12” FR4) 10 kHz 100 kHz 1 MHz 10 MHz 20 MHz 40 MHz −135 −136 −150 −151 −151 −151 35 0.7 100 Q, Q 15 35 1200 50 45 40 50 50 0.2 fin ≤ 7 GHz INn/INn to Q, Q SEL to Q, Q Characteristic VOUTPP ≥ 200 mV Min 7 10.7 25 200 120 5 Typ 8 12 50 400 180 13 50 50 55 60 0.8 10 10 240 22 Max Unit GHz Gbps MHz mV ps ns Dfs/°C ps % ps rms ps pk−pk dBc
FN
Phase Noise, fc = 1 GHz
t∫FN VINPP tr, tf
Integrated Phase Jitter (Figure 4) fc = 1 GHz, 12 kHz − 20 MHz Offset (RMS) Crosstalk Induced Jitter (Adjacent Channel) (Note 15) Input Voltage Swing (Differential Configuration) (Figure 11) (Note 12) Output Rise/Fall Times @ 1 GHz (20% − 80%)
fs ps RMS mV ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. Measured using a VINPPmin source, 50% duty cycle clock source. All output loading with external 50 W to VCC. Input edge rates 40 ps (20% − 80%). 12. Input and output voltage swings are single−ended measurements operating in differential mode. 13. Additive RMS jitter with 50% duty cycle clock signal. 14. Additive Peak−to−Peak data dependent jitter with input NRZ data at PRBS23 at 3 Gbps. 15. Crosstalk is measured at the output while applying two similar clock frequencies that are asynchronous with respect to each other at the inputs. 500 VOUTPP, OUTPUT VOLTAGE AMPLITUDE (mV) 450 POWER (dBc) 400 350 300 250 200 −115 −120 −125 −130 −135 −140 −145 −150 0 1 2 3 4 5 7 8 6 fin, CLOCK INPUT FREQUENCY (GHz) 9 10 −155 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 FREQUENCY OFFSET (Hz) 1.E+08
Figure 3. Output Voltage Amplitude (VOUTPP) vs. Input Frequency (fin) at Ambient Temperature (Typical)
Figure 4. Typical Phase Noise (VCC = 1.8 V, T = 255C, fc = 1 GHz)
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NB7VQ58M
VCC
INn 50 W VTn 50 W INn I
Figure 5. Input Structure
VIH Vth VIL IN Vth
IN IN
IN
Figure 6. Differential Input Driven Single−Ended
VCC Vthmax
Figure 7. Differential Inputs Driven Differentially
VIHmax VILmax VIH Vth VIL VIHmin VILmin IN IN VID = |VIHD(IN) − VILD(IN)| VIHD VILD
Vth Vthmin GND
Figure 8. Vth Diagram
Figure 9. VID − Differential Inputs Driven Differentially
VCC VCMRmax
VIHDmax VILDmax IN
IN IN VINPP = VIH(IN) − VIL(IN)
VCMR
IN
VIHDtyp VID = VIHD − VILD VILDtyp VIHDmin VILDmin
Q Q tPLH VOUTPP = VOH(Q) − VOL(Q) tPHL
VCMRmin GND
Figure 10. VCMR Diagram
Figure 11. AC Reference Measurement
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NB7VQ58M
VCC
VT FR4 − 12 Inch Backplane
NB7VQ58M EQualizer EQEN = 1
Driver
Q
IN IN
Q
DJ1
DJ2
DJ3
Figure 12. Typical NB7VQ58M Equalizer Application and Interconnect with PRBS23 pattern at 6.5 Gbps, EQEN = 1
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NB7VQ58M
VCC VCC VCC VCC
ZO = 50 W LVPECL Driver
NB7VQ58M INx 50 W LVDS Driver
ZO = 50 W
NB7VQ58M INx 50 W
VT = VCC − 2 V ZO = 50 W INx 50 W
VT = Open ZO = 50 W INx 50 W
GND
GND
GND
GND
Figure 13. LVPECL Interface
VCC VCC VCC
Figure 14. LVDS Interface
VCC
ZO = 50 W CML Driver
NB7VQ58M INx 50 W 50 W INx Differential Driver
ZO = 50 W
NB7VQ58M INx 50 W
VT = VCC ZO = 50 W
VT = VREFAC* ZO = 50 W INx 50 W
GND
GND
GND
GND
Figure 15. Standard 50 W Load CML Interface
Figure 16. Capacitor−Coupled Differential Interface (VT Connected to External VREFAC)
*VREFAC Bypassed to Ground with 0.01 mF Capacitor Receiver VCC (Receiver)
NB7VQ58M VCC
50 W
50 W
Q Q
50 W
50 W
16 mA GND
(see Application Note AND8173)
Figure 17. Typical CML Output Structure and Termination ORDERING INFORMATION
Device NB7VQ58MMNG NB7VQ58MMNHTBG NB7VQ58MMNTXG Package QFN−16 (Pb−Free) QFN−16 (Pb−Free) QFN−16 (Pb−Free) Shipping† 123 Units / Rail 100 / Tape & Reel 3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NB7VQ58M
PACKAGE DIMENSIONS
16 PIN QFN CASE 485G−01 ISSUE D
D A B L L1 DETAIL A E
EXPOSED Cu ALTERNATE TERMINAL CONSTRUCTIONS
L
PIN 1 LOCATION
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG
0.15 C 0.15 C
TOP VIEW
A1
0.10 C
DETAIL B
(A3) A
DETAIL B
ALTERNATE CONSTRUCTIONS
16 X
0.08 C SIDE VIEW A1 C
SEATING PLANE
16X
L
DETAIL A 5 4
D2
8
e
EXPOSED PAD 9
0.575 0.022
NOTE 5
16X
K
1 16 16X 13
E2
12
e
3.25 0.128
b BOTTOM VIEW 0.50 0.02
0.10 C A B 0.05 C
NOTE 3
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
GigaComm is a trademark of Semiconductor Component Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
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ÇÇ ÉÉ ÉÉ
ÉÉ ÉÉ ÉÉ
ÇÇÇ ÇÇÇ
MOLD CMPD
A3
DIM A A1 A3 b D D2 E E2 e K L L1
MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.18 TYP 0.30 0.50 0.00 0.15
SOLDERING FOOTPRINT*
3.25 0.128 0.30 0.012
EXPOSED PAD
1.50 0.059
0.30 0.012
SCALE 10:1 mm inches
NB7VQ58M/D
