NBSG11
2.5V/3.3V SiGe 1:2
Differential Clock Driver
with RSECL* Outputs
*Reduced Swing ECL
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Description
The NBSG11 is a 1−to−2 differential fanout buffer, optimized for
low skew and Ultra−Low JITTER.
Inputs incorporate internal 50 W termination resistors and accept
Negative ECL (NECL), Positive ECL (PECL), CML, LVCMOS,
LVTTL, or LVDS. Outputs are Reduced Swing ECL (RSECL),
400 mV. All outputs loaded with 50 W to VCC − 2 V.
Features
•
•
•
•
•
•
•
•
•
•
Maximum Input Clock Frequency up to 12 GHz Typical
Maximum Input Data Rate up to 12 Gb/s Typical
30 ps Typical Rise and Fall Times
125 ps Typical Propagation Delay
RSPECL Output with Operating Range: VCC = 2.375 V to 3.465 V
with VEE = 0 V
RSNECL Output with RSNECL or NECL Inputs with
Operating Range: VCC = 0 V with VEE = −2.375 V to −3.465 V
RSECL Output Level (400 mV Peak−to−Peak Output), Differential
Output Only
50 W Internal Input Termination Resistors
Compatible with Existing 2.5 V/3.3 V LVEP, EP, and LVEL Devices
These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2014
June, 2014 − Rev. 17
1
MARKING DIAGRAM*
ÇÇ
ÇÇ
16
1
1
QFN16
MN SUFFIX
CASE 485G
A
L
Y
W
G
SG
11
ALYWG
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
Publication Order Number:
NBSG11/D
NBSG11
VTCLK
1
CLK
2
VEE
NC
NC
VCC
16
15
14
13
Exposed Pad (EP)
12
Q0
11
Q0
NBSG11
CLK
3
10
Q1
VTCLK
4
9
Q1
5
6
7
8
VEE
NC
NC
VCC
Figure 1. QFN16 Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
1
VTCLK
−
2
CLK
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Inverted Differential Input. Internal 75 kW to VEE and 36.5 kW to VCC.
3
CLK
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Noninverted Differential Input. Internal 75 kW to VEE.
Internal 50 W Termination Pin. See Table 2.
4
VTCLK
−
Internal 50 W Termination Pin. See Table 2.
5,16
VEE
−
Negative Supply Voltage
6,7,14,15
NC
−
No Connect
8,13
VCC
−
Positive Supply Voltage
9
Q1
RSECL Output
Inverted Differential Output 1. Typically Terminated with 50 W to VTT = VCC − 2.0 V.
10
Q1
RSECL Output
Noninverted Differential Output 1. Typically Terminated with 50 W to VTT = VCC − 2.0 V.
11
Q0
RSECL Output
Inverted Differential output 0. Typically Terminated with 50 W to VTT = VCC − 2.0 V.
12
Q0
RSECL Output
Noninverted Differential Output 0. Typically Terminated with 50 W to VTT = VCC − 2.0 V.
−
EP
−
The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die
for improved heat transfer out of package. The exposed pad must be attached to a heat−
sinking conduit. The pad is not electrically connected to the die but may be electrically
and thermally connected to VEE on the PC board.
1. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad on package
bottom (see case drawing) must be attached to a heat−sinking conduit.
2. In the differential configuration when the input termination pins (VTCLK, VTCLK) are connected to a common termination voltage, and
if no signal is applied then the device will be susceptible to self−oscillation.
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NBSG11
VCC
VTCLK
Q1
36.5 KW
50 W
Q1
CLK
CLK
50 W
75 KW
Q0
75 KW
Q0
VTCLK
VEE
Figure 2. Logic Diagram
Table 2. INTERFACING OPTIONS
INTERFACING OPTIONS
CONNECTIONS
CML
Connect VTCLK and VTCLK to VCC
LVDS
Connect VTCLK and VTCLK together
AC−COUPLED
Bias VTCLK and VTCLK Inputs within
(VIHCMR) Common Mode Range
RSECL, PECL, NECL
Standard ECL Termination Techniques
LVTTL, LVCMOS
An external voltage should be be applied to the
unused complementary differential input.
Nominal voltage is 1.5 V for LVTTL and VCC/2
for LVCMOS inputs.
Table 3. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor (CLK, CLK)
75 kW
Internal Input Pullup Resistor (CLK)
ESD Protection
36.5 kW
Human Body Model
Machine Model
> 2 kV
> 100 V
Pb−Free
Level 1
Moisture Sensitivity (Note 3)
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
UL 94 V−0 @ 0.125 in
125
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
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NBSG11
Table 4. MAXIMUM RATINGS
Rating
Unit
VCC
Symbol
Positive Power Supply
Parameter
VEE = 0 V
Condition 1
3.6
V
VEE
Negative Power Supply
VCC = 0 V
−3.6
V
VI
Positive Input
Negative Input
VEE = 0 V
VCC = 0 V
3.6
−3.6
V
V
VINPP
Differential Input Voltage
2.8
|VCC − VEE|
V
V
Iout
Output Current
25
50
mA
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
qJA
Thermal Resistance (Junction−to−Ambient)
(Note 4)
0 lfpm
500 lfpm
qJC
Thermal Resistance (Junction−to−Case)
2S2P (Note 4)
Tsol
Wave Solder
|D − D|
VCC − VEE w
VCC − VEE <
Condition 2
VI ≤ VCC
VI ≥ VEE
2.8 V
2.8 V
Continuous
Surge
Pb−Free
−65 to +150
°C
41.6
35.2
°C/W
°C/W
4.0
°C/W
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NBSG11
Table 5. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT VCC = 2.5 V; VEE = 0 V (Note 5)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
45
60
75
45
60
75
45
60
75
mA
POWER SUPPLY CURRENT
IEE
Negative Power Supply Current
RSPECL OUTPUTS (Note 6)
VOH
Output HIGH Voltage
1450
1530
1575
1525
1565
1600
1550
1590
1625
mV
VOUTPP
Output Voltage Amplitude
350
410
525
350
410
525
350
410
525
mV
DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE−ENDED (Figures 4 & 6) (Note 7)
VIH
Input HIGH Voltage
1200
VCC
1200
VCC
1200
VCC
mV
VIL
Input LOW Voltage
0
VIH −
150
0
VIH −
150
0
VIH −
150
mV
Vth
Input Threshold Reference Voltage
Range (Note 8)
950
VCC
–75
950
VCC
–75
950
VCC
–75
mV
VISE
Single−Ended Input Voltage (VIH –
VIL)
150
2600
150
2600
150
260
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 5 & 7) (Note 9)
VIHD
Differential Input HIGH Voltage
1200
VCC
1200
VCC
1200
VCC
mV
VILD
Differential Input LOW Voltage
0
VCC −
75
0
VCC −
75
0
VCC −
75
mV
VID
Differential Input Voltage
(VIHD – VILD)
75
2600
75
2600
75
2600
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Note 10) (Figure 8)
1200
2500
1200
2500
1200
2500
mV
IIH
Input HIGH Current (@VIH)
80
150
80
150
80
150
mA
IIL
Input LOW Current (@VIL)
25
100
25
100
25
100
mA
50
55
50
55
50
55
W
TERMINATION RESISTORS
RTIN
Internal Input Termination Resistor
45
45
45
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with VCC.
6. All loading with 50 W to VCC − 2 V.
7. Vth, VIH, VIL, and VISE parameters must be complied with simultaneously.
8. Vth is applied to the complementary input when operating in single−ended mode. Vth = (VIH − VIL) / 2.
9. VIHD, VILD, VID and VIHCMR parameters must be complied with simultaneously.
10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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NBSG11
Table 6. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT VCC = 3.3 V; VEE = 0 V (Note 11)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
45
60
75
45
60
75
45
60
75
mA
POWER SUPPLY CURRENT
IEE
Negative Power Supply Current
RSPECL OUTPUTS (Note 12)
VOH
Output HIGH Voltage
2250
2330
2375
2325
2365
2400
2350
2390
2425
mV
VOUTPP
Output Voltage Amplitude
350
410
525
350
410
525
350
410
525
mV
DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE−ENDED (Figures 4 & 6) (Note 13)
VIH
Input HIGH Voltage
1200
VCC
1200
VCC
1200
VCC
mV
VIL
Input LOW Voltage
0
VIH −
150
0
VIH −
150
0
VIH −
150
mV
Vth
Input Threshold Reference Voltage
Range (Note 14)
950
VCC
–75
950
VCC
–75
950
VCC
–75
mV
VISE
Single−Ended Input Voltage (VIH –
VIL)
150
2600
150
2600
150
260
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 5 & 7) (Note 15)
VIHD
Differential Input HIGH Voltage
1200
VCC
1200
VCC
1200
VCC
mV
VILD
Differential Input LOW Voltage
0
VCC −
75
0
VCC −
75
0
VCC −
75
mV
VID
Differential Input Voltage
(VIHD – VILD)
75
2600
75
2600
75
2600
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Note 16) (Figure 8)
1200
3300
1200
3300
1200
3300
mV
IIH
Input HIGH Current (@VIH)
80
150
80
150
80
150
mA
IIL
Input LOW Current (@VIL)
25
100
25
100
25
100
mA
50
55
50
55
50
55
W
TERMINATION RESISTORS
RTIN
Internal Input Termination Resistor
45
45
45
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
11. Input and output parameters vary 1:1 with VCC.
12. All loading with 50 W to VCC − 2 V.
13. Vth, VIH, VIL, and VISE parameters must be complied with simultaneously.
14. Vth is applied to the complementary input when operating in single−ended mode. Vth = (VIH − VIL) / 2.
15. VIHD, VILD, VID and VIHCMR parameters must be complied with simultaneously.
16. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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NBSG11
Table 7. DC CHARACTERISTICS, NECL or RSNECL INPUT WITH NECL OUTPUT VCC = 0 V; VEE = −3.465 V to −2.375 V
(Note 17)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
45
60
75
45
60
75
45
60
75
mA
−1050
−970
−925
−975
−935
−900
−950
−910
−875
mV
350
410
525
350
410
525
350
410
525
mV
POWER SUPPLY CURRENT
IEE
Negative Power Supply Current
RSPECL OUTPUTS (Note 18)
VOH
Output HIGH Voltage
VOUTPP
Output Voltage Amplitude
DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE−ENDED (Figures 4 & 6) (Note 19)
VIH
Input HIGH Voltage
VEE +
1200
VCC
VEE +
1200
VCC
VEE +
1200
VCC
mV
VIL
Input LOW Voltage
VEE
VIH −
150
VEE
VIH −
150
VEE
VIH −
150
mV
Vth
Input Threshold Reference Voltage
Range (Note 20)
VEE +
950
VCC
–75
VEE +
950
VCC
–75
VEE +
950
VCC
–75
mV
VISE
Single−Ended Input Voltage (VIH –
VIL)
150
2600
150
2600
150
260
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 5 & 7) (Note 21)
VIHD
Differential Input HIGH Voltage
VEE +
1200
VCC
VEE +
1200
VCC
VEE +
1200
VCC
mV
VILD
Differential Input LOW Voltage
VEE
VCC −
75
VEE
VCC −
75
VEE
VCC −
75
mV
VID
Differential Input Voltage
(VIHD – VILD)
75
2600
75
2600
75
2600
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Note 22) (Figure 8)
VEE +
1200
0
VEE +
1200
0
VEE +
1200
0
mV
IIH
Input HIGH Current (@VIH)
80
150
80
150
80
150
mA
IIL
Input LOW Current (@VIL)
25
100
25
100
25
100
mA
50
55
50
55
50
55
W
TERMINATION RESISTORS
RTIN
Internal Input Termination Resistor
45
45
45
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
17. Input and output parameters vary 1:1 with VCC.
18. All loading with 50 W to VCC − 2 V.
19. Vth, VIH, VIL, and VISE parameters must be complied with simultaneously.
20. Vth is applied to the complementary input when operating in single−ended mode. Vth = (VIH − VIL) / 2.
21. VIHD, VILD, VID and VIHCMR parameters must be complied with simultaneously.
22. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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NBSG11
Table 8. AC CHARACTERISTICS VCC = 0 V; VEE = −3.465 V to −2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V
−40°C
Characteristic
Symbol
fmax
Maximum Input Clock Frequency
(See Figure 3. Fmax/JITTER) (Note 23)
tPLH,
tPHL
Propagation Delay to
Output Differential
tSKEW
Duty Cycle Skew (Note 24)
Within−Device Skew (Note 25)
Device−to−Device Skew (Note 26)
tJITTER
RMS Random Clock Jitter
25°C
Min
Typ
Max
10.5
12
90
125
160
3
6
25
0.2
85°C
Min
Typ
Max
Min
Typ
10.5
12
90
125
160
15
15
50
3
6
25
1
0.2
Max
10.5
12
90
125
160
ps
15
15
50
3
6
25
15
15
50
ps
1
0.2
1
Unit
GHz
ps
fin < 10 GHz
Peak−to−Peak Data Dependent Jitter
fin < 10 Gb/s
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 27)
tr
tf
Output Rise/Fall Times
(20% − 80%) @ 1 GHz
10.7
75
Q, Q
15
30
10.7
2600
75
55
20
30
10.7
2600
75
55
20
30
2600
mV
55
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
23. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V for QFN package. For minimum fmax
value of 10.5 GHz, output amplitude is approximately 200 mV (as shown in Figure 3, where output P−P spec is shown as a
minimum/guarantee of around 150 mV). Input edge rates 40 ps (20% − 80%).
24. See Figure 9. tSKEW = |tPLH − tPHL| for a nominal 50% Differential Clock Input Waveform.
25. Within−Device skew is defined as identical transitions on similar paths through a device.
26. Device−to−device skew for identical transitions at identical VCC levels.
27. VINPP (MAX) cannot exceed VCC − VEE.
OUTPUT VOLTAGE AMPLITUDE (mV)
600
500
OUTPUT AMP.
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400
OUTPUT P−P SPEC
300
200
100
0
1
2
3
4
5
6
7
8
9
INPUT FREQUENCY (GHz)
10
11
12
Figure 3. Output Amplitude (VOUTPP) vs. Input Frequency (FIN) at Ambient Temperature (Typical)
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NBSG11
IN
VIH
Vth
IN
VIL
IN
IN
Vth
Figure 4. Differential Input Driven
Single−Ended
VCC
Vthmax
Figure 5. Differential Inputs
Driven Differentially
VIHmax
VILmax
Vth
IN
Vthmin
VEE
VIH
Vth
VIL
IN
IN
VID = |VIHD(IN) − VILD(IN)|
VIHD
VILD
VIHmin
VILmin
Figure 6. Vth Diagram
Figure 7. Differential Inputs Driven Differentially
VCC
VIHDmax
VIHCMRmax
VILDmax
VIHCMR
VIHDtyp
VID = VIHD − VILD
IN
IN
VILDtyp
VIHDmin
VIHCMRmin
VILDmin
VEE
Figure 8. VIHCMR Diagram
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NBSG11
CLK
VINPP = VIH(CLK) − VIL(CLK)
CLK
Q
VOUTPP = VOH(Q) − VOL(Q)
Q
tPLH
tPHL
Figure 9. AC Reference Measurement
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
Zo = 50 W
D
50 W
50 W
VTT
VTT = VCC − 2.0 V (QFN)
Figure 10. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
Package
Shipping†
NBSG11MNG
QFN16
(Pb−Free / Halide−Free)
123 Units / Tube
NBSG11MNR2G
QFN16
(Pb−Free / Halide−Free)
3000 / Tape & Reel
NBSG11MNHTBG
QFN16
(Pb−Free / Halide−Free)
100 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NBSG11
PACKAGE DIMENSIONS
QFN16 3x3, 0.5P
CASE 485G
ISSUE F
D
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
PIN 1
LOCATION
0.10 C
2X
L1
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
E
ÉÉÉ
ÉÉÉ
TOP VIEW
DETAIL B
0.05 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L
L
EXPOSED Cu
0.10 C
2X
A
B
(A3)
ÉÉ
ÉÉ
ÇÇ
MOLD CMPD
A3
A1
DETAIL B
A
0.05 C
ALTERNATE
CONSTRUCTIONS
NOTE 4
A1
SIDE VIEW
C
SEATING
PLANE
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
MILLIMETERS
MIN
NOM MAX
0.80
0.90
1.00
0.00
0.03
0.05
0.20 REF
0.18
0.24
0.30
3.00 BSC
1.65
1.75
1.85
3.00 BSC
1.65
1.75
1.85
0.50 BSC
0.18 TYP
0.30
0.40
0.50
0.00
0.08
0.15
RECOMMENDED
SOLDERING FOOTPRINT*
16X
0.10 C A B
16X
L
DETAIL A
0.58
PACKAGE
OUTLINE
D2
8
4
1
9
2X
E2
16X
2X
1.84 3.30
K
1
16X
16
e
e/2
BOTTOM VIEW
0.30
16X
b
0.50
PITCH
0.10 C A B
0.05 C
NOTE 3
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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