NBSG72A
2.5V/3.3VSiGe Differential
2 X 2 Crosspoint Switch
with Output Level Select
The NBSG72A is a high−bandwidth fully differential 2 X 2
crosspoint switch with Output Level Select (OLS) capabilities. This is
a part of the GigaComm family of high performance Silicon
Germanium products. The device is housed in a low profile 3 X 3 mm
16−pin QFN package.
Differential inputs incorporate internal 50 termination resistors
and accept NECL (Negative ECL), PECL (Positive ECL),
LVCMOS/LVTTL, CML, or LVDS. The OLS input is used to
program the peak−to−peak output amplitude between 0 mV and
800 mV in five discrete steps. The SELECT inputs are single−ended
and can be driven with either LVECL or LVCMOS/LVTTL
input levels.
•
•
•
•
•
•
•
MARKING
DIAGRAM*
ÇÇ
ÇÇ
16
1
1
QFN−16
MN SUFFIX
CASE 485G
SG
72A
ALYW
Maximum Input Clock Frequency > 7 GHz Typical
Maximum Input Data Rate > 7 Gb/s Typical
A
L
Y
W
200 ps Typical Propagation Delay (OLS = FLOAT)
55/45 ps Typical Rise/Fall Times (OLS = FLOAT)
Selectable Swing PECL Output with Operating Range:
VCC = 2.375 V to 3.465 V with VEE = 0 V
Selectable Swing NECL Output with NECL Inputs with
Operating Range: VCC = 0 V with VEE = −2.375 V to −3.465 V
Selectable Output Levels (0 mV, 200 mV, 400 mV, 600 mV or
800 mV Peak−to−Peak Output)
50 Internal Input Termination Resistors
•
• Single−Ended LVECL or LVCMOS/LVTTL Select Inputs
•
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= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
(SELA, SELB)
Pb−Free Package is Available
Semiconductor Components Industries, LLC, 2004
October, 2004 − Rev. 2
1
Publication Order Number:
NBSG72A/D
NBSG72A
Exposed Pad (EP)
VTD0
1
D0
2
VCC
Q0
Q0
OLS
16
15
14
13
12 VCC
11 Q1
NBSG72A
D0
3
10 Q1
SELA
4
9
5
6
7
VEE
D1
D1
SELB
8
VTD1
Figure 1. QFN−16 Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin No.
Name
I/O
1
VTD0
−
2
D0
LVDS, CML, ECL,
LVTTL, LVCMOS
Input
Inverted Differential Input 0.
3
D0
LVDS, CML, ECL,
LVTTL, LVCMOS
Input
Noninverted Differential Input 0.
4
SELA
LVECL, LVCMOS
Input
Select Logic Input A. Internal 75 k Pulldown to VEE.
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Description
Common Internal 50 Termination Pin for D0 and D0 Input. See Table 4. (Note 1)
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5
VEE
−
Negative Supply. All VEE Pins must be Externally Connected to Power Supply to
Guarantee Proper Operation.
6
D1
LVDS, CML, ECL,
LVTTL, LVCMOS
Input
Inverted Differential Input 1.
7
D1
LVDS, CML, ECL,
LVTTL, LVCMOS
Input
Noninverted Differential Input 1.
8
VTD1
−
9
SELB
LVECL, LVCMOS
Input
10
Q1
RSECL Output
11
Q1
RSECL Output
12
VCC
−
13
OLS
(Note 2)
Input
14
Q0
RSECL Output
15
Q0
RSECL Output
16
VCC
−
−
EP
−
Common Internal 50 Termination Pin for D1 and D1 Input. See Table 4. (Note 1)
Select Logic Input B. Internal 75 k Pulldown to VEE.
Noninverted Differential Output.
Inverted Differential Output.
Positive Supply. All VCC Pins must be Externally Connected to Power Supply to
Guarantee Proper Operation.
Input Pin for Output Level Select (OLS) See Table 3.
Noninverted Differential Output Typically Terminated with 50 Resistor to
VTT = VCC − 2.0 V.
Inverted Differential Output Typically Terminated with 50 Resistor to
VTT = VCC − 2.0 V.
Positive Supply. All VCC Pins must be Externally Connected to Power Supply to
Guarantee Proper Operation.
Exposed Pad. The thermally exposed pad on package bottom (see case drawing)
must be attached to a heat−sinking conduit.
1. In the differential configuration when the input termination pins (VTD0, VTD1) are connected to a common termination voltage, and if no signal
is applied then the device will be susceptible to self−oscillation.
2. When an output level of 400 mV is desired and VCC − VEE > 3.0 V, 2 k resistor should be connected from OLS pin to VEE.
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2
NBSG72A
VTD0
50
D0
50
2
2
D0
2
D1
2
Q0
2
Q0
D1
+
50
VTD1
50
VCC
2
SELA
Table 2. TRUTH TABLE
VEE
2
75 k
2
Q1
2
Q1
SELA
SELB
Q0
Q1
LOW
LOW
D0
D0
HIGH
LOW
D1
D0
LOW
HIGH
D0
D1
HIGH
HIGH
D1
D1
2
SELB
75 k
OLS
Figure 2. Logic/Block Diagram
Table 3. OUTPUT LEVEL SELECT (OLS)
OLS
Output Amplitude (VOUTPP)
OLS Sensitivity
VCC
800 mV
OLS − 75 mV
VCC − 0.4 V
200 mV
OLS ± 150 mV
VCC − 0.8 V
600 mV
OLS ± 100 mV
VCC − 1.2 V
0
OLS ± 75 mV
VEE (Note 3)
400 mV
OLS ± 100 mV
FLOAT
600 mV
N/A
3. When an output level of 400 mV is desired and VCC − VEE > 3.0 V, a 2 k resistor should be connected from OLS to VEE.
Table 4. INTERFACING OPTIONS
Interfacing Options
Connections
CML
Connect VTD0 and VTD1 to VCC
LVDS
VTD0 and VTD1 Should Be Left Floating.
AC−COUPLED
RSECL, PECL, NECL
LVCMOS / LVTTL
Bias VTD0 and VTD1 Inputs within Common Mode Range (VIHCMR)
Standard ECL Termination Techniques
The external voltage should be applied to the unused complementary differential input.
Nominal voltage is 1.5 V for LVTTL and VCC/2 for LVCMOS Inputs.
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3
NBSG72A
Table 5. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor (SELA, SELB)
75 k
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 50 V
> 1 kV
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Moisture Sensitivity (Note 1)
Flammability Rating
Level 1
Transistor Count
436
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 6. MAXIMUM RATINGS
Rating
Units
VCC
Symbol
Positive Power Supply
Parameter
VEE = 0 V
Condition 1
Condition 2
3.6
V
VEE
Negative Power Supply
VCC = 0 V
−3.6
V
VI
Positive Input
Negative Input
VEE = 0 V
VCC = 0 V
3.6
−3.6
V
V
VINPP
Differential Input Voltage |DX − DX|
VEE − VCC 2.8 V
VEE − VCC 2.8 V
2.8
|VCC − VEE|
V
Iout
Output Current
Continuous
Surge
25
50
mA
mA
IIN
Input Current Through RT (50 Resistor)
Static
Surge
45
80
mA
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
JA
Thermal Resistance (Junction−to−Ambient)
(Note 2)
0 lfpm
500 lfpm
QFN−16
QFN−16
42
35
°C/W
°C/W
JC
Thermal Resistance (Junction−to−Case)
(Note 2)
QFN−16
4
°C/W
Tsol
Wave Solder
< 15 sec
225
°C
VI VCC
VI VEE
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
2. JEDEC standard multilayer board − 1S2P (1 signal, 2 power).
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4
NBSG72A
Table 7. DC CHARACTERISTICS, INPUT WITH PECL OUTPUT VCC = 2.5 V; VEE = 0 V (Note 3)
−40°C
Symbol
Characteristic
IEE
Negative Power Supply Current
VOH
Output HIGH Voltage (Note 4)
VOL
Output LOW Voltage (Note 4)
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS = FLOAT)
(OLS = VCC − 1.2 V)
(OLS = VEE)
VOUTPP
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
40
55
65
40
55
65
40
55
65
mA
1460
1510
1560
1490
1540
1590
1515
1565
1615
mV
555
1235
775
1455
1005
705
1295
895
1505
1095
855
1355
1015
1555
1185
595
1270
810
1490
1040
745
1330
930
1540
1130
895
1390
1050
1590
1220
625
1295
840
1510
1065
775
1355
960
1560
1155
925
1415
1080
1610
1245
700
125
525
0
325
800
215
615
5
415
680
120
520
0
320
795
210
610
0
410
680
120
515
0
320
790
210
605
5
410
mV
Output Voltage Amplitude
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS = FLOAT)
(OLS = VCC − 1.2 V)
(OLS = VEE)
mV
VIH
Input HIGH Voltage (Single−Ended)
(Note 6)
D0, D0, D1, D1
VEE +
1275
VCC −
1000*
VCC
VEE +
1275
VCC −
1000*
VCC
VEE +
1275
VCC−
1000*
VCC
mV
VIL
Input LOW Voltage (Single−Ended)
(Note 7)
D0, D0, D1, D1
VEE
VCC−
1400*
VIH−
150
VEE
VCC−
1400*
VIH−
150
VEE
VCC−
1400*
VIH−
150
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 5)
1.2
2.5
1.2
2.5
1.2
2.5
V
RTIN
Internal Input Termination Resistor
45
50
55
45
50
55
45
50
55
IIH
Input HIGH Current (@VIH)
35
100
35
100
35
100
A
IIL
Input LOW Current (@VIL)
20
100
20
100
20
100
A
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
*Typicals used for testing purposes.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to −0.965 V.
4. All loading with 50 to VCC − 2.0 V.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
6. VIH cannot exceed VCC.
7. VIL always VEE.
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5
NBSG72A
Table 8. DC CHARACTERISTICS, INPUT WITH PECL OUTPUT VCC = 3.3 V; VEE = 0 V (Note 8)
−40°C
Symbol
Characteristic
IEE
Negative Power Supply Current
VOH
Output HIGH Voltage (Note 9)
VOL
Output LOW Voltage (Note 9)
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS = FLOAT)
(OLS = VCC − 1.2 V)
**(OLS = VEE)
VOUTPP
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
40
55
65
40
55
65
40
55
65
mA
2260
2310
2360
2290
2340
2390
2315
2365
2415
mV
1320
2030
1550
2260
1785
1470
2090
1670
2310
1875
1620
2150
1790
2360
1965
1360
2065
1585
2290
1820
1510
2125
1705
2340
1910
1660
2185
1825
2390
2000
1390
2090
1615
2315
1850
1540
2150
1735
2365
1940
1690
2210
1855
2415
2030
715
130
550
0
345
815
220
640
0
435
705
125
545
0
340
805
215
635
0
430
690
125
540
0
335
800
215
630
0
425
mV
Output Amplitude Voltage
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS = FLOAT)
(OLS = VCC − 1.2 V)
**(OLS = VEE)
mV
VIH
Input HIGH Voltage (Single−Ended)
(Note 11)
D0, D0, D1, D1
VEE +
1275
VCC −
1000*
VCC
VEE +
1275
VCC −
1000*
VCC
VEE +
1275
VCC −
1000*
VCC
mV
VIL
Input LOW Voltage (Single−Ended)
(Note 12)
D0, D0, D1, D1
VIH−
2600
VCC−
1400*
VIH−
150
VIH−
2600
VCC−
1400*
VIH−
150
VIH−
2600
VCC−
1400*
VIH−
150
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 10)
1.2
3.3
1.2
3.3
1.2
3.3
V
RTIN
Internal Input Termination Resistor
45
50
55
45
50
55
45
50
55
IIH
Input HIGH Current (@VIH)
35
100
35
100
35
100
A
IIL
Input LOW Current (@VIL)
20
100
20
100
20
100
A
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
*Typicals used for testing purposes.
**When an output level of 400 mV is desired and VCC − VEE > 3.0 V, a 2 k resistor should be connected from OLS to VEE.
8. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to −0.165 V.
9. All loading with 50 to VCC − 2.0 V.
10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
11. VIH cannot exceed VCC.
12. VIL always VEE.
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NBSG72A
Table 9. DC CHARACTERISTICS, NECL INPUT WITH NECL OUTPUT VCC = 0 V; VEE = −3.465 V to −2.375 V (Note 13)
−40°C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Negative Power Supply Current
40
55
65
40
55
65
40
55
65
mA
VOH
Output HIGH Voltage (Note 14)
−1040
−990
−840
−1010
−960
−910
−985
−935
−885
mV
VOL
Output LOW Voltage (Note 14)
−3.465 V VEE −3.0 V
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS =FLOAT)
(OLS = VCC − 1.2 V)
**(OLS = VEE)
−3.0 V < VEE −2.375 V
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS =FLOAT)
(OLS = VCC − 1.2 V)
(OLS = VEE)
Symbol
VOUTPP
Characteristic
Output Voltage Amplitude
−3.465 V VEE −3.0 V
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS = FLOAT)
(OLS = VCC − 1.2 V)
**(OLS = VEE)
−3.0 V < VEE −2.375 V
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS =FLOAT)
(OLS = VCC − 1.2 V)
(OLS = VEE)
mV
−1980
−1270
−1750
−1040
−1515
−1830
−1210
−1630
−990
−1425
−1680
−1150
−1510
−940
−1335
−1940
−1235
−1715
−1010
−1480
−1790
−1175
−1595
−960
−1390
−1640
−1115
−1475
−910
−1300
−1910
−1210
−1685
−985
−1450
−1760
−1150
−1565
−935
−1360
−1610
−1090
−1445
−885
−1270
−1945
−1265
−1725
−1045
−1495
−1795
−1205
−1605
−995
−1405
−1645
−1145
−1485
−945
−1315
−1905
−1230
−1690
−1010
−1460
−1755
−1170
−1570
−960
−1370
−1605
−1110
−1450
−910
−1280
−1875
−1205
−1660
−990
−1435
−1725
−1145
−1540
−940
−1345
−1575
−1085
−1420
−890
−1255
mV
715
130
550
0
345
815
220
640
0
435
705
125
545
0
340
805
215
635
0
430
690
125
540
0
335
800
215
630
0
425
700
125
525
0
325
800
215
615
5
415
690
120
520
0
320
795
210
610
0
410
680
120
515
0
320
790
210
605
5
410
VIH
Input HIGH Voltage (Single−Ended)
(Note 16)
D0, D0, D1, D1
VEE +
1275
VCC −
1000*
VCC
VEE +
1275
VCC −
1000*
VCC
VEE +
1275
VCC −
1000*
VCC
mV
VIL
Input LOW Voltage (Single−Ended)
(Note 17)
D0, D0, D1, D1
VIH−
2600
VCC−
1400*
VIH−
150
VIH−
2600
VCC−
1400*
VIH−
150
VIH−
2600
VCC−
1400*
VIH−
150
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 15)
0.0
V
RTIN
Internal Input Termination Resistor
50
55
50
55
50
55
IIH
Input HIGH Current (@VIH)
35
100
35
100
35
100
A
IIL
Input LOW Current (@VIL)
20
100
20
100
20
100
A
IOLS
OLS Input Current (See Figure 9)
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS = FLOAT)
(OLS = VCC − 1.2 V)
−3.0 V < VEE −2.375 V
(OLS = VEE)
−3.465 V VEE −3.0 V
*(OLS = VEE)
900
300
100
−300
300
100
5
−100
900
300
100
−300
300
100
5
−100
900
300
100
−300
300
100
5
−100
−1000
−400
−1000
−400
−1000
−400
−1500
−600
−1500
−600
−1500
−600
VEE+1.2
45
0.0
VEE+1.2
45
0.0
VEE+1.2
45
A
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
*Typicals used for testing purposes.
**When an output level of 400 mV is desired and VCC − VEE > 3.0 V, a 2 k resistor should be connected from OLS to VEE.
13. Input and output parameters vary 1:1 with VCC.
14. All loading with 50 to VCC − 2.0 V.
15. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
16. VIH cannot exceed VCC.
17. VIL always VEE.
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7
NBSG72A
Table 10. AC CHARACTERISTICS VCC = 0 V; VEE = −3.465 V to −2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V (Note 18)
−40°C
Symbol
VOUTPP
tPLH
tPHL
Min
Typ
fin < 5 GHz
400
fin 7 GHz
25°C
Min
Typ
590
450
200
250
Propagation Delay to Output Differential
D0, D1 → Q0, Q1
SELA, SELB → Q0, Q1
170
190
205
265
Propagation Delay to Output Differential
D0, D1 → Q0, Q1
SELA, SELB → Q0, Q1
170
150
Characteristic
Output Voltage Amplitude
(Note 18)
tSKEW
Duty Cycle Skew (Note 19)
Within−Device Skew
Device−to−Device Skew
tJITTER
RMS Random Clock Jitter (Note 20)
fin 7 GHz
Peak−to−Peak Data Dependent Jitter
(Note 21)
fin 7 Gb/s
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 22)
tr
tf
Output Rise/Fall Times
(20% − 80%)
@ 1 GHz
Max
Min
Typ
590
440
590
180
250
130
250
255
350
170
190
205
265
255
350
170
190
210
265
260
350
Max
Max
205
215
255
270
170
150
205
215
255
270
170
150
210
215
260
270
5.0
5.0
15
25
25
50
5.0
5.0
15
25
25
50
5.0
5.0
15
25
25
50
0.2
1.5
0.2
1.5
0.2
1.5
12
18
12
18
12
18
Unit
mV
ps
ps
ps
ps
75
(Q0, Q1)
tr
tf
85°C
2600
75
70
55
40
30
2600
75
70
55
40
30
2600
mV
ps
40
30
55
45
55
45
55
45
70
55
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
18. Measured using a 75 mV source, 50% duty cycle clock source. All loading with 50 to VCC − 2.0 V. OLS = FLOAT. Input edge rates 40 ps
(20% − 80%).
19. tSKEW = |tPLH − tPHL| for a nominal 50% differential clock input waveform.
20. Additive RMS jitter with 50% Duty Cycle clock signal at 7 GHz.
21. Additive Peak−to−Peak data dependent jitter with NRZ PRBS 231−1 data at 7 Gb/s.
22. Input Voltage Swing is a single−ended measurement operating in differential mode. VINPP (max) cannot exceed VCC − VEE.
OUTPUT VOLTAGE AMPLITUDE (mV)
900
OLS = VCC
800
700
OLS = VCC − 0.8 V = FLOAT
600
500
*OLS = VEE
400
300
OLS = VCC − 0.4 V
200
100
0
1
2
3
4
5
6
7
8
9
INPUT FREQUENCY (GHz)
Figure 3. Output Voltage Amplitude (VOUTPP) vs.
Input Clock Frequency (fin) @ Ambient Temperature (Typical)
*When an output level of 400 mV is desired and VCC − VEE > 3.0 V, a 2 k resistor should be connected from OLS to VEE.
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8
NBSG72A
D0
Input Signal
D0
Q0
Signal Path
Selected
Q0 Output
20
NBSG72A
Q1
D1
Measured
Q1 Non−Driven Output
(VNA)
SELA
Logic
Low
SELB
Yscale = 10 dB/div
Non−Driven
Input
0 dB
0
D1
Logic
High
−80
Q
Q
1
Xscale = 1 GHz/div
8
Figure 4. Channel−to−Channel Crosstalk Isolation at Ambient Temperature
(D0 to Q0 Signal Path Selected; SelA = Low, SelB = High)
D0
Non−Driven
Input
NBSG72A
D0
Q0
20
Selected
Q0 Output
0
Input Signal
Q1
D1
SELA
Logic
High
SELB
0 dB
Yscale = 10 dB/div
D1
Measured
Non−Driven Output
Q1
(VNA)
Q
Q
Logic
Low
−80
1
Xscale = 1 GHz/div
Figure 5. Channel−to−Channel Crosstalk Isolation at Ambient Temperature
(D1 to Q0 Signal Path Selected; SelA = High, SelB = Low)
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8
NBSG72A
Q0
Signal Path
D1
Input Signal
D1
Non−Driven
Q0 Selected Output
20
NBSG72A
SELA
Logic
Low
0dB
0
Q1
Yscale = 10 dB/div
D0
Non−Driven
Input D0
Measured Output
Q1 (VNA)
SELB
Logic
Low
−80
1
Q
Q
Xscale = 1 GHz/div
8
Figure 6. Channel−to−Channel Crosstalk Isolation at Ambient Temperature
(D0 to Q0 and Q1 Signal Path Selected; SelA = Low, SelB = Low)
Input Signal
NBSG72A
Measured Output
Q0 (VNA)
D0
D1
Non−Driven
Input D1
Q0
20
SELA
Logic
High
0dB
0
Q1
Signal Path
Yscale = 10 dB/div
D0
Non−Driven
Q1 Selected Output
SELB
Logic
High
−80
1
Q
Q
Xscale = 1 GHz/div
Figure 7. Channel−to−Channel Crosstalk Isolation at Ambient Temperature
(D1 to Q0 and Q1 Signal Path Selected; SelA = High, SelB = High)
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10
8
NBSG72A
Y = 75 mv/div
Total System Jitter = 17.2 ps
Input Generator Jitter = 10 ps
Device Jitter = 6.8 ps
X = 60 ps/div
Y = 80 mV/div
Figure 8. Eye Diagram at 3.2 Gb/s
(VCC − VEE = 3.3 V, OLS = FLOAT @ 25C with input pattern of 231−1 PRBS, 5000 Waveforms)
Total System Jitter = 17.2 ps
Input Generator Jitter = 10 ps
Device Jitter = 7.2 ps
X = 21 ps/div
Figure 9. Eye Diagram at 7 GBit/s
(VCC − VEE = 3.3 V, OLS = FLOAT @ 25C with input pattern of 231−1 PRBS, 5000 Waveforms)
300
200
100
IOLS (A)
0
−100
−200
−300
−400
−500
−600
−700
VCC
VCC − 400
VCC − 800
VCC − 1200
VEE
VOLS (mV)
Figure 10. Typical OLS Input Current vs. OLS Input Voltage
(VCC − VEE = 3.3 V @ 25C)
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11
NBSG72A
1000
VCC − 75
VOUTPP (mV)
800
VCC − 700
VCC − 900
600
VEE + 100
400
VCC − 250
VCC − 550
200
VCC − 1125
VCC − 1275
0
VCC
VCC − 400
VCC − 800
VCC − 1200
VEE
OLS (mV)
Figure 11. OLS Operating Area
D
VINPP = VIH(D) − VIL(D)
D
Q
VOUTPP = VOH(Q) − VOL(Q)
Q
tPHL
tPLH
Figure 12. AC Reference Measurement
Q
Zo = 50
D
Receiver
Device
Driver
Device
Q
Zo = 50
D
50
50
VTT
VTT = VCC − 2.0 V
Figure 13. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
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12
NBSG72A
ORDERING INFORMATION
Package
Shipping†
QFN−16
123 Units / Rail
NBSG72AMNG
QFN−16
(Pb−Free)
123 Units / Rail
NBSG72AMNR2
QFN−16
3000 / Tape & Reel
Device
NBSG72AMN
Board
Description
NBSG72AMNEVB
NBSG72AMN Evaluation Board
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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13
NBSG72A
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPS I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1642/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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NBSG72A
PACKAGE DIMENSIONS
D
PIN 1
LOCATION
ÇÇÇ
ÇÇÇ
ÇÇÇ
16 PIN QFN
MN SUFFIX
CASE 485G−01
ISSUE B
A
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM
MINIMUM SPACING BETWEEN LEAD TIP
AND FLAG
E
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
0.15 C
TOP VIEW
0.15 C
(A3)
0.10 C
A
16 X
0.08 C
SIDE VIEW
SEATING
PLANE
A1
C
D2
16X
e
L
5
NOTE 5
EXPOSED PAD
8
4
9
E2
16X
K
12
1
16
16X
13
b
0.10 C A B
0.05 C
e
BOTTOM VIEW
NOTE 3
SOLDERING FOOTPRINT*
0.575
0.022
3.25
0.128
0.30
0.012
EXPOSED PAD
1.50
0.059
3.25
0.128
0.50
0.02
0.30
0.012
SCALE 10:1
mm
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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15
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.18
0.30
3.00 BSC
1.65
1.85
3.00 BSC
1.65
1.85
0.50 BSC
0.20
−−−
0.30
0.50
NBSG72A
GigaComm is a trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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LITERATURE FULFILLMENT:
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Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
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Phone: 81−3−5773−3850
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For additional information, please contact your
local Sales Representative.
NBSG72A/D
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