NBXDBA017LN1TAG

NBXDBB017, NBXDBA017, NBXHBA017, NBXSBA017 3.3 V, 156.25 MHz / 312.5 MHz LVPECL Clock Oscillator The single and dual frequency crystal oscillator (XO) is designed to meet today’s requirements for 3.3 V LVPECL clock generation applications. The device uses a high Q fundamental crystal and Phase Lock Loop (PLL) multiplier to provide selectable 156.25 MHz or 312.5 MHz, ultra low jitter and phase noise LVPECL differential output. This device is a member of ON Semiconductor’s PureEdget clock family that provides accurate and precision clock solutions. Available in 5 mm x 7 mm SMD (CLCC) package on 16 mm tape and reel in quantities of 1,000. Frequency stability options available as either 50 PPM NBXDBA017, NBXSBA017, NBXHBA017 (Industrial Temperature Range) or 20 PPM NBXDBB017 (Commercial Temperature Range). Features http://onsemi.com 6 PIN CLCC LN SUFFIX CASE 848AB MARKING DIAGRAMS NBXDBA017 156.25/312.50 AWLYYWWG NBXDBB017 156.25/312.50 AWLYYWWG • • • • • • • • • LVPECL Differential Output Uses High Q Fundamental Mode Crystal and PLL Multiplier Ultra Low Jitter and Phase Noise − 0.4 ps (12 kHz − 20 MHz) Selectable Output Frequency − 156.25 MHz (default) / 312.5 MHz Hermetically Sealed Ceramic SMD Package RoHS Compliant Operating Range 3.3 V ±10% Total Frequency Stability − ±20 PPM or ±50 PPM This is a Pb−Free Device NBXSBA017 312.5 AWLYYWWG NBXHBA017 156.25 AWLYYWWG 156.25/312.5 A WL YY WW G = Output Frequency (MHz) = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package Applications • Networking • 10 Gigabit Ethernet VDD 6 CLK CLK 54 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. Crystal PLL Clock Multiplier 1 OE 2 FSEL/NC* 3 GND Figure 1. Simplified Logic Diagram * NBXSBA017 and NBXHBA017 only © Semiconductor Components Industries, LLC, 2009 March, 2009 − Rev. 2 1 Publication Order Number: NBXDBB017/D NBXDBB017, NBXDBA017, NBXHBA017, NBXSBA017 OE FSEL GND 1 2 3 6 5 4 VDD CLK CLK OE NC GND 1 2 3 6 5 4 VDD CLK CLK NBXDBA017/NBXDBB017 NBXSBA017/NBXHBA017 Figure 2. Pin Connections (Top View) Table 1. PIN DESCRIPTION Pin No. 1 2 3 4 5 6 Symbol OE I/O LVTTL/LVCMOS Control Input LVTTL/LVCMOS Control Input Power Supply Description Output Enable Pin. When left floating pin defaults to logic HIGH and output is active. See OE pin description Table 2. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ FSEL/ NC* GND CLK CLK VDD Output Frequency Select Pin. Pin will default to logic HIGH when left open. See Output Frequency Select pin description Table 3. Ground 0 V LVPECL Output LVPECL Output Power Supply Non−Inverted Clock Output. Typically loaded with 50 W receiver termination resistor to VTT = VDD − 2 V. Inverted Clock Output. Typically loaded with 50 W receiver termination resistor to VTT = VDD − 2 V. Positive power supply voltage. Voltage should not exceed 3.3 V ±10%. *NBXSBA017 and NBXHBA017 only. Table 2. OUTPUT ENABLE TRI−STATE FUNCTION OE Pin Open HIGH Level LOW Level Output Pins Active Active High Z Table 3. OUTPUT FREQUENCY SELECT FSEL Pin Open (pin will float high) HIGH Level LOW Level Output Frequency (MHz) 156.25 156.25 312.5 Table 4. ATTRIBUTES Characteristic Input Default State Resistor ESD Protection Human Body Model Machine Model Value 170 kW 2 kV 200 V Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test 1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D. Table 5. MAXIMUM RATINGS Symbol VDD Iout TA Tstg Tsol Parameter Positive Power Supply LVPECL Output Current Operating Temperature Range Storage Temperature Range Wave Solder See Figure 6 Condition 1 GND = 0 V Continuous Surge Condition 2 Rating 4.6 25 50 −40 to +85 −55 to +120 260 Units V mA °C °C °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 2 NBXDBB017, NBXDBA017, NBXHBA017, NBXSBA017 Table 6. DC CHARACTERISTICS (VDD = 3.3 V ± 10%, GND = 0 V, TA = −40°C to +85°C) (Note 2) Symbol IDD VIH VIL IIH IIL VOH VOL VOUTPP Characteristic Power Supply Current (Note 2) OE and FSEL Input HIGH Voltage OE and FSEL Input LOW Voltage Input HIGH Current Input LOW Current OE FSEL OE FSEL VDD = 3.3 V Output LOW Voltage (Note 2) VDD = 3.3 V Output Voltage Amplitude (Note 2) 2000 GND − 300 −100 −100 −100 −100 VDD−1195 2105 VDD−1945 1355 660 Conditions Min. Typ. 78 Max. 100 VDD 800 +100 +100 +100 +100 VDD−945 2355 VDD−1600 1700 Units mA mV mV mA mA mV mV mV Output HIGH Voltage (Note 2) NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Measurement taken with outputs terminated with 50 ohm to VDD−2 V. See Figure 5. http://onsemi.com 3 NBXDBB017, NBXDBA017, NBXHBA017, NBXSBA017 Table 7. AC CHARACTERISTICS (VDD = 3.3 V ± 10%, GND = 0 V, TA = −40°C to +85°C) (Note 3) Symbol fCLKOUT Df Characteristic Output Clock Frequency Conditions FSEL = HIGH FSEL = LOW Frequency Stability − NBXDBB017 − NBXDBA017/NBXSBA017/NBXHBA017 Phase−Noise Performance fCLKout = 156.25 MHz/312.5 MHz (See Figures 3 and 4) 0°C to +70°C −40°C to +85°C (Note 4) 100 Hz of Carrier 1 kHz of Carrier 10 kHz of Carrier 100 kHz of Carrier 1 MHz of Carrier 10 MHz of Carrier tjit(F) tjitter RMS Phase Jitter Cycle−to−Cycle, RMS Cycle−to−Cycle, Peak−to−Peak Period, RMS Period, Peak−to−Peak tOE/OD tDUTY_CYCLE tR tF tstart Output Enable/Disable Time Output Clock Duty Cycle (Measured at Cross Point) Output Rise Time (20% and 80%) Output Fall Time (80% and 20%) Start−up Time Aging 1st Year Every Year After 1st 48 50 250 250 1 12 kHz to 20 MHz 1000 Cycles 1000 Cycles 10,000 Cycles 10,000 Cycles −108/−102 −122/−115 −129/−122 −129/−122 −137/−131 −161/−159 0.4 1 7 0.6 5 0.9 8 30 4 20 200 52 400 400 5 3 1 Min. Typ. 156.25 312.5 ±20 ±50 ppm Max. Units MHz FNOISE dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz ps ps ps ps ps ns % ps ps ms ppm ppm NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. Measurement taken with outputs terminated with 50 ohm to VDD−2 V. See Figure 5. 4. Parameter guarantees 10 years of aging. Includes initial stability at 25°C, shock, vibration, and first year aging. http://onsemi.com 4 NBXDBB017, NBXDBA017, NBXHBA017, NBXSBA017 Figure 3. Typical Phase Noise Plot at 156.25 MHz Figure 4. Typical Phase Noise Plot at 312.5 MHz http://onsemi.com 5 NBXDBB017, NBXDBA017, NBXHBA017, NBXSBA017 Table 8. RELIABILITY COMPLIANCE Parameter Shock Mechanical Mechanical Mechanical Mechanical Solderability Vibration Standard Method MIL−STD−833, Method 2002, Condition B MIL−STD−833, Method 2003 MIL−STD−202, Method 215 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á MIL−STD−833, Method 2007, Condition A MIL−STD−833, Method 1011, Condition A Solvent Resistance Thermal Shock Environment Environment Moisture Level Sensitivity MSL1 260°C per IPC/JEDEC J−STD−020D NBXxxxxxx CLK Driver Device CLK Z o = 50 W 50 W 50 W D Z o = 50 W D Receiver Device VTT VTT = VDD − 2.0 V Figure 5. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) Temperature (°C) 260 217 temp. 260°C 20 − 40 sec. max. peak 3°C/sec. max. ramp−up 6°C/sec. max. cooling 175 150 pre−heat reflow 60180 sec. 60150 sec. Time Figure 6. Recommended Reflow Soldering Profile http://onsemi.com 6 NBXDBB017, NBXDBA017, NBXHBA017, NBXSBA017 ORDERING INFORMATION Device Order Number NBXDBB017LN1TAG NBXDBA017LN1TAG NBXSBA017LN1TAG NBXHBA017LN1TAG* NBXDBB017LNHTAG NBXDBA017LNHTAG NBXSBA017LNHTAG NBXHBA017LNHTAG* Package Type CLCC−6 (Pb−Free) CLCC−6 (Pb−Free) CLCC−6 (Pb−Free) CLCC−6 (Pb−Free) CLCC−6 (Pb−Free) CLCC−6 (Pb−Free) CLCC−6 (Pb−Free) CLCC−6 (Pb−Free) Shipping† 1000 / Tape & Reel 1000 / Tape & Reel 1000 / Tape & Reel 1000 / Tape & Reel 100 / Tape & Reel 100 / Tape & Reel 100 / Tape & Reel 100 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *Please contact sales office for availability http://onsemi.com 7 NBXDBB017, NBXDBA017, NBXHBA017, NBXSBA017 PACKAGE DIMENSIONS 6 PIN CLCC, 7x5, 2.54P CASE 848AB−01 ISSUE C D 4X A 0.15 C D1 B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. DIM A A1 A2 A3 b D D1 D2 D3 E E1 E2 E3 e H L R SEATING PLANE MIN 1.70 0.08 1.30 6.17 6.66 4.37 4.65 MILLIMETERS NOM MAX 1.80 1.90 0.70 REF 0.36 REF 0.10 0.12 1.40 1.50 7.00 BSC 6.20 6.23 6.81 6.96 5.08 BSC 5.00 BSC 4.40 4.43 4.80 4.95 3.49 BSC 2.54 BSC 1.80 REF 1.27 1.37 0.70 REF TERMINAL 1 INDICATOR E2 H E1 E D2 TOP VIEW A3 0.10 C A A1 SIDE VIEW D3 1 2 3 A2 1.17 C SOLDERING FOOTPRINT* e 6X R E3 1.50 5.06 0.10 C A B 0.05 C 6X b 6 5 4 6X L 2.54 PITCH BOTTOM VIEW 1.50 DIMENSION: MILLIMETERS 6X *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PureEdge is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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