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Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
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is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
NC7SV02
TinyLogic® ULP-A 2-Input NOR Gate
Features
Description
0.9V to 3.6V VCC Supply Operation
Extremely High Speed tPD
- 1.0ns: Typical for 2.7V to 3.6V VCC
- 1.2ns: Typical for 2.3V to 2.7V VCC
- 1.9ns: Typical for 1.65V to 1.95V VCC
- 3.2ns: Typical for 1.4V to 1.6V VCC
- 6.0ns: Typical for 1.1V to 1.3V VCC
- 13.0ns: Typical for 0.9V VCC
The NC7SV02 is a single two-input NOR gate from
Fairchild's Ultra-Low Power (ULP-A) Series of
®
TinyLogic . ULP-A is ideal for applications that require
extreme high speed, high drive, and low power. This
product is designed for a wide low-voltage operating
range (0.9V to 3.6V VCC) and applications that require
®
more drive and speed than the TinyLogic ULP series,
but still offer best-in-class, low-power operation.
3.6V Over-Voltage Tolerant I/Os at VCC from
0.9V to 3.6V
The NC7SV02 is uniquely designed for optimized power
and speed and is fabricated with an advanced CMOS
technology to achieve high-speed operation while
maintaining low CMOS power dissipation.
Power-Off High-Impedance Inputs and Outputs
High Static Drive (IOH/IOL)
- ±24mA at 3.00V VCC
- ±18mA at 2.30V VCC
- ±6mA at 1.65V VCC
- ±4mA at 1.4V VCC
- ±2mA at 1.1V VCC
- ±0.1mA at 0.9V VCC
Uses Proprietary Quiet Series™ Noise/EMI
Reduction Circuitry
Ultra-Small MicroPak™ Packages
Ultra-Low Dynamic Power
Ordering Information
Part Number
Top Mark
NC7SV02P5X
V02
NC7SV02L6X
NC7SV02FHX
Package
Packing Method
5-Lead SC70, EIAJ SC-88a, 1.25mm Wide
3000 Units on Tape & Reel
F6
6-Lead MicroPak™, 1.00mm Wide
5000 Units on Tape & Reel
F6
6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch
5000 Units on Tape & Reel
© 2002 Fairchild Semiconductor Corporation
NC7SV02 • Rev. 1.0.3
www.fairchildsemi.com
NC7SV02 — TinyLogic® ULP-A 2-Input NOR Gate
December 2010
Figure 1.
Battery Life vs. VCC Supply Voltage
Notes:
®
1. TinyLogic ULP and ULP-A with up to 50% less power consumption can extend battery life significantly.
Battery Life = (Vbattery•Ibattery•.9)/(Pdevice)/24hrs/day
where, Pdevice = (ICC • VCC) + (CPD + CL) • VCC2 • f.
2. Assumes ideal 3.6V Lithium Ion battery with current rating of 900mAH and derated 90% and device frequency at
10MHz, with CL=15pF load.
NC7SV02 — TinyLogic® ULP-A 2-Input NOR Gate
Battery Life
Connection Diagram
IEEE/IEC
Figure 2.
© 2002 Fairchild Semiconductor Corporation
NC7SV02 • Rev. 1.0.3
Logic Symbol
www.fairchildsemi.com
2
Figure 3.
SC70 (Top View)
A
1
6
VCC
B
2
5
NC
GND
3
4
Y
Figure 4.
MicroPak™ (Top Through View)
Pin Definitions
Pin # SC70
Pin # MicroPak™
Name
Description
1
1
A
2
2
B
3
3
GND
Ground
4
4
Y
Output
5
NC
No Connect
5
6
VCC
Supply Voltage
Input
Input
NC7SV02 — TinyLogic® ULP-A 2-Input NOR Gate
Pin Configurations
Function Table
Y=/A + /B
Inputs
Output
A
B
Y
L
L
H
L
H
L
H
L
L
H
H
L
H=HIGH Logic Level
L=LOW Logic Level
© 2002 Fairchild Semiconductor Corporation
NC7SV02 • Rev. 1.0.3
www.fairchildsemi.com
3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
VCC
Supply Voltage
-0.5
4.6
V
VIN
DC Input Voltage
-0.5
4.6
V
-0.5
VCC + 0.5
-0.5
4.6
VOUT
IIK
DC Input Diode Current
IOK
DC Output Diode Current
IOH/IOL
ICC or IGND
TSTG
HIGH or LOW State
DC Output Voltage
(3)
VCC=0V
VIN < 0V
-50
VOUT < 0V
-50
VOUT > VCC
+50
V
mA
mA
DC Output Source/Sink Current
±50
mA
DC VCC or Ground Current per Supply Pin
±50
mA
+150
°C
TJ
Storage Temperature Range
Junction Temperature Under Bias
-65
+150
°C
TL
Junction Lead Temperature, Soldering 10 Seconds
+260
°C
SC70-5
PD
ESD
Power Dissipation at +85°C
150
MicroPak™-6
130
MicroPak2™-6
120
Human Body Model, JEDEC:JESD22-A114
4000
Charge Device Model, JEDEC:JESD22-C101
2000
NC7SV02 — TinyLogic® ULP-A 2-Input NOR Gate
Absolute Maximum Ratings
mW
V
Note:
3. IO absolute maximum rating must be observed.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
VCC
Supply Voltage
VIN
Input Voltage
VOUT
IOH/IOL
Output Voltage
Output Current in IOH/IOL
Conditions
Min.
Max.
Unit
0.9
3.6
V
V
0
3.6
VCC=0V
0
3.6
HIGH or LOW State
0
VCC
VCC=3.0V to 3.6V
±24
VCC=2.3V to 2.7V
±18
VCC=1.65V to 1.95V
±6
VCC=1.4V to 1.6V
±4
VCC=1.1V to 1.3V
Δt/ΔV
θJA
Operating Temperature, Free Air
Minimum Input Edge Rate
Thermal Resistance
mA
±2
VCC=0.9V
TA
V
±0.1
-40
+85
°C
VIN=0.8V to 2.0, VCC=3.0V
10
ns/V
SC70-5
425
MicroPak™-6
500
MicroPak2™-6
560
°C/W
Note:
4. Unused inputs must be held HIGH or LOW. They may not float.
© 2002 Fairchild Semiconductor Corporation
NC7SV02 • Rev. 1.0.3
www.fairchildsemi.com
4
Symbol
VIH
Parameter
VCC
HIGH Level Input
Voltage
Conditions
Min.
.65 x VCC
1.10 ≤ VCC ≤ 1.30
.65 x VCC
.65 x VCC
1.40 ≤ VCC ≤ 1.60
.65 x VCC
.65 x VCC
1.65 ≤ VCC ≤ 1.95
.65 x VCC
.65 x VCC
1.6
1.6
2.0
2.0
Max.
0.90
.35 x VCC
.35 x VCC
.35 x VCC
.35 x VCC
1.40 ≤ VCC ≤ 1.60
.35 x VCC
.35 x VCC
1.65 ≤ VCC ≤ 1.95
.35 x VCC
.35 x VCC
2.30 ≤ VCC ≤ 2.70
0.7
0.7
VCC-0.1
VCC-0.1
1.10 ≤ VCC ≤ 1.30
VCC-0.1
VCC-0.1
1.40 ≤ VCC ≤ 1.60
VCC-0.2
VCC-0.2
VCC-0.2
VCC-0.2
2.30 ≤ VCC ≤ 2.70
VCC-0.2
VCC-0.2
2.70 ≤ VCC ≤ 3.60
VCC-0.2
VCC-0.2
IOH=-100µA
1.10 ≤ VCC ≤ 1.30
IOH=-2mA
.75 x VCC
.75 x VCC
1.40 ≤ VCC ≤ 1.60
IOH=-4mA
.75 x VCC
.75 x VCC
1.65 ≤ VCC ≤ 1.95
2.30 ≤ VCC ≤ 2.70
2.30 ≤ VCC ≤ 2.70
2.70 ≤ VCC ≤ 3.60
2.30 ≤ VCC ≤ 2.70
2.70 ≤ VCC ≤ 3.60
2.70 ≤ VCC ≤ 3.60
IOH=-6mA
IOH=-12mA
IOH=-18mA
IOH=-24mA
1.25
1.25
2.00
2.00
1.8
1.8
2.2
2.2
1.7
1.7
2.4
2.4
2.2
V
0.8
0.90
1.65 ≤ VCC ≤ 1.95
HIGH Level Output
Voltage
0.8
Units
V
1.10 ≤ VCC ≤ 1.30
2.70 ≤ VCC ≤ 3.60
VOH
Max.
.65 x VCC
2.70 ≤ VCC ≤ 3.60
LOW Level Input
Voltage
Min.
TA=-40 to +85°C
0.90
2.30 ≤ VCC ≤ 2.70
VIL
TA=+25°C
NC7SV02 — TinyLogic® ULP-A 2-Input NOR Gate
DC Electrical Characteristics
V
2.2
Continued on following page…
© 2002 Fairchild Semiconductor Corporation
NC7SV02 • Rev. 1.0.3
www.fairchildsemi.com
5
Symbol
Parameter
VCC
LOW Level
Output Voltage
Min.
Max.
0.1
0.1
1.40 ≤ VCC ≤ 1.60
0.2
0.2
0.2
0.2
2.30 ≤ VCC ≤ 2.70
0.2
0.2
2.70 ≤ VCC ≤ 3.60
0.2
0.2
1.10 ≤ VCC ≤ 1.30 IOL=2mA
0.25 x VCC
0.25 x VCC
1.40 ≤ VCC ≤ 1.60 IOL=4mA
0.25 x VCC
0.25 x VCC
1.65 ≤ VCC ≤ 1.95 IOL=6mA
0.3
0.3
2.30 ≤ VCC ≤ 2.70
0.4
0.4
0.4
0.4
0.6
0.6
0.4
0.4
0.55
0.55
0 ≤ VIN ≤ 3.60
±0.1
±0.5
µA
0 ≤ (VIN, VO) ≤ 3.60
0.5
0.5
µA
VIN=VCC, or GND
0.9
0.9
IOL=100µA
IOL=12mA
IOL=18mA
2.70 ≤ VCC ≤ 3.60 IOL=24mA
Power Off
Leakage
Current
ICC
Quiescent
Supply Current
Units
1.10 ≤ VCC ≤ 1.30
2.30≤ VCC ≤ 2.70
IOFF
Max.
0.1
2.70 ≤ VCC ≤ 3.60
IIN
Min.
0.1
2.70 ≤ VCC ≤ 3.60
Input Leakage
Current
TA=-40 to +85°C
0.90
1.65 ≤ VCC ≤ 1.95
VOL
TA=+25°C
Conditions
0.90 to 3.60
0
0.90 to 3.60
VCC ≤ VIN ≤ 3.6V
±0.9
V
NC7SV02 — TinyLogic® ULP-A 2-Input NOR Gate
DC Electrical Characteristics (Continued)
µA
AC Electrical Characteristics
Symbol
Parameter
Conditions
0.90
CL=15pF, RL=1MΩ
Min.
1.10 ≤ VCC ≤ 1.30
tPHL, tPLH
Propagation
Delay
1.40 ≤ VCC ≤ 1.60
CL=15pF, RL=2kΩ
1.65 ≤ VCC ≤ 1.95
2.30 ≤ VCC ≤ 2.70
CL=30pF, RL=500Ω
2.70 ≤ VCC ≤ 3.60
CIN
Input
Capacitance
0
CPD
Power
Dissipation
Capacitance
0.90 to 3.60
© 2002 Fairchild Semiconductor Corporation
NC7SV02 • Rev. 1.0.3
TA=-40 to
+85°C
TA=+25°C
VCC
VIN=0V or VCC,
f=10MHz
Typ.
Max.
Min.
Max.
Units Figure
13
3.0
6.0
15.0
1.0
18.6
1.0
3.2
8.7
1.0
9.7
1.0
1.9
6.0
1.0
6.8
0.8
1.2
4.1
0.7
4.7
0.7
1.0
3.3
0.6
4.0
ns
2
pF
8
pF
Figure 5
Figure 6
www.fairchildsemi.com
6
NC7SV02 — TinyLogic® ULP-A 2-Input NOR Gate
AC Loadings and Waveforms
Figure 5. AC Test Circuit
Figure 6.
AC Waveforms
VCC
Symbol
3.3V ± 0.3V
2.5V ± 0.2V
1.8V ± 0.15V
1.5V ± 0.1V
1.2V ± 0.1V
0.9V
Vmi
1.5V
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
Vmo
1.5V
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
© 2002 Fairchild Semiconductor Corporation
NC7SV02 • Rev. 1.0.3
www.fairchildsemi.com
7
NC7SV02 — TinyLogic® ULP-A 2-Input NOR Gate
Physical Dimensions
Figure 7.
5-Lead, SC70, EIAJ SC-88a, 1.25mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specification
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/products/analog/pdf/sc70-5_tr.pdf.
Package Designator
P5X
© 2002 Fairchild Semiconductor Corporation
NC7SV02 • Rev. 1.0.3
Tape Section
Cavity Number
Cavity Status
Cover Type Status
Leader (Start End)
125 (Typical)
Empty
Sealed
Carrier
3000
Filled
Sealed
Trailer (Hub End)
75 (Typical)
Empty
Sealed
www.fairchildsemi.com
8
NC7SV02 — TinyLogic® ULP-A 2-Input NOR Gate
Physical Dimensions
2X
0.05 C
1.45
B
2X
(1)
0.05 C
(0.254)
(0.49)
5X
1.00
(0.75)
PIN 1 IDENTIFIER
5
(0.52)
1X
A
TOP VIEW
0.55MAX
(0.30)
6X
PIN 1
0.05 C
0.05
0.00
RECOMMENED
LAND PATTERN
0.05 C
C
0.25
0.15 6X
1.0
DETAIL A
0.10
0.05
0.45
0.35
0.10
0.00 6X
C B A
C
0.40
0.30
0.35 5X
0.25
0.40 5X
0.30
0.5
(0.05)
6X
DETAIL A
PIN 1 TERMINAL
0.075 X 45
CHAMFER
(0.13)
4X
BOTTOM VIEW
Notes:
1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD
2. DIMENSIONS ARE IN MILLIMETERS
3. DRAWING CONFORMS TO ASME Y14.5M-1994
4. FILENAME AND REVISION: MAC06AREV4
5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY
OTHER LINE IN THE MARK CODE LAYOUT.
Figure 8.
6-Lead, MicroPak™, 1.0mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specification
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf.
Package Designator
L6X
© 2002 Fairchild Semiconductor Corporation
NC7SV02 • Rev. 1.0.3
Tape Section
Cavity Number
Cavity Status
Cover Type Status
Leader (Start End)
125 (Typical)
Empty
Sealed
Carrier
5000
Filled
Sealed
Trailer (Hub End)
75 (Typical)
Empty
Sealed
www.fairchildsemi.com
9
NC7SV02 — TinyLogic® ULP-A 2-Input NOR Gate
Physical Dimensions
0.89
0.35
0.05 C
1.00
2X
B
A
5X 0.40
PIN 1
MIN 250uM
0.66
1.00
1X 0.45
6X 0.19
0.05 C
TOP VIEW
RECOMMENDED LAND PATTERN
FOR SPACE CONSTRAINED PCB
2X
0.90
0.05 C
0.35
0.55MAX
C
5X 0.52
SIDE VIEW
0.73
(0.08) 4X
1
DETAIL A
2
1X 0.57
0.09
0.19 6X
3
0.20 6X
ALTERNATIVE LAND PATTERN
FOR UNIVERSAL APPLICATION
(0.05) 6X
5X 0.35
0.25
6
5
4
0.35
0.60
(0.08)
4X
0.10
.05 C
C B A
0.40
0.30
BOTTOM VIEW
NOTES:
A. COMPLIES TO JEDEC MO-252 STANDARD
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994
D. LANDPATTERN RECOMMENDATION IS BASED ON FSC
DESIGN.
E. DRAWING FILENAME AND REVISION: MGF06AREV3
Figure 9.
0.075X45°
CHAMFER
DETAIL A
PIN 1 LEAD SCALE: 2X
6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specification
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/packaging/MicroPAK2_6L_tr.pdf.
Package Designator
FHX
© 2002 Fairchild Semiconductor Corporation
NC7SV02 • Rev. 1.0.3
Tape Section
Cavity Number
Cavity Status
Cover Type Status
Leader (Start End)
125 (Typical)
Empty
Sealed
Carrier
5000
Filled
Sealed
Trailer (Hub End)
75 (Typical)
Empty
Sealed
www.fairchildsemi.com
10
NC7SV02 — TinyLogic® ULP-A 2-Input NOR Gate
© 2002 Fairchild Semiconductor Corporation
NC7SV02 • Rev. 1.0.3
www.fairchildsemi.com
11
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regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
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