NC7SZ00P5

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This literature is subject to all applicable copyright laws and is not for resale in any manner. NC7SZ00 TinyLogic® UHS Two-Input NAND Gate Features Description ƒ Ultra-High Speed: tPD 2.4ns (Typical) into 50pF at 5V VCC ƒ ƒ ƒ ƒ ƒ High Output Drive: ±24mA at 3V VCC The NC7SZ00 is a single two-input NAND gate from Fairchild’s Ultra-High Speed (UHS) series of ® TinyLogic . The device is fabricated with advanced CMOS technology to achieve ultra-high speed with high output drive while maintaining low static power dissipation over a broad VCC operating range. The device is specified to operate over the 1.65V to 5.5V VCC operating range. The inputs and output are high impedance when VCC is 0V. Inputs tolerate voltages up to 6V, independent of VCC operating voltage. ƒ ƒ ƒ Proprietary Noise/EMI Reduction Circuitry Broad VCC Operating Range: 1.65V to 5.5V Matches Performance of LCX Operated at 3.3V VCC Power Down High-Impedance Inputs/Outputs Over-Voltage Tolerance inputs facilitate 5V to 3V Translation Ultra-Small MicroPak™ Packages Space-Saving SOT23 and SC70 Packages Related Resources ƒ MS-503 — Family Characteristics TinyLogic® HS/HST and UHS Series Ordering Information Part Number Top Mark NC7SZ00M5X 7Z00 5-Lead SOT23, JEDEC MO-178 1.6mm 3000 Units on Tape & Reel NC7SZ00P5X Z00 5-Lead SC70, EIAJ SC-88a, 1.25mm Wide 3000 Units on Tape & Reel NC7SZ00L6X YY 6-Lead MicroPak™, 1.00mm Wide 5000 Units on Tape & Reel NC7SZ00FHX YY 6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch 5000 Units on Tape & Reel © 1996 Fairchild Semiconductor Corporation NC7SZ00 • Rev. 1.0.4 Package Packing Method www.fairchildsemi.com NC7SZ00 — TinyLogic® UHS Two-Input NAND Gate December 2010 IEEE/IEC Figure 1. Logic Symbol Pin Configurations Figure 2. SC70 and SOT23 (Top View) Figure 3. MicroPak™ (Top Through View) NC7SZ00 — TinyLogic® UHS Two-Input NAND Gate Connection Diagrams Pin Definitions Pin # SC70 / SOT23 Pin # MicroPak™ Name Description 1 1 A Input 2 2 B Input 3 3 GND Ground 4 4 Y Output 5 6 VCC Supply Voltage 5 NC No Connect Function Table Inputs Output A B Y L L H L H H H L H H H L H = HIGH Logic Level L = LOW Logic Level © 1996 Fairchild Semiconductor Corporation NC7SZ00 • Rev. 1.0.4 www.fairchildsemi.com 2 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC VIN VOUT Parameter Supply Voltage 6.0 V -0.5 6.0 V 6.0 V DC Output Diode Current IOUT DC Output Current VIN < -0.5V -50 VIN > 6.0V +20 VOUT < -0.5V -50 VOUT > 6V, VCC=GND +20 DC VCC or Ground Current Storage Temperature Range -65 TJ Junction Temperature Under Bias TL Junction Lead Temperature (Soldering, 10 Seconds) ESD -0.5 -0.5 IOK PD Unit DC Input Voltage DC Input Diode Current TSTG Max. DC Output Voltage IIK ICC or IGND Min. Power Dissipation at +85°C mA mA ±50 mA ±50 mA +150 °C +150 °C +260 °C SOT-23 200 SC70-5 150 MicroPak™-6 130 MicroPak2™-6 120 Human Body Model, JEDEC:JESD22-A114 4000 Charge Device Model, JEDEC:JESD22-C101 2000 NC7SZ00 — TinyLogic® UHS Two-Input NAND Gate Absolute Maximum Ratings mW V Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VCC VIN VOUT TA tr , tf θJA Parameter Conditions Min. Max. Supply Voltage Operating 1.65 5.50 Supply Voltage Data Retention 1.5 5.5 Unit V Input Voltage 0 5.5 V Output Voltage 0 VCC V -40 +85 °C VCC at 1.8V, 2.5V ±0.2V 0 20 VCC at 3.3V ± 0.3V 0 10 VCC at 5.0V ± 0.5V 0 5 Operating Temperature Input Rise and Fall Times Thermal Resistance SOT-23 300 SC70-5 435 MicroPak™-6 500 MicroPak2™-6 560 ns/V °C/W Note: 1. Unused inputs must be held HIGH or LOW. They may not float. © 1996 Fairchild Semiconductor Corporation NC7SZ00 • Rev. 1.0.4 www.fairchildsemi.com 3 Symbol Parameter VCC Conditions Min. VIH HIGH Level Input Voltage VIL LOW Level Input Voltage HIGH Level Output Voltage 0.75VCC 0.75VCC 0.70VCC IIN Input Leakage Current Power Off ICC Quiescent Supply Current © 1996 Fairchild Semiconductor Corporation NC7SZ00 • Rev. 1.0.4 Units Max. V 1.65 to 1.95 0.25VCC 0.25VCC 2.30 to 5.50 0.30VCC 0.30VCC 1.65 1.55 1.65 1.55 1.80 1.70 1.80 1.70 VIN=VIL IOH=-100µA 2.20 2.30 2.20 3.00 2.90 3.00 2.90 4.50 4.40 4.50 4.40 1.65 IOH=-4mA 1.29 1.52 1.29 1.80 IOH=-8mA 1.90 2.15 1.90 2.30 IOH=-16mA 2.40 2.80 2.40 3.00 IOH=-24mA 2.30 2.68 2.30 4.50 IOH=-32mA 3.80 4.20 3.80 0.10 0.08 0.00 0.10 0.10 0.00 0.10 0.10 3.00 0.00 0.10 0.10 4.50 0.00 0.10 0.10 VIN=VIH IOL=100µA V V 0.00 3.00 IOFF Min. 0.70VCC 2.30 LOW Level Output Voltage Max. 1.65 to 1.95 1.65 VOL Typ. 2.30 to 5.50 2.30 VOH TA=-40 to +85°C TA=25°C V 1.65 IOL=4mA 0.80 0.24 0.24 2.30 IOL=8mA 0.10 0.30 0.30 3.00 IOL=16mA 0.15 0.40 0.40 3.00 IOL=24mA 0.22 0.55 0.55 4.50 IOL=32mA 0.22 0.55 0.55 VIN=5.5V, GND ±1 ±10 µA VIN or VOUT=5.5V 1 10 µA 2 20 µA 0 to 5.5 0 1.65 to 5.50 VIN=5.5V, GND NC7SZ00 — TinyLogic® UHS Two-Input NAND Gate DC Electrical Characteristics www.fairchildsemi.com 4 Symbol Parameter VCC TA=25°C Conditions 1.65 1.80 2.50 ± 0.20 tPHL, tPLH Propagation Delay CL=15pF, RL=1MΩ 3.30 ± 0.30 TA=-40 to +85°C Min. Typ. Max. Min. Max. 2.0 5.4 11.4 2.0 12.0 2.0 4.5 9.5 2.0 10.0 0.8 3.0 6.5 0.8 7.0 0.5 2.4 4.5 0.5 4.7 5.00 ± 0.50 0.5 2.0 3.9 0.5 4.1 3.30 ± 0.30 CL=50pF, 5.00 ± 0.50 RL=500Ω 1.5 2.9 5.0 1.5 5.2 0.8 2.4 4.3 0.8 4.5 CIN Input Capacitance 0.00 4 CPD Power Dissipation Capacitance(2) 3.30 24 5.00 30 Units Figure ns Figure 4 Figure 5 pF pF Figure 6 Note: 2. CPD is defined as the value of the internal equivalent capacitance derived from dynamic operating current consumption (ICCD) at no output lading and operating at 50% duty cycle. CPD is related to ICCD dynamic operating current by the expression: ICCD=(CPD)(VCC)(fIN)+(ICCstatic). Figure 4. AC Test Circuit NC7SZ00 — TinyLogic® UHS Two-Input NAND Gate AC Electrical Characteristics Figure 5. AC Waveforms Note: 3. Input=AC Waveform; tr=tf=1.8ns; PRR=10MHz; Duty Cycle =50%. Figure 6. ICCD Test Circuit © 1996 Fairchild Semiconductor Corporation NC7SZ00 • Rev. 1.0.4 www.fairchildsemi.com 5 NC7SZ00 — TinyLogic® UHS Two-Input NAND Gate Physical Dimensions 3.00 2.80 5 SYMM CL 0.95 0.95 A 4 B 3.00 2.60 1.70 1.50 1 2 2.60 3 (0.30) 1.00 0.50 0.30 0.95 0.20 1.90 C A B 0.70 TOP VIEW LAND PATTERN RECOMMENDATION SEE DETAIL A 1.30 0.90 1.45 MAX 0.15 0.05 0.22 0.08 C 0.10 C NOTES: UNLESS OTHEWISE SPECIFIED GAGE PLANE A) THIS PACKAGE CONFORMS TO JEDEC MO-178, ISSUE B, VARIATION AA, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) MA05Brev5 0.25 8° 0° 0.55 0.35 SEATING PLANE 0.60 REF Figure 7. 5-Lead SOT23, JEDEC MO-178 1.6mm Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Tape and Reel Specifications Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/packaging/SOT23-5L_tr.pdf. Package Designator M5X © 1996 Fairchild Semiconductor Corporation NC7SZ00 • Rev. 1.0.4 Tape Section Cavity Number Cavity Status Cover Type Status Leader (Start End) 125 (Typical) Empty Sealed Carrier 3000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed www.fairchildsemi.com 6 NC7SZ00 — TinyLogic® UHS Two-Input NAND Gate Physical Dimensions Figure 8. 5-Lead, SC70, EIAJ SC-88a, 1.25mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Tape and Reel Specifications Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/products/analog/pdf/sc70-5_tr.pdf. Package Designator P5X © 1996 Fairchild Semiconductor Corporation NC7SZ00 • Rev. 1.0.4 Tape Section Cavity Number Cavity Status Cover Type Status Leader (Start End) 125 (Typical) Empty Sealed Carrier 3000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed www.fairchildsemi.com 7 NC7SZ00 — TinyLogic® UHS Two-Input NAND Gate Physical Dimensions 2X 0.05 C 1.45 B 2X (1) 0.05 C (0.254) (0.49) 5X 1.00 (0.75) PIN 1 IDENTIFIER 5 (0.52) 1X A TOP VIEW 0.55MAX (0.30) 6X PIN 1 0.05 C 0.05 0.00 RECOMMENED LAND PATTERN 0.05 C C 0.25 0.15 6X 1.0 DETAIL A 0.10 0.05 0.45 0.35 0.10 0.00 6X C B A C 0.40 0.30 0.35 5X 0.25 0.40 5X 0.30 0.5 (0.05) 6X DETAIL A PIN 1 TERMINAL 0.075 X 45 CHAMFER (0.13) 4X BOTTOM VIEW Notes: 1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD 2. DIMENSIONS ARE IN MILLIMETERS 3. DRAWING CONFORMS TO ASME Y14.5M-1994 4. FILENAME AND REVISION: MAC06AREV4 5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY OTHER LINE IN THE MARK CODE LAYOUT. Figure 9. 6-Lead, MicroPak™, 1.0mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Tape and Reel Specifications Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf. Package Designator L6X © 1996 Fairchild Semiconductor Corporation NC7SZ00 • Rev. 1.0.4 Tape Section Cavity Number Cavity Status Cover Type Status Leader (Start End) 125 (Typical) Empty Sealed Carrier 5000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed www.fairchildsemi.com 8 NC7SZ00 — TinyLogic® UHS Two-Input NAND Gate Physical Dimensions 0.89 0.35 0.05 C 1.00 2X B A 5X 0.40 PIN 1 MIN 250uM 0.66 1.00 1X 0.45 6X 0.19 0.05 C TOP VIEW RECOMMENDED LAND PATTERN FOR SPACE CONSTRAINED PCB 2X 0.90 0.05 C 0.35 0.55MAX C 5X 0.52 SIDE VIEW 0.73 (0.08) 4X 1 DETAIL A 2 1X 0.57 0.09 0.19 6X 3 0.20 6X ALTERNATIVE LAND PATTERN FOR UNIVERSAL APPLICATION (0.05) 6X 5X 0.35 0.25 6 5 4 0.35 0.60 (0.08) 4X 0.10 .05 C C B A 0.40 0.30 BOTTOM VIEW NOTES: A. COMPLIES TO JEDEC MO-252 STANDARD B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994 D. LANDPATTERN RECOMMENDATION IS BASED ON FSC DESIGN. E. DRAWING FILENAME AND REVISION: MGF06AREV3 0.075X45° CHAMFER DETAIL A PIN 1 LEAD SCALE: 2X Figure 10. 6-Lead, MicroPak2, 1x1mm Body, .35mm Pitch Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Tape and Reel Specifications Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/packaging/MicroPAK2_6L_tr.pdf. Package Designator FHX © 1996 Fairchild Semiconductor Corporation NC7SZ00 • Rev. 1.0.4 Tape Section Cavity Number Cavity Status Cover Type Status Leader (Start End) 125 (Typical) Empty Sealed Carrier 5000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed www.fairchildsemi.com 9 NC7SZ00 — TinyLogic® UHS Two-Input NAND Gate © 1996 Fairchild Semiconductor Corporation NC7SZ00 • Rev. 1.0.4 www.fairchildsemi.com 10 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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