DATA SHEET
www.onsemi.com
TinyLogic UHS D-Type
Latch with 3-STATE Output
NC7SZ373
MARKING
DIAGRAMS
Description
Pin 1
The NC7SZ373 is a single positive edge−triggered D−type CMOS
Lach with 3−STATE output from onsemi’s Ultra High Speed Series of
TinyLogic in the space saving SC70 6−lead package. The device is
fabricated with advanced CMOS technology to achieve ultra high
speed with high output drive while maintaining low static power
dissipation over a very broad VCC operating range. The device is
specified to operate over the 1.65 V to 5.5 V VCC range. The inputs
and output are high impedance when VCC is 0 V. Inputs tolerate
voltages up to 5.5 V independent of VCC operating voltage. The latch
appears transparent to the data when Latch Enable (LE) is HIGH.
When LE is LOW, the data that meets the setup time is latched. The
output tolerates voltages above VCC in the 3−STATE condition.
6
SC−88
CASE 419B−02
Z73MG
G
1
D4, Z73
KK
XY
Z
M
G
= Specific Device Code
= 2−Digit Lot Run Traceability Code
= 2−Digit Date Code Format
= Assembly Plant Code
= Date Code*
= Pb−Free Package
(Note: Microdot may be in either location)
Features
•
•
•
•
•
•
•
•
•
•
D4KK
XYZ
SIP6 1.45x1.0
CASE 127EB
Space Saving SC−88 6−Lead Package
Ultra Small MicroPak™ Leadless Package
Ultra High Speed: tPD = 2.6 ns Typ into 50 pF at 5 V VCC
High Output Drive: ±24 mA at 3 V VCC
Broad VCC Operating Range: 1.65 V to 5.5 V
Matches the Performance of LCX when Operated at 3.3 V VCC
Power Down High Impedance Inputs / Output
Overvoltage Tolerant Inputs Facilitate 5 V to 3 V Translation
Patented Noise / EMI Reduction Circuitry Implemented
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
*Date Code orientation and/or position may
vary depending upon manufacturing location.
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 7 of this data sheet.
IEEC / IEC
OE
LE
D
Q
Figure 1. Logic Symbol
© Semiconductor Components Industries, LLC, 2004
March, 2022 − Rev. 3
1
Publication Order Number:
NC7SZ373/D
NC7SZ373
Connection Diagrams
LE
1
GND
2
LE
6
OE
5
VCC
LE 1
D
D
GND 2
Q
3
4
Q
5 VCC
D 3
Figure 2. SC−88 (Top View)
(Top View)
6 OE
4 Q
Figure 4. MicroPak (Top Through View)
AAA
Pin One
AAA = Product Code Top Mark − see ordering code
NOTE:
Orientation of Top Mark determines Pin One location.
Read the top product code mark left to right, Pin One
is the lower left pin (see diagram).
Figure 3. Pin 1 Orientation
PIN DESCRIPTIONS
Pin Name
D
FUNCTION TABLE
Description
Inputs
Output
Data Input
LE
D
OE
Q
CP
Latch Enable Input
H
L
L
L
OE
Output Enable Input
H
H
L
H
Latch Output
L
X
L
Qn−1
X
X
H
Z
Q
H = HIGH Logic Level
X = Immaterial
L = LOW Logic Level
Z = HIGH Impedance
Qn−1 = Previous state prior to HIGH−to−LOW transition of latch
enable
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2
NC7SZ373
ABSOLUTE MAXIMUM RATINGS
Symbol
Min
Max
Unit
VCC
Supply Voltage
−0.5
+6.5
V
VIN
DC Input Voltage
−0.5
+6.5
V
DC Output Voltage
−0.5
+6.5
V
VOUT
Parameter
IIK
DC Input Diode Current
VIN < 0 V
−
−50
mA
IOK
DC Output Diode Current
VOUT < 0 V
−
−50
mA
IOUT
DC Output Source / Sink Current
−
±50
mA
DC VCC / GND Current
−
±50
mA
−65
+150
°C
ICC / IGND
TSTG
Storage Temperature Range
TJ
Junction Temperature under Bias
−
150
°C
TL
Junction Lead Temperature (Soldering, 10 Seconds)
−
260
°C
PD
Power Dissipation in Still Air
SC−88
−
332
mW
MicroPak
−
812
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIN
VOUT
tr, tf
Min
Max
Unit
Supply Voltage Operating
Parameter
Conditions
1.65
5.5
V
Supply Voltage Data Retention
1.5
5.5
0
5.5
V
Active State
0
VCC
V
3−STATE
0
5.5
V
VCC = 1.8 V, 2.5 V ±0.2 V
0
20
ns/V
VCC = 3.3 V ±0.3 V
0
10
VCC = 5.5 V ±0.5 V
0
5
−40
+85
°C
SC−88
−
377
°C/W
MicroPak
−
154
Input Voltage
Output Voltage
Input Rise and Fall Time
TA
Operating Temperature
qJA
Thermal Resistance
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
1. Unused inputs must be held HIGH or LOW. They may not float.
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3
NC7SZ373
DC ELECTICAL CHARACTERISTICS
TA = +25°C
Symbol
VIH
VIL
VOH
VOL
Parameter
VCC (V)
Conditions
TA = −40 to +85°C
Min
Typ
Max
Min
Max
Unit
V
HIGH Level Control
Input Voltage
1.65 to 1.95
0.65 VCC
−
−
0.65 VCC
−
2.3 to 5.5
0.7 VCC
−
−
0.7 VCC
−
LOW Level Control
Input Voltage
1.65 to 1.95
−
−
0.35 VCC
−
0.35 VCC
2.3 to 5.5
−
−
0.3 VCC
−
0.3 VCC
HIGH Level Control
Output Voltage
1.65
1.55
1.65
−
1.55
−
1.7
1.8
−
1.7
−
2.3
2.2
2.3
−
2.2
−
3.0
2.9
3.0
−
2.9
−
4.5
4.4
4.5
−
4.4
−
LOW Level Control
Output Voltage
1.8
VIN = VIH
or VIL
IOH = −100 mA
1.65
IOH = −4 mA
1.24
1.52
−
1.29
−
2.3
IOH = −8 mA
1.9
2.15
−
1.9
−
3.0
IOH = −16 mA
2.4
2.8
−
2.4
−
3.0
IOH = −24 mA
2.3
2.68
−
2.3
−
4.5
IOH = −32 mA
3.8
4.2
−
3.8
−
IOL = 100 mA
−
0.0
0.08
−
0.0
−
0.0
0.1
−
0.1
2.3
−
0.0
0.1
−
0.1
3.0
−
0.0
0.1
−
0.1
4.5
−
0.0
0.1
−
0.1
1.65
1.8
VIN = VIH
or VIL
1.65
IOL = 4 mA
−
0.08
0.24
−
0.24
2.3
IOL = 8 mA
−
0.10
0.3
−
0.3
3.0
IOL = 16 mA
−
0.15
0.4
−
0.4
3.0
IOL = 24 mA
−
0.22
0.55
−
0.55
IOL = 32 mA
4.5
V
V
V
−
0.22
0.55
−
0.55
IIN
Input Leakage
Current
1.65 to 5.5
0 ≤ VIN ≤ 5.5 V
−
−
±0.1
−
±1.0
mA
IOZ
3−STATE Output
Leakage
1.65 to 5.5
VIN = VIL or VIH
0 ≤ VOUT ≤ 5.5 V
−
−
±0.5
−
±5.0
mA
IOFF
Power Off Leakage
Current
VIN or VOUT = 5.5 V
−
−
1.0
−
10
mA
ICC
Quiescent Supply
Current
VIN = 5.5 V, GND
−
−
1.0
−
10
mA
0.0
1.65 to 5.5
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4
NC7SZ373
AC ELECTRICAL CHARACTERISTICS
TA = +25°C
Symbol
tPLH
tPHL
Parameter
Propagation Delay
D to Q
Conditions
Min
Typ
Max
Min
Max
Unit
1.65
CL = 15 pF, RD = 1 MW,
S1 = Open
(Figures 5, 7)
−
9.0
15.0
−
16.0
ns
−
6.1
10.0
−
10.5
2.5 ±0.2
−
3.6
6.5
−
6.8
3.3 ±0.3
−
2.7
4.6
−
5.0
5.0 ±0.5
−
2.0
3.4
−
3.7
CL = 50 pF, RD = 500 W
S1 = Open
(Figures 5, 7)
−
3.3
5.5
−
6.2
−
2.6
4.3
−
4.8
CL = 15 pF, RD = 1 MW,
S1 = Open
(Figures 5, 7)
−
9.0
1.45
−
15.0
−
6.0
9.6
−
10.0
2.5 ±0.2
−
3.5
6.1
−
6.6
3.3 ±0.3
−
2.6
4.4
−
4.8
5.0 ±0.5
−
2.0
3.2
−
3.5
CL = 50 pF, RD = 500 W,
S1 = Open
(Figures 5, 8)
−
3.3
5.3
−
6.2
−
2.6
4.2
−
4.6
CL = 50 pF, VI = 2 x VCC,
RU, RD = 500 W,
S1 = GND for tPZH
S1 = VI for tPZL
(Figures 5, 8)
−
9.0
13.5
−
14.6
−
6.0
9.0
−
9.5
−
3.7
6.0
−
6.6
3.3 ±0.3
−
2.8
5.0
−
5.3
5.0 ±0.5
−
2.2
3.7
−
3.9
−
7.7
12.0
−
13.0
−
5.1
8.0
−
8.5
1.8
3.3 ±0.3
5.0 ±0.5
tPLH
tPHL
Propagation Delay
LE to Q
1.65
1.8
3.3 ±0.3
5.0 ±0.5
tPZL
tPZH
Output Enable Time
1.65
1.8
2.5 ±0.2
tPLZ
tPHZ
Output Disable Time
1.65
1.8
2.5 ±0.2
tS
Setup Time, D to LE
CL = 50 pF, VI = 2 x VCC,
RU, RD = 500 W,
S1 = GND for tPHZ
S1 = VI for tPLZ
(Figures 5, 8)
−
3.5
6.0
−
6.3
3.3 ±0.3
−
2.8
4.5
−
4.7
5.0 ±0.5
−
2.3
3.7
−
3.9
−
−
−
2.0
−
−
−
−
1.5
−
−
−
1.5
−
−
−
−
1.5
−
−
−
−
1.5
−
−
−
−
1.5
−
−
−
−
3.0
−
−
−
−
3.0
−
−
−
−
3.0
−
2.5 ±0.2
3.3 ±0.3
CL = 50 pF, RD = 500 W,
S1 = Open
(Figures 5, 9)
5.0 ±0.5
tH
Hold Time, D to LE
2.5 ±0.2
3.3 ±0.3
CL = 50 pF, RD = 500 W,
S1 = Open
(Figures 5, 9)
5.0 ±0.5
tW
Pulse Width, LE
TA = −40 to +85°C
VCC (V)
2.5 ±0.2
3.3 ±0.3
CL = 50 pF, RD = 500 W,
S1 = Open
(Figures 5, 9)
5.0 ±0.5
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5
ns
ns
ns
ns
ns
ns
NC7SZ373
CAPACITANCE (TA = +25°C, f = 1 MHz)
Symbol
CIN
Parameter
Condition
Typ
Max
Units
Input Capacitance
VCC = Open, VIN = 0 V or VCC
3
−
pF
COUT
Output Capacitance
VCC = 3.3 V, VIN = 0 V or VCC
4
−
pF
CPD
Power Dissipation Capacitance
(Note 2)
VCC = 3.3 V
VCC = 5.0 V
14
17
−
−
pF
2. CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (ICCD) at
no output loading and operating at 50% duty cycle. (See Figure 6)
CPD is related to ICCD dynamic operating current by the expression: ICCD = (CPD) (VCC) (fIN) + (ICCstatic).
AC Loading and Waveforms
VCC
VCC
OE
D
LE
A
VIN
OPEN
GND
Q
OE
LE Input
RU
OUTPUT
CL
RD
D Input
CL includes load and stray capacitance
Input PRR = 1.0 MHz, tW = 500 ns.
Q Output
D Input = AC Waveform; tr = tf = 1.8 ns;
D Input PRR = 10 MHz; Duty Cycle = 50%.
Figure 5. AC Test Circuit
Figure 6. ICCD Test Circuit
Figure 7. AC Waveforms
Figure 8. AC Waveforms
Figure 9. AC Waveforms
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6
NC7SZ373
ORDERING INFORMATION
Top Mark
Packages
Shipping†
NC7SZ373P6X
Z73
6−Lead SC70, EIAJ SC88, 1.25 mm Wide
3000 / Tape & Reel
NC7SZ373P6X−L22347
Z73
6−Lead SC70, EIAJ SC88, 1.25 mm Wide
3000 / Tape & Reel
NC7SZ373L6X
D4
6−Lead MicroPak, 1.00 mm Wide
5000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MicroPak is trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
www.onsemi.com
7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SIP6 1.45X1.0
CASE 127EB
ISSUE O
DOCUMENT NUMBER:
DESCRIPTION:
98AON13590G
SIP6 1.45X1.0
DATE 31 AUG 2016
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC−88 (SC−70 6 Lead), 1.25x2
CASE 419AD
ISSUE A
DATE 07 JUL 2010
1
D
e
e
E1 E
SYMBOL
MIN
A
0.80
MAX
1.10
A1
0.00
0.10
A2
0.80
1.00
b
0.15
0.30
0.18
c
0.10
D
1.80
2.00
2.20
E
1.80
2.10
2.40
E1
1.15
1.25
1.35
0.65 BSC
e
L
0.26
L1
0.36
0.46
0.42 REF
0.15 BSC
L2
TOP VIEW
NOM
θ
0º
8º
θ1
4º
10º
q1
A2 A
q
b
q1
L
L1
A1
SIDE VIEW
c
L2
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-203.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34266E
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
SC−88 (SC−70 6 LEAD), 1.25X2
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
1
SCALE 2:1
DATE 11 DEC 2012
2X
aaa H D
D
H
A
D
6
5
GAGE
PLANE
4
1
2
L
L2
E1
E
DETAIL A
3
aaa C
2X
bbb H D
2X 3 TIPS
e
B
6X
b
ddd
TOP VIEW
C A-B D
M
A2
DETAIL A
A
6X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.
4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY AND DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.
7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OF THE FOOT.
ccc C
A1
SIDE VIEW
C
SEATING
PLANE
END VIEW
c
RECOMMENDED
SOLDERING FOOTPRINT*
6X
DIM
A
A1
A2
b
C
D
E
E1
e
L
L2
aaa
bbb
ccc
ddd
MILLIMETERS
MIN
NOM MAX
−−−
−−−
1.10
0.00
−−−
0.10
0.70
0.90
1.00
0.15
0.20
0.25
0.08
0.15
0.22
1.80
2.00
2.20
2.00
2.10
2.20
1.15
1.25
1.35
0.65 BSC
0.26
0.36
0.46
0.15 BSC
0.15
0.30
0.10
0.10
GENERIC
MARKING DIAGRAM*
6
XXXMG
G
6X
0.30
INCHES
NOM MAX
−−− 0.043
−−− 0.004
0.035 0.039
0.008 0.010
0.006 0.009
0.078 0.086
0.082 0.086
0.049 0.053
0.026 BSC
0.010 0.014 0.018
0.006 BSC
0.006
0.012
0.004
0.004
MIN
−−−
0.000
0.027
0.006
0.003
0.070
0.078
0.045
0.66
1
2.50
0.65
PITCH
XXX = Specific Device Code
M
= Date Code*
G
= Pb−Free Package
(Note: Microdot may be in either location)
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
*Date Code orientation and/or position may
vary depending upon manufacturing location.
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42985B
SC−88/SC70−6/SOT−363
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
DATE 11 DEC 2012
STYLE 1:
PIN 1. EMITTER 2
2. BASE 2
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
6. COLLECTOR 2
STYLE 2:
CANCELLED
STYLE 3:
CANCELLED
STYLE 4:
PIN 1. CATHODE
2. CATHODE
3. COLLECTOR
4. EMITTER
5. BASE
6. ANODE
STYLE 5:
PIN 1. ANODE
2. ANODE
3. COLLECTOR
4. EMITTER
5. BASE
6. CATHODE
STYLE 6:
PIN 1. ANODE 2
2. N/C
3. CATHODE 1
4. ANODE 1
5. N/C
6. CATHODE 2
STYLE 7:
PIN 1. SOURCE 2
2. DRAIN 2
3. GATE 1
4. SOURCE 1
5. DRAIN 1
6. GATE 2
STYLE 8:
CANCELLED
STYLE 9:
PIN 1. EMITTER 2
2. EMITTER 1
3. COLLECTOR 1
4. BASE 1
5. BASE 2
6. COLLECTOR 2
STYLE 10:
PIN 1. SOURCE 2
2. SOURCE 1
3. GATE 1
4. DRAIN 1
5. DRAIN 2
6. GATE 2
STYLE 11:
PIN 1. CATHODE 2
2. CATHODE 2
3. ANODE 1
4. CATHODE 1
5. CATHODE 1
6. ANODE 2
STYLE 12:
PIN 1. ANODE 2
2. ANODE 2
3. CATHODE 1
4. ANODE 1
5. ANODE 1
6. CATHODE 2
STYLE 13:
PIN 1. ANODE
2. N/C
3. COLLECTOR
4. EMITTER
5. BASE
6. CATHODE
STYLE 14:
PIN 1. VREF
2. GND
3. GND
4. IOUT
5. VEN
6. VCC
STYLE 15:
PIN 1. ANODE 1
2. ANODE 2
3. ANODE 3
4. CATHODE 3
5. CATHODE 2
6. CATHODE 1
STYLE 16:
PIN 1. BASE 1
2. EMITTER 2
3. COLLECTOR 2
4. BASE 2
5. EMITTER 1
6. COLLECTOR 1
STYLE 17:
PIN 1. BASE 1
2. EMITTER 1
3. COLLECTOR 2
4. BASE 2
5. EMITTER 2
6. COLLECTOR 1
STYLE 18:
PIN 1. VIN1
2. VCC
3. VOUT2
4. VIN2
5. GND
6. VOUT1
STYLE 19:
PIN 1. I OUT
2. GND
3. GND
4. V CC
5. V EN
6. V REF
STYLE 20:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. EMITTER
5. COLLECTOR
6. COLLECTOR
STYLE 21:
PIN 1. ANODE 1
2. N/C
3. ANODE 2
4. CATHODE 2
5. N/C
6. CATHODE 1
STYLE 22:
PIN 1. D1 (i)
2. GND
3. D2 (i)
4. D2 (c)
5. VBUS
6. D1 (c)
STYLE 23:
PIN 1. Vn
2. CH1
3. Vp
4. N/C
5. CH2
6. N/C
STYLE 24:
PIN 1. CATHODE
2. ANODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
STYLE 25:
PIN 1. BASE 1
2. CATHODE
3. COLLECTOR 2
4. BASE 2
5. EMITTER
6. COLLECTOR 1
STYLE 26:
PIN 1. SOURCE 1
2. GATE 1
3. DRAIN 2
4. SOURCE 2
5. GATE 2
6. DRAIN 1
STYLE 27:
PIN 1. BASE 2
2. BASE 1
3. COLLECTOR 1
4. EMITTER 1
5. EMITTER 2
6. COLLECTOR 2
STYLE 28:
PIN 1. DRAIN
2. DRAIN
3. GATE
4. SOURCE
5. DRAIN
6. DRAIN
STYLE 29:
PIN 1. ANODE
2. ANODE
3. COLLECTOR
4. EMITTER
5. BASE/ANODE
6. CATHODE
STYLE 30:
PIN 1. SOURCE 1
2. DRAIN 2
3. DRAIN 2
4. SOURCE 2
5. GATE 1
6. DRAIN 1
Note: Please refer to datasheet for
style callout. If style type is not called
out in the datasheet refer to the device
datasheet pinout or pin assignment.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42985B
SC−88/SC70−6/SOT−363
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
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