DATA SHEET
www.onsemi.com
TinyLogic UHS Universal
Configurable Two-Input
Logic Gates
MARKING
DIAGRAMS
NC7SZ57, NC7SZ58
Pin 1
UDFN6
1.0X1.0, 0.35P
CASE 517DP
Description
The NC7SZ57 and NC7SZ58 are universal configurable two−input
logic gates. Each device is capable of being configured for 1 of 5
unique two−input logic functions. Any possible two−input
combinatorial logic function can be implemented, as shown in the
Function Selection Table. Device functionality is selected by how the
device is wired at the board level. Figures 4 through 13 illustrate how
to connect the NC7SZ57 and NC7SZ58, respectively, for the desired
logic function. All inputs have been implemented with hysteresis.
The device is fabricated with advanced CMOS technology to
achieve ultra high speed with high output drive while maintaining low
static power dissipation over a broad VCC operating range. The device
is specified to operate over the 1.65 V to 5.5 V VCC operating range.
The input and output are high impedance when VCC is 0 V. Inputs
tolerate voltages up to 5.5 V independent of VCC operating range.
Features
•
•
•
•
•
•
•
•
•
Ultra High−Speed
Capable of Implementing any Two−Input Logic Functions
Typical Usage Replaces Two (2) TinyLogic Gate Devices
Reduces Part Counts in Inventory
Broad VCC Operating Range: 1.65 V to 5.5 V
Power Down High Impednce Input / Output
Over−Voltage Tolerant Inputs Facilitate 5 V to 3 V Translation
Proprietary Noise / EMI Reduction Circuitry Implemented
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
© Semiconductor Components Industries, LLC, 2000
June, 2022 − Rev. 5
XXKK
XYZ
SIP6 1.45x1.0
CASE 127EB
1
XXKK
XYZ
Pin 1
6
SC−88
DF SUFFIX
CASE 419B−02
XXXMG
G
1
1
XX, XXX
KK
XY
Z
M
G
= Specific Device Code
= 2−Digit Lot Run Traceability Code
= 2−Digit Date Code Format
= Assembly Plant Code
= Date Code*
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may
vary depending upon manufacturing location.
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 9 of this data sheet.
Publication Order Number:
NC7SZ58/D
NC7SZ57, NC7SZ58
Pin Configurations
I1
1
6
I2
GND
2
5
VCC
I0
3
4
Y
I1 1
GND 2
5 VCC
I0 3
Figure 1. SC70 (Top View)
(Top View)
6 I2
4 Y
Figure 3. MicroPakt (Top Through View)
AAA
Pin One
NOTES:
1. AAA represents product code top mark (see Ordering Information).
2. Orientation of top mark determines pin one location.
3. Reading the top mark left to right, pin one is the lower left pin.
Figure 2. Pin 1 Orientation
PIN DEFINITIONS
FUNCTION TABLE
Pin # SC70 Pin # MicroPak Name
1
1
I1
2
2
GND
3
3
I0
4
4
Y
5
5
VCC
6
6
I2
Description
Inputs
NC7SZ57
NC7SZ58
Data Input
I2
I1
Ground
L
L
L
H
L
Data Input
L
L
H
L
H
Output
L
H
L
H
L
Supply Voltage
L
H
H
L
H
Data Input
H
L
L
L
H
H
L
H
L
H
H
H
L
H
L
H
H
H
H
L
I0
Y = (I0) · (I2) + (I1) · (I2) Y = (I0) · (I2) + (I1) · (I2)
H = HIGH Logic Level
L = LOW Logic Level
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2
NC7SZ57, NC7SZ58
FUNCTION SELECTION TABLE
2−Input Logic Function
Device Selection
Connection Configuration
2−Input AND
NC7SZ57
Figure 4
2−Input AND with Inverted Input
NC7SZ58
Figure 10, Figure 11
2−Input AND with Both Inputs Inverted
NC7SZ57
Figure 7
2−Input NAND
NC7SZ58
Figure 9
2−Input NAND with Inverted Input
NC7SZ57
Figure 5, Figure 6
2−Input NAND with Both Inputs Inverted
NC7SZ58
Figure 12
2−Input OR
NC7SZ58
Figure 12
2−Input OR with Inverted Input
NC7SZ57
Figure 5, Figure 6
2−Input OR with Both Inputs Inverted
NC7SZ58
Figure 9
2−Input NOR
NC7SZ57
Figure 7
2−Input NOR with Inverted Input
NC7SZ58
Figure 9, Figure 10
2−Input NOR with Both Inputs Inverted
NC7SZ57
Figure 4
2−Input XOR
NC7SZ58
Figure 13
2−Input XNOR
NC7SZ57
Figure 8
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3
NC7SZ57, NC7SZ58
NC7SZ57 Logic Configurations
Figure 4 through Figure 8 show the logical functions that
can be implemented using the NC7SZ57. The diagrams
show the DeMorgan’s equivalent logic duals for a given
two−input function. The logical implementation is next to
the board−level physical implementation of how the pins of
the function should be connected.
Figure 4. 2−Input AND Gate
Figure 5. 2−Input NAND with Inverted A Input
Figure 6. 2−Input NAND with Inverted B Input
Figure 7. 2−Input NOR Gate
Figure 8. 2−Input XNOR Gate
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4
NC7SZ57, NC7SZ58
NC7SZ58 Logic Configurations
Figure 9 through Figure 13 show the logical functions that
can be implemented using the NC7SZ58. The diagrams
show the DeMorgan’s equivalent logic duals for a given
two−input function. The logical implementation is next to
the board−level physical implementation of how the pins of
the function should be connected.
Figure 9. 2−Input NAND Gate
Figure 10. 2−Input AND with Inverted A Input
Figure 11. 2−Input AND with Inverted B Input
Figure 12. 2−Input OR Gate
Figure 13. 2−Input XOR Gate
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5
NC7SZ57, NC7SZ58
ABSOLUTE MAXIMUM RATINGS
Symbol
Min
Max
Unit
VCC
Supply Voltage
−0.5
6.5
V
VIN
DC Input Voltage
−0.5
6.5
V
DC Output Voltage
−0.5
6.5
V
VOUT
Parameter
IIK
DC Input Diode Current
VIN < 0 V
−
−50
mA
IOK
DC Output Diode Current
VOUT < 0 V
−
−50
mA
IOUT
DC Output Source / Sink Current
−
±50
mA
DC VCC or Ground Current
−
±50
mA
−65
+150
°C
ICC or IGND
TSTG
Storage Temperature Range
TJ
Maximum Junction Temperature under Bias
−
+150
°C
TL
Lead Temperature, Soldering, 10 Seconds
−
+260
°C
PD
Power Dissipation in Still Air
SC70−6
−
332
mW
MicroPak−6
−
812
MicroPak2t−6
−
812
Human Body Model, JEDEC: JESD22−A114
−
4000
Charge Device Model, JEDEC: JESD22−C101
−
2000
ESD
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIN
VOUT
Parameter
Conditions
Min
Max
Unit
Supply Voltage Operating
1.65
5.5
V
Supply Voltage Data Retention
1.5
5.5
0
5.5
Input Voltage
Output Voltage
TA
Operating Temperature
qJA
Thermal Resistance
V
0
VCC
V
−40
+85
°C
SC70−6
−
377
°C/W
MicroPak−6
−
154
MicroPak2−6
−
154
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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6
NC7SZ57, NC7SZ58
DC ELECTICAL CHARACTERISTICS
TA = +25°C
Symbol
VP
VN
VH
VOH
Parameter
Positive Threshold
Voltage
Negative Threshold
Voltage
Hysteresis Voltage
HIGH Level Output
Voltage
Typ
Max
Min
Max
Unit
1.65
−
0.99
1.40
−
1.40
V
2.30
−
1.39
1.80
−
1.80
3.00
−
1.77
2.20
−
2.20
4.50
−
2.49
3.10
−
3.10
5.50
−
2.95
3.60
−
3.60
1.65
0.20
0.50
−
0.20
−
2.30
0.40
0.75
−
0.40
−
3.00
0.60
0.99
−
0.60
−
4.50
1.00
1.43
−
1.00
−
5.50
1.20
1.70
−
1.20
−
1.65
0.15
0.48
0.90
0.15
0.90
2.30
0.25
0.64
1.10
0.25
1.10
3.00
0.40
0.78
1.20
0.40
1.20
4.50
0.60
1.06
1.50
0.60
1.50
5.50
0.70
1.25
1.70
0.70
1.70
1.55
1.65
−
1.55
−
VCC (V)
1.65
2.30
Conditions
VIN = VIH or VIL
IOH = −100 mA
2.20
2.30
−
2.20
−
3.00
2.90
3.00
−
2.90
−
4.50
4.40
4.50
−
4.40
−
IOH = −4 mA
1.29
1.52
−
1.29
−
IOH = −8 mA
1.90
2.15
−
1.90
−
3.00
IOH = −16 mA
2.40
2.80
−
2.40
−
3.00
IOH = −24 mA
2.30
2.68
−
2.30
−
IOH = −32 mA
3.80
4.20
−
3.80
−
−
−
0.10
−
0.10
−
−
0.10
−
0.10
3.00
−
−
0.10
−
0.10
4.50
−
−
0.10
−
0.10
IOL = 4 mA
−
0.08
0.24
−
0.24
1.65
2.30
VIN = VIH
or VIL
4.50
VOL
LOW Level Output
Voltage
1.65
2.30
1.65
2.30
IIN
Input Leakage Current
IOFF
Power Off Leakage
Current
ICC
Quiescent Supply
Current
TA = −40 to +85°C
Min
VIN = VIH or VIL
IOL = 100 mA
VIN = VIH
or VIL
V
V
V
V
IOL = 8 mA
−
0.10
0.30
−
0.30
3.00
IOL = 16 mA
−
0.15
0.40
−
0.40
3.00
IOL = 24 mA
−
0.22
0.55
−
0.55
4.50
IOL = 32 mA
−
0.22
0.55
−
0.55
VIN = 5.5 V, GND
−
−
±0.1
−
±1.0
mA
VIN or VOUT = 5.5 V
−
−
1
−
10
mA
VIN = 5.5 V, GND
−
−
1
−
10
mA
1.65 to 5.50
0
1.65 to 5.5
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7
NC7SZ57, NC7SZ58
AC ELECTRICAL CHARACTERISTICS
TA = +25°C
Symbol
tPLH, tPHL
Parameter
Propagation Delay In to Y
(Figure 14, 16)
Typ
Max
Min
Max
Unit
−
8.0
14.0
−
14.5
ns
−
4.9
8.0
−
8.5
3.3 ±0.3
−
3.7
5.3
−
5.7
5.0 ±0.5
−
2.8
4.3
−
4.6
−
4.2
6.0
−
6.5
−
3.4
4.9
−
5.3
−
2
−
−
−
pF
−
14
−
−
−
pF
−
17
−
−
−
Conditions
CL = 15 pF,
RL = 1 MW
1.8 ±0.15
2.5 ±0.2
CL = 50 pF,
RL = 500 W
3.3 ±0.3
5.0 ±0.5
CIN
Input Capacitance
CPD
Power Dissipation Capacitance
(Figure 15)
TA = −40 to +85°C
Min
VCC (V)
0
(Note 4)
3.3
5.0
ns
4. CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (ICCD) at
no output loading and operating at 50% duty cycle. (See Figure 12) CPD is related to ICCD dynamic operating current by the expression:
ICCD = (CPD) (VCC) (fIN) + (ICCstatic).
AC Loading and Waveforms
VCC
VCC
A
INPUT
DUT
OUTPUT
CL
INPUT
RL
NOTE:
5. CL includes load and stray capacitance.
6. Input PRR = 1.0 MHz, tW = 500 ns.
DUT
NOTE:
7. Input = AC Waveforms.
8. PRR = Variable; Duty Cycle = 50%.
Figure 14. AC Test Circuit
Figure 15. ICCD Test Circuit
tr = 3 ns
tf = 3 ns
90%
90%
50%
INPUT
10%
10%
tW
GND
tPLH
VOH
50%
50%
Out of Phase
OUTPUT
VCC
50%
tPHL
VOL
tPLH
In Phase
OUTPUT
INPUT
tPHL
VOH
50%
50%
VOL
Figure 16. AC Waveforms
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8
NC7SZ57, NC7SZ58
ORDERING INFORMATION
Top Mark
Package
Shipping†
NC7SZ57P6X
Z57
6−Lead SC70, EIAJ SC−88, 1.25 mm Wide
3000 / Tape & Reel
NC7SZ57P6X−L22347
Z57
6−Lead SC70, EIAJ SC−88, 1.25 mm Wide
3000 / Tape & Reel
NC7SZ57L6X
KK
6−Lead Micropak, 1.0 mm Wide
5000 / Tape & Reel
NC7SZ57L6X−L22175
KK
6−Lead Micropak, 1.0 mm Wide
5000 / Tape & Reel
NC7SZ57FHX
KK
6−Lead, MicroPak2, 1x1 mm Body, .35 mm Pitch
5000 / Tape & Reel
NC7SZ57FHX−L22175
KK
6−Lead, MicroPak2, 1x1 mm Body, .35 mm Pitch
5000 / Tape & Reel
NC7SZ58P6X
Z58
6−Lead SC70, EIAJ SC−88, 1.25 mm Wide
3000 / Tape & Reel
NC7SZ58P6X−L22347
Z58
6−Lead SC70, EIAJ SC−88, 1.25 mm Wide
3000 / Tape & Reel
NC7SZ58L6X
LL
6−Lead Micropak, 1.0 mm Wide
5000 / Tape & Reel
NC7SZ58L6X−L22175
LL
6−Lead Micropak, 1.0 mm Wide
5000 / Tape & Reel
NC7SZ58FHX
LL
6−Lead, MicroPak2 , 1x1 mm Body, .35 mm Pitch
5000 / Tape & Reel
NC7SZ58FHX−L22175
LL
6−Lead, MicroPak2 , 1x1 mm Body, .35 mm Pitch
5000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MicroPak and MicroPak2 are trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other
countries.
www.onsemi.com
9
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SIP6 1.45X1.0
CASE 127EB
ISSUE O
DOCUMENT NUMBER:
DESCRIPTION:
98AON13590G
SIP6 1.45X1.0
DATE 31 AUG 2016
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC−88 (SC−70 6 Lead), 1.25x2
CASE 419AD
ISSUE A
DATE 07 JUL 2010
1
D
e
e
E1 E
SYMBOL
MIN
A
0.80
MAX
1.10
A1
0.00
0.10
A2
0.80
1.00
b
0.15
0.30
0.18
c
0.10
D
1.80
2.00
2.20
E
1.80
2.10
2.40
E1
1.15
1.25
1.35
0.65 BSC
e
L
0.26
L1
0.36
0.46
0.42 REF
0.15 BSC
L2
TOP VIEW
NOM
θ
0º
8º
θ1
4º
10º
q1
A2 A
q
b
q1
L
L1
A1
SIDE VIEW
c
L2
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-203.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34266E
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
SC−88 (SC−70 6 LEAD), 1.25X2
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
1
SCALE 2:1
DATE 11 DEC 2012
2X
aaa H D
D
H
A
D
6
5
GAGE
PLANE
4
1
2
L
L2
E1
E
DETAIL A
3
aaa C
2X
bbb H D
2X 3 TIPS
e
B
6X
b
ddd
TOP VIEW
C A-B D
M
A2
DETAIL A
A
6X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.
4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY AND DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.
7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OF THE FOOT.
ccc C
A1
SIDE VIEW
C
SEATING
PLANE
END VIEW
c
RECOMMENDED
SOLDERING FOOTPRINT*
6X
DIM
A
A1
A2
b
C
D
E
E1
e
L
L2
aaa
bbb
ccc
ddd
MILLIMETERS
MIN
NOM MAX
−−−
−−−
1.10
0.00
−−−
0.10
0.70
0.90
1.00
0.15
0.20
0.25
0.08
0.15
0.22
1.80
2.00
2.20
2.00
2.10
2.20
1.15
1.25
1.35
0.65 BSC
0.26
0.36
0.46
0.15 BSC
0.15
0.30
0.10
0.10
GENERIC
MARKING DIAGRAM*
6
XXXMG
G
6X
0.30
INCHES
NOM MAX
−−− 0.043
−−− 0.004
0.035 0.039
0.008 0.010
0.006 0.009
0.078 0.086
0.082 0.086
0.049 0.053
0.026 BSC
0.010 0.014 0.018
0.006 BSC
0.006
0.012
0.004
0.004
MIN
−−−
0.000
0.027
0.006
0.003
0.070
0.078
0.045
0.66
1
2.50
0.65
PITCH
XXX = Specific Device Code
M
= Date Code*
G
= Pb−Free Package
(Note: Microdot may be in either location)
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
*Date Code orientation and/or position may
vary depending upon manufacturing location.
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42985B
SC−88/SC70−6/SOT−363
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
DATE 11 DEC 2012
STYLE 1:
PIN 1. EMITTER 2
2. BASE 2
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
6. COLLECTOR 2
STYLE 2:
CANCELLED
STYLE 3:
CANCELLED
STYLE 4:
PIN 1. CATHODE
2. CATHODE
3. COLLECTOR
4. EMITTER
5. BASE
6. ANODE
STYLE 5:
PIN 1. ANODE
2. ANODE
3. COLLECTOR
4. EMITTER
5. BASE
6. CATHODE
STYLE 6:
PIN 1. ANODE 2
2. N/C
3. CATHODE 1
4. ANODE 1
5. N/C
6. CATHODE 2
STYLE 7:
PIN 1. SOURCE 2
2. DRAIN 2
3. GATE 1
4. SOURCE 1
5. DRAIN 1
6. GATE 2
STYLE 8:
CANCELLED
STYLE 9:
PIN 1. EMITTER 2
2. EMITTER 1
3. COLLECTOR 1
4. BASE 1
5. BASE 2
6. COLLECTOR 2
STYLE 10:
PIN 1. SOURCE 2
2. SOURCE 1
3. GATE 1
4. DRAIN 1
5. DRAIN 2
6. GATE 2
STYLE 11:
PIN 1. CATHODE 2
2. CATHODE 2
3. ANODE 1
4. CATHODE 1
5. CATHODE 1
6. ANODE 2
STYLE 12:
PIN 1. ANODE 2
2. ANODE 2
3. CATHODE 1
4. ANODE 1
5. ANODE 1
6. CATHODE 2
STYLE 13:
PIN 1. ANODE
2. N/C
3. COLLECTOR
4. EMITTER
5. BASE
6. CATHODE
STYLE 14:
PIN 1. VREF
2. GND
3. GND
4. IOUT
5. VEN
6. VCC
STYLE 15:
PIN 1. ANODE 1
2. ANODE 2
3. ANODE 3
4. CATHODE 3
5. CATHODE 2
6. CATHODE 1
STYLE 16:
PIN 1. BASE 1
2. EMITTER 2
3. COLLECTOR 2
4. BASE 2
5. EMITTER 1
6. COLLECTOR 1
STYLE 17:
PIN 1. BASE 1
2. EMITTER 1
3. COLLECTOR 2
4. BASE 2
5. EMITTER 2
6. COLLECTOR 1
STYLE 18:
PIN 1. VIN1
2. VCC
3. VOUT2
4. VIN2
5. GND
6. VOUT1
STYLE 19:
PIN 1. I OUT
2. GND
3. GND
4. V CC
5. V EN
6. V REF
STYLE 20:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. EMITTER
5. COLLECTOR
6. COLLECTOR
STYLE 21:
PIN 1. ANODE 1
2. N/C
3. ANODE 2
4. CATHODE 2
5. N/C
6. CATHODE 1
STYLE 22:
PIN 1. D1 (i)
2. GND
3. D2 (i)
4. D2 (c)
5. VBUS
6. D1 (c)
STYLE 23:
PIN 1. Vn
2. CH1
3. Vp
4. N/C
5. CH2
6. N/C
STYLE 24:
PIN 1. CATHODE
2. ANODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
STYLE 25:
PIN 1. BASE 1
2. CATHODE
3. COLLECTOR 2
4. BASE 2
5. EMITTER
6. COLLECTOR 1
STYLE 26:
PIN 1. SOURCE 1
2. GATE 1
3. DRAIN 2
4. SOURCE 2
5. GATE 2
6. DRAIN 1
STYLE 27:
PIN 1. BASE 2
2. BASE 1
3. COLLECTOR 1
4. EMITTER 1
5. EMITTER 2
6. COLLECTOR 2
STYLE 28:
PIN 1. DRAIN
2. DRAIN
3. GATE
4. SOURCE
5. DRAIN
6. DRAIN
STYLE 29:
PIN 1. ANODE
2. ANODE
3. COLLECTOR
4. EMITTER
5. BASE/ANODE
6. CATHODE
STYLE 30:
PIN 1. SOURCE 1
2. DRAIN 2
3. DRAIN 2
4. SOURCE 2
5. GATE 1
6. DRAIN 1
Note: Please refer to datasheet for
style callout. If style type is not called
out in the datasheet refer to the device
datasheet pinout or pin assignment.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42985B
SC−88/SC70−6/SOT−363
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
UDFN6 1.0X1.0, 0.35P
CASE 517DP
ISSUE O
DOCUMENT NUMBER:
DESCRIPTION:
98AON13593G
UDFN6 1.0X1.0, 0.35P
DATE 31 AUG 2016
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
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