NC7SZ74K8X

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This literature is subject to all applicable copyright laws and is not for resale in any manner. NC7SZ74 TinyLogic® UHS D-Type, Flip-Flop with Preset and Clear Features Description  Ultra-High Speed: tPD 2.6ns (Typical) into 50pF at 5V VCC     High Output Drive: ±24mA at 3V VCC The NC7SZ74 is a single, D-type, CMOS flip-flop with preset and clear from Fairchild’s ultra high-speed series ® of TinyLogic . The device is fabricated with advanced CMOS technology to achieve ultra high speed with high output drive, while maintaining low static power dissipation over a very broad VCC operating range of 1.65V to 5.5V VCC. The inputs and outputs are high impedance when VCC is 0V. Inputs tolerate voltages up to 7V, independent of VCC operating voltage.    Proprietary Noise/EMI Reduction Circuitry Broad VCC Operating Range: 1.65V to 5.5V Power Down High-Impedance Inputs/Outputs Over-Voltage Tolerance Inputs Facilitate 5V to 3V Translation Ultra-Small MicroPak™ Package The signal level applied to the D input is transferred to the Q output during the positive-going transition of the CLK pulse. Space-Saving US8 Surface Mount Package Ordering Information Part Number Top Mark NC7SZ74K8X SZ74 NC7SZ74L8X N9 © 2001 Fairchild Semiconductor Corporation NC7SZ74 • Rev. 1.0.2 Package Packing Method 8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide- 3000 Units on Tape & Reel 8-Lead MicroPak, 1.6 mm Wide 5000 Units on Tape & Reel www.fairchildsemi.com NC7SZ74 — TinyLogic® UHS D-Type Flip-Flow with Preset and Clear August 2011 IEEE/IEC Figure 1. Logic Symbol Pin Configurations Figure 2. US8 (Top View) Figure 3. MicroPak™ (Top Through View) Pin Definitions Pin # US8 Pin # MicroPak Name 1 7 CK 2 6 D Description Clock Pulse Input Data Input 3 5 /Q 4 4 GND Flip-Flop Output 5 3 Q 6 2 /CLR Direct Clear Input 7 1 /PR Direct Preset Input 8 8 VCC Supply Voltage NC7SZ74 — TinyLogic® UHS D-Type Flip-Flop with Preset and Clear Connection Diagrams Ground Flip-Flop Output Function Table Inputs Output Function /CLR /PR D CK Q /Q L H X X L H Clear H L X X H L Preset L L X X H H H H L L H H H H   H L H H X  Qn /Qn H = HIGH Logic Level Qn = No change in data X = Immaterial L = LOW Logic Level Z = High Impedance  = Rising Edge © 2001 Fairchild Semiconductor Corporation NC7SZ74 • Rev. 1.0.2 Falling Edge No Change  www.fairchildsemi.com 2 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit 7.0 V VCC Supply Voltage -0.5 VIN DC Input Voltage -0.5 7.0 V DC Output Voltage -0.5 7.0 V VOUT IIK DC Input Diode Current VIN < 0V -50 mA IOK DC Output Diode Current VOUT < 0V -50 mA IOUT DC Output Source/Sink Current ±50 mA DC VCC or Ground Current ±50 mA +150 °C ICC or IGND TSTG Storage Temperature Range -65 TJ Junction Temperature Under Bias +150 °C TL Junction Lead Temperature (Soldering, 10 Seconds) +260 °C PD Power Dissipation at +85°C 250 mW Human Body Model, JEDEC:JESD22-A114 5000 Charge Device Model: JEDEC:JESD22-C101 2000 ESD V Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VCC VIN VOUT Parameter Conditions Min. Max. Supply Voltage Operating 1.65 5.50 Supply Voltage Data Retention 1.50 5.50 0 5.5 V Active State 0 VCC V 3-State 0 5.5 VCC=1.8V, 2.5V ± 0.2V 0 20 VCC=3.3V ± 0.3V 0 10 Input Voltage Output Voltage tr, tf Input Rise and Fall Times TA Operating Temperature JA Thermal Resistance VCC=5.0V ± 0.5V 0 5 -40 +85 US8 250 MicroPak™-8 280 Unit NC7SZ74 — TinyLogic® UHS D-Type Flip-Flop with Preset and Clear Absolute Maximum Ratings V ns/V °C °C/W Note: 1. Unused inputs must be held HIGH or LOW. They may not float. © 2001 Fairchild Semiconductor Corporation NC7SZ74 • Rev. 1.0.2 www.fairchildsemi.com 3 TA=+25°C Conditions TA=-40 to +85°C Symbol Parameter VCC VIH HIGH Level Control Input Voltage 1.65 to 1.95 0.75VCC 0.75VCC 2.30 to 5.50 0.70VCC 0.70VCC VIL LOW Level Control Input Voltage 1.65 to 1.95 0.25VCC 0.25VCC 2.30 to 5.50 0.30VCC 0.30VCC Min. 1.55 1.65 1.55 VIN=VIH, IOH=-100µA 2.20 2.30 2.20 2.90 3.00 2.90 4.40 4.50 4.40 1.65 IOH=-4mA 1.29 1.52 1.29 2.30 IOH=-8mA 1.90 2.15 1.90 3.00 IOH=-16mA 2.40 2.80 2.40 3.00 IOH=-24mA 2.30 2.68 2.30 4.50 IOH=-32mA 3.80 4.20 3.80 1.65 2.30 3.00 VIN=VIH, IOL=100µA 4.50 VOL IIN LOW Level Control Output Voltage Input Leakage Current IOFF Power Off Leakage Current ICC Quiescent Supply Current Max. Units V V V 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 1.65 IOL=4mA 0.80 0.24 0.24 2.30 IOL=8mA 0.10 0.30 0.30 3.00 IOL=16mA 0.15 0.40 0.40 3.00 IOL=24mA 0.22 0.55 0.55 4.50 IOL=32mA 0.22 0.55 0.55 ±0.1 ±1.0 µA 1 10 µA 1 10 µA 0 to 5.5 0  VIN  5.5V VIN or VOUT=5.5V 1.65 to 5.50 VIN=5.5V, GND © 2001 Fairchild Semiconductor Corporation NC7SZ74 • Rev. 1.0.2 Min. 1.65 4.50 HIGH Level Output Voltage Max. 2.30 3.00 VOH Typ. V NC7SZ74 — TinyLogic® UHS D-Type Flip-Flop with Preset and Clear DC Electrical Characteristics www.fairchildsemi.com 4 Symbol Parameter VCC TA=+25°C Conditions Min. 1.80 ± 0.15 2.50 ± 0.20 fMAX Maximum Clock Frequency 3.30 ± 0.30 CL=15pF RD=1M S1=Open 5.00 ± 0.50 3.30 ± 0.50 5.00 ± 0.50 CL=50pF RD=500, S1=Open 1.80 ± 0.15 2.50 ± 0.20 tPLH, tPHL Propagation Delay CK to Q, /Q 3.30 ± 0.30 CL=15pF, RD=1M S1=Open 5.00 ± 0.50 3.30 ± 0.30 5.00 ± 0.50 CL=50pF RD=500, S1=Open 1.80 ± 0.15 2.50 ± 0.20 tPLH, tPHL Propagation Delay /CLR, /PR to Q, /Q 3.30 ± 0.30 CL=15pF, RL=1M S1=Open 5.00 ± 0.50 3.30 ± 0.30 5.00± 0.50 CL=50pF, RD=500 S1=Open 1.80 ± 0.15 2.50 ± 0.20 3.30 ± 0.30 tS Setup Time CK to D CL=15pF, RL=1M S1=Open 5.00 ± 0.50 3.30 ± 0.30 5.00± 0.50 CL=50pF, RD=500 S1=Open 1.80 ± 0.15 2.50 ± 0.20 3.30 ± 0.30 tH Hold Time, CK to D CL=15pF, RL=1M S1=Open 5.00 ± 0.50 3.30 ± 0.30 5.00± 0.50 CL=50pF, RD=500 S1=Open 1.80 ± 0.15 2.50 ± 0.20 tW Pulse Width, CK, /PR, /CLR 3.30 ± 0.30 CL=15pF, RL=1M S1=Open 5.00 ± 0.50 3.30 ± 0.30 5.00± 0.50 CL=50pF, RD=500 S1=Open 1.80 ± 0.15 2.50 ± 0.20 tREC Recover Time /CLR, /PR to CK 3.30 ± 0.30 CL=15pF, RL=1M S1=Open 5.00 ± 0.50 3.30 ± 0.30 5.00 ± 0.50 CL=50pF, RD=500 S1=Open Typ. TA=-40 to +85°C Max. Min. 75 75 150 150 200 200 250 250 175 175 200 200 Max. 2.5 6.5 12.5 2.5 13.0 3.8 7.5 1.5 8.0 1.0 2.8 6.5 1.0 7.0 0.8 2.2 4.5 0.8 5.0 1.0 3.4 7.0 1.0 7.5 1.0 2.6 5.0 1.0 5.5 2.5 6.5 14.0 2.5 14.5 1.5 3.8 9.0 1.5 9.5 1.0 2.8 6.5 1.0 7.0 0.8 2.2 5.0 0.8 5.5 1.0 3.4 7.0 1.0 7.5 1.0 2.6 5.0 1.0 5.5 6.5 6.5 3.5 2.0 2.0 1.5 1.5 2.0 2.0 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 6.0 6.0 4.0 4.0 3.0 3.0 2.0 2.0 3.0 3.0 2.0 2.0 8.0 8.0 4.5 4.5 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 Figure Figure 4 Figure 8 1.5 3.5 Units ns Figure 4 Figure 6 ns Figure 4 Figure 6 ns Figure 4 Figure 7 ns Figure 4 Figure 7 ns Figure 4 Figure 8 ns Figure 4 Figure 7 NC7SZ74 — TinyLogic® UHS D-Type Flip-Flop with Preset and Clear AC Electrical Characteristics Continued on the following page… © 2001 Fairchild Semiconductor Corporation NC7SZ74 • Rev. 1.0.2 www.fairchildsemi.com 5 Symbol CIN COUT CPD Parameter VCC TA=+25°C Conditions Min. Typ. TA=-40 to +85°C Min. Typ. Min. Units Input Capacitance 0 3 pF Output Capacitance 0 4 pF 3.30 10 5.00 12 Power Dissipation (2) Capacitance Figure pF Note: 2. CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (ICCD) at no output loading and operating at 50% duty cycle. CPD is related to ICCD dynamic operating current by the expression: ICCD=(CPD)(VCC)(fIN)+(ICCstatic). Note: 3. CL includes load and stray capacitance. Input PRR=1.0MHz tw=500ns. Figure 4. AC Test Circuit Notes: 4. CP input=AC Waveforms tr=tf=2.5ns. 5. CP input PRR=10MHz; Duty Cycle=50%. 6. D input PRR=5MHz; Duty Cycle=50%. Figure 5. ICCD Test Circuit Figure 6. AC Waveforms NC7SZ74 — TinyLogic® UHS D-Type Flip-Flop with Preset and Clear AC Electrical Characteristics Figure 7. AC Waveforms Figure 8. AC Waveforms © 2001 Fairchild Semiconductor Corporation NC7SZ74 • Rev. 1.0.2 www.fairchildsemi.com 6 2.10 1.90 0.15 A 1.80 B 5 8 (8X) 0.70 3.20 3.00 2.40 2.20 2.70 3.40 1.00 1.55 1 PIN 1 IDENT 4 0.2 C B A ALL LEAD TIPS TOP VIEW 0.50 0.30 (8X) RECOMMENDED LAND PATTERN 0.80 0.60 0.90 MAX 0.10 0.00 ALL LEAD TIPS 0.1 C A. CONFORMS TO JEDEC REGISTRATION MO-187 B. DIMENSIONS ARE IN MILLIMETERS. SEATING PLANE C C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS. 0.17-0.27 (8X) 0.50 0.13 A B C D. DIMENSIONS AND TOLERANCES PER ANSI Y14.5M, 1994. E. FILE DRAWING NAME : MKT-MAB08Arev4 SIDE VIEW DETAIL A 0.4 TYP GAGE PLANE 0.10-0.18 0.12 0°-8° 0.20-0.35 NC7SZ74 — TinyLogic® UHS D-Type Flip-Flop with Preset and Clear Physical Dimensions SEATING PLANE DETAIL A Figure 9. 8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Tape and Reel Specifications Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/products/analog/pdf/sc70-5_tr.pdf. Package Designator K8X © 2001 Fairchild Semiconductor Corporation NC7SZ74 • Rev. 1.0.2 Tape Section Cavity Number Cavity Status Cover Type Status Leader (Start End) 125 (Typical) Empty Sealed Carrier 3000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed www.fairchildsemi.com 7 NC7SZ74 — TinyLogic® UHS D-Type Flip-Flop with Preset and Clear Physical Dimensions 0.10 2X C A 1.6 B 1.6 INDEX AREA 0.10 2X C TOP VIEW 0.55 MAX 0.05 0.05 0.00 DETAIL A 8X(0.09) C 8X Recommended Landpattern 0.05 C (0.20) 1.0 2 1 4 (0.1) C 8 0.35 0.25 3X(0.2) 0.35 0.25 0.5 3 4 7 6 5 (0.15) 0.15 8X 0.25 0.10 0.05 C A B C 0.35 0.25 DETAIL A PIN #1 TERMINAL SCALE: 2X BOTTOM VIEW Notes: 1. PACKAGE CONFORMS TO JEDEC MO-255 VARIATION UAAD 2. DIMENSIONS ARE IN MILLIMETERS 3. DRAWING CONFORMS TO ASME Y.14M-1994 4. PIN 1 FLAG, END OF PACKAGE OFFSET 5. DRAWING FILE NAME: MKT-MAC08AREV4 MAC08AREV4 Figure 10. 8-Lead, MicroPak™, 1.6mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Tape and Reel Specifications Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf. Package Designator L8X © 2001 Fairchild Semiconductor Corporation NC7SZ74 • Rev. 1.0.2 Tape Section Cavity Number Cavity Status Cover Type Status Leader (Start End) 125 (Typical) Empty Sealed Carrier 5000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed www.fairchildsemi.com 8 NC7SZ74 — TinyLogic® UHS D-Type Flip-Flop with Preset and Clear © 2001 Fairchild Semiconductor Corporation NC7SZ74 • Rev. 1.0.2 www.fairchildsemi.com 9 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. 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