NCD5703A, NCD5703B,
NCD5703C
High Current IGBT Gate
Drivers
The NCD5703A, NCD5703B and NCD5703C are high−current,
high−performance stand−alone IGBT drivers for high power
applications that include solar inverters, motor control and
uninterruptible power supplies. The devices offer a cost−effective
solution by eliminating external output buffer. Devices protection
features include accurate Under−voltage−lockout (UVLO),
desaturation protection (DESAT) and Active open−drain FAULT
output. The drivers also feature an accurate 5.0 V output. The drivers
are designed to accommodate a wide voltage range of bias supplies
including unipolar and NCD5703B even bipolar voltages.
Depending on the pin configuration the devices also include Active
Miller Clamp (NCD5703A) and separate high and low (VOH and VOL)
driver outputs for system design convenience (NCD5703C).
All three available pin configuration variants have 8−pin SOIC
package.
Features
•
•
•
•
•
•
•
•
High Current Output (+4/−6 A) at IGBT Miller Plateau voltages
Low Output Impedance for Enhanced IGBT Driving
Short Propagation Delay with Accurate Matching
Direct Interface to Digital Isolator/Opto−coupler/Pulse Transformer
for Isolated Drive, Logic Compatibility for Non−isolated Drive
DESAT Protection with Programmable Delay
Tight UVLO Thresholds for Bias Flexibility
Wide Bias Voltage Range
This Device is Pb−Free, Halogen−Free and RoHS Compliant
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MARKING
DIAGRAM
8
• Active Miller Clamp to Prevent Spurious Gate Turn−on
1
NCD5703 = Specific Device Code
X
= A, B or C
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
PIN CONNECTIONS
VIN
VREF
FLT
DESAT
1
8
2
7
3
6
4
5
VIN
DESAT
1
8
2
7
3
6
4
5
NCD5703C Features
VIN
• Separate Outputs for VOL and VOH
VREF
FLT
Typical Applications
DESAT
Solar Inverters
Motor Control
Uninterruptible Power Supplies (UPS)
Rapid Shutdown for Photovoltaic Systems
© Semiconductor Components Industries, LLC, 2018
August, 2019 − Rev. 1
GND
VO
VCC
VEE
GND
VO
VCC
NCD5703B
• Negative Output Voltage for Enhanced IGBT Driving
•
•
•
•
CLAMP
NCD5703A
FLT
NCD5703B Features
NCD5703X
ALYW
G
SOIC−8
D SUFFIX
CASE 751
VREF
NCD5703A Features
8
1
1
8
2
7
3
6
4
5
GND
VOL
VOH
VCC
NCD5703C
ORDERING INFORMATION
See detailed ordering and shipping information on page 9 of
this data sheet.
1
Publication Order Number:
NCD5703/D
NCD5703A, NCD5703B, NCD5703C
NCD5703A
VREF
DESAT
VCC
VCC
VO
CLAMP
VIN
GND
FLT
NCD5703B
VREF
DESAT
VCC
VCC
VO
VIN
GND
VEE
VEE
FLT
NCD5703C
VREF
DESAT
VCC
VCC
VOH
VOL
VIN
GND
FLT
Figure 1. Simplified Application Schematics
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2
NCD5703A, NCD5703B, NCD5703C
FLT
TSD
SET
Q
Q
S
CLR
R
NCD5703A
IDESAT-CHG
DELAY
DESAT
+
VDESAT-THR
SET
Q
S
-
R
CLR
VCC
Q
VREF
VIN
VREF
VO
RIN-
DELAY
Bandgap
VUVLO
-
VCC
+
SET
Q
S
R
CLR
Q
-
CLAMP
+
VMC-THR
GND
Figure 2(a). Detailed Block Diagram NCD5703A
NCD5703A
CLAMP
VIN
CLAMP
VCC
LDO
GND
FLT
TSD
VCC
Logic Unit
VREF
VO
UVLO
DESAT
VCC
DESAT
Figure 2(b). Simplified Block Diagram NCD5703A
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3
NCD5703A, NCD5703B, NCD5703C
FLT
TSD
SET
Q
Q
S
CLR
R
NCD5703B
IDESAT-CHG
DESAT
DELAY
+
VDESAT-THR
SET
Q
S
-
R
CLR
VCC
Q
VREF
VIN
VO
RIN-L
VREF
DELAY
Bandgap
VUVLO
VEE
-
VCC
+
GND
Figure 3(a). Detailed Block Diagram NCD5703B
VEE
NCD5703B
VEE
VIN
VCC
LDO
GND
FLT
TSD
VCC
Logic Unit
VREF
VO
UVLO
DESAT
VCC
DESAT
Figure 3(b). Simplified Block Diagram NCD5703B
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4
NCD5703A, NCD5703B, NCD5703C
FLT
TSD
SET
Q
Q
S
CLR
R
NCD5703C
IDESAT-CHG
DELAY
DESAT
+
VDESAT-THR
SET
Q
S
-
R
CLR
VCC
Q
VREF
VOH
VIN
RIN-L
VOL
DELAY
VREF
Bandgap
VUVLO
+
VCC
GND
Figure 4(a). Detailed Block Diagram NCD5703C
NCD5703C
GND
VIN
VCC
LDO
VOL
FLT
TSD
VCC
Logic Unit
VREF
VOH
UVLO
DESAT
VCC
DESAT
Figure 4(b). Simplified Block Diagram NCD5703C
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5
NCD5703A, NCD5703B, NCD5703C
Table 1. PIN FUNCTION DESCRIPTION
Pin Name
No.
I/O/x
Description
VIN
1
I
Input signal to control the output. In applications which require galvanic isolation, VIN is generated at the opto output, the pulse transformer secondary or the digital isolator output. VO (VOH/
VOL) signal is in phase with VIN. VIN is internally clamped to GND and has a pull−down resistor
of 1 MW to ensure that an output is low in the absence of an input signal. A minimum pulse−
width is required at VIN before VO (VOH/VOL) is activated.
VREF
2
O
5 V Reference generated within the driver is brought out to this pin for external bypassing and
for powering low bias circuits (such as digital isolators).
FLT
3
O
Fault open drain output (active low) that allows communication to the main controller that the
driver has encountered a fault condition and has deactivated the output. Open drain allows easy
setting of (inactive) high level and parallel connection of multiple fault signals.
Connect to 10k pull−up resistor recommended. Truth Table is provided in the datasheet to indicate conditions under which this signal is asserted. Capable of driving optos or digital isolators
when isolation is required.
DESAT
4
I
Input for detecting the desaturation of IGBT due to a fault condition. A capacitor connected to
this pin allows a programmable blanking delay every ON cycle before DESAT fault is processed,
thus preventing false triggering.
VCC
5
x
Positive bias supply for the driver. The operating range for this pin is from UVLO to the maximum. A good quality bypassing capacitor is required from this pin to GND and should be placed
close to the pins for best results.
VO
(NCD5703A,
NCD5703B)
6
O
Driver output that provides the appropriate drive voltage, source and sink current to the IGBT
gate. VO is actively pulled low during start−up and under Fault conditions.
VOH
(NCD5703C)
6
O
Driver high output that provides the appropriate drive voltage and source current to the IGBT
gate.
VOL
(NCD5703C)
7
O
Driver low output that provides the appropriate drive voltage and sink current to the IGBT gate.
VOL is actively pulled low during start−up and under Fault conditions.
GND
(NCD5703A,
NCD5703B)
7
x
This pin should connect to the IGBT Emitter with a short trace. All power pin bypass capacitors
should be referenced to this pin and kept at a short distance from the pin.
GND
(NCD5703C)
8
x
This pin should connect to the IGBT Emitter with a short trace. All power pin bypass capacitors
should be referenced to this pin and kept at a short distance from the pin.
VEE
(NCD5703B)
8
x
A negative voltage with respect to GND can be applied to this pin and that will allow VO to go to
a negative voltage during OFF state. A good quality bypassing capacitor is needed from VEE to
GND. If a negative voltage is not applied or available, this pin must be connected to GND.
CLAMP
(NCD5703A)
8
I/O
Provides clamping for the IGBT gate during the off period to protect it from parasitic turn−on. To
be tied directly to IGBT gate with minimum trace length for best results.
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6
NCD5703A, NCD5703B, NCD5703C
Table 2. ABSOLUTE MAXIMUM RATINGS (Note 1)
Parameter
Differential Power Supply
Positive Power Supply
Negative Power Supply
Symbol
Minimum
Maximum
Unit
VCC−VEE (Vmax)
0
36
V
VCC−GND
−0.3
22
V
VEE−GND
−18
0.3
V
VCC + 0.3
V
Gate Output High
(VO, VOH)−GND
Gate Output Low
(VO, VOL)−GND
VEE − 0.3
VIN−GND
−0.3
5.5
V
VDESAT−GND
−0.3
VCC + 0.3
V
Input Voltage
DESAT Voltage
FLT current
Sink
V
mA
Power Dissipation
SO−8 package
Maximum Junction Temperature
Storage Temperature Range
IFLT−SINK
20
PD
700
mW
TJ(max)
150
°C
TSTG
−65 to 150
°C
ESD Capability, Human Body Model (Note 2)
ESDHBM
4
kV
ESD Capability, Machine Model (Note 2)
ESDMM
200
V
Moisture Sensitivity Level
MSL
1
−
Lead Temperature Soldering
Reflow (SMD Styles Only), Pb−Free Versions (Note 3)
TSLD
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latchup Current Maximum Rating: ≤100 mA per JEDEC standard: JESD78, 25°C
3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
Table 3. THERMAL CHARACTERISTICS
Parameter
Symbol
Value
RqJA
176
Thermal Characteristics, SOIC−8 (Note 4)
Thermal Resistance, Junction−to−Air (Note 5)
Unit
°C/W
4. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
5. Values based on copper area of 100 mm2 (or 0.16 in2) of 1 oz copper thickness and FR4 PCB substrate.
Table 4. OPERATING RANGES (Note 6)
Parameter
Differential Power Supply
Symbol
Min
VCC−VEE (Vmax)
Max
Unit
30
V
Positive Power Supply
VCC
UVLO
20
V
Negative Power Supply
VEE
−15
0
V
Input Voltage
VIN
0
5
V
Input pulse width
ton
40
Ambient Temperature
TA
−40
125
°C
ns
6. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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NCD5703A, NCD5703B, NCD5703C
Table 5. ELECTRICAL CHARACTERISTICS VCC = 15 V, VEE = 0 V, Kelvin GND connected to VEE. For typical values TA = 25°C,
for min/max values, TA is the operating ambient temperature range that applies, unless otherwise noted.
Parameter
Test Conditions
Symbol
Min
Input Threshold Voltages
High−state (Logic 1) Required
Low−state (Logic 0) Required
No state change
Pulse−Width = 150 ns, VEN = 5 V
Voltage applied to get output to go high
Voltage applied to get output to go low
Voltage applied without change in output state
VIN−H1
VIN−L1
VIN−NC
4.3
Input Current
High−state
Low−state
VIN−H = 4.5 V
VIN−L = 0.5 V
Typ
Max
Unit
LOGIC INPUT and OUTPUT
Input Pulse−Width
No Response at the Output
Guaranteed Response at the
Output
FLT Threshold Voltage
Low State
High State
V
0.75
3.7
1.2
mA
Voltage thresholds consistent with input
specs
IIN−H
IIN−L
10
1
ton−min1
ton−min2
15
ns
35
V
(IFLT−SINK = 15 mA)
External pull−up
VFLT−L
VFLT−H
0.5
1.0
VCC+0.3
Isink = 200 mA, TA = 25°C
Isink = 200 mA, TA = −40°C to 125°C
Isink = 1.0 A, TA = 25°C
VOL1
VOL2
VOL3
0.1
0.2
0.8
0.2
0.5
1.2
Isrc = 200 mA, TA = 25°C
Isrc = 200 mA, TA = −40°C to 125°C
Isrc = 1.0 A, TA = 25°C
VOH1
VOH2
VOH3
Peak Driver Current, Sink
(Note 7)
RG = 0.1 W, VCC = 15 V, VEE = −8 V
VO = 13 V
VO = 9 V (near Miller Plateau)
IPK−snk1
IPK−snk2
6.8
6.1
Peak Driver Current, Source
(Note 7)
RG = 0.1 W, VCC = 15 V, VEE = −8 V
VO = −5 V
VO = 9 V (near Miller Plateau)
IPK−src1
IPK−src2
7.8
4.0
DRIVE OUTPUT
V
Output Low State
Output High State
V
14.5
14.2
13.8
14.8
14.7
14.1
A
A
DYNAMIC CHARACTERISTICS
Turn−on Delay
(see timing diagram)
Negative input pulse width = 10 ms
tpd−on
45
59
75
ns
Turn−off Delay
(see timing diagram)
Positive input pulse width = 10 ms
tpd−off
45
54
75
ns
Propagation Delay Distortion
(=tpd−on− tpd−off)
For input or output pulse width > 150 ns,
TA = 25°C
TA = −40°C to 125°C
tdistort1
tdistort2
−5
−25
5
15
25
tdistort −tot
−30
0
30
Prop Delay Distortion between
Parts (Note 7)
ns
ns
Rise Time (Note 7)
(see timing diagram)
Cload = 1.0 nF
trise
9.2
ns
Fall Time (Note 7)
(see timing diagram)
Cload = 1.0 nF
tfall
7.9
ns
Delay from FLT under UVLO/
TSD to VO/VOL
td1−OUT
Delay from DESAT to VO/VOL
(Note 7)
td2−OUT
7. Values based on design and/or characterization.
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8
10
12
220
15
ms
ns
NCD5703A, NCD5703B, NCD5703C
Table 5. ELECTRICAL CHARACTERISTICS VCC = 15 V, VEE = 0 V, Kelvin GND connected to VEE. For typical values TA = 25°C,
for min/max values, TA is the operating ambient temperature range that applies, unless otherwise noted.
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
DYNAMIC CHARACTERISTICS
Delay from UVLO/TSD to FLT
(Note 7)
td3−FLT
7.3
Vclamp
1.2
1.4
2.2
V
ms
MILLER CLAMP (NCD5703A ONLY)
Isink = 500 mA, TA = 25°C
Isink = 500 mA, TA = −40°C to 125°C
Clamp Voltage
Clamp Activation Threshold
VMC−THR
1.8
2.0
2.2
V
DESAT Threshold Voltage
VDESAT−THR
6.0
6.35
7.0
V
Blanking Charge Current
IDESAT−CHG
0.20
0.24
0.28
mA
Blanking Discharge Current
IDESAT−DIS
DESAT PROTECTION
30
mA
UVLO
UVLO Startup Voltage
VUVLO−OUT−ON
13.2
13.5
13.8
V
UVLO Disable Voltage
VUVLO−OUT−OFF
12.2
12.5
12.8
V
UVLO Hysteresis
VUVLO−HYST
1.0
V
VREF
Voltage Reference
IREF = 10 mA
VREF
Reference Output Current
(Note 7)
4.85
5.00
5.15
V
20
mA
IREF
Recommended Capacitance
CVREF
100
nF
SUPPLY CURRENT
Current Drawn from VCC
VCC = 15 V
Standby (No load on output, FLT, VREF)
ICC−SB
Current Drawn from VEE
(NCD5703B ONLY)
VEE = −10 V
Standby (No load on output, FLT, VREF)
IEE−SB
0.9
−0.2
1.5
mA
−0.14
mA
THERMAL SHUTDOWN
Thermal Shutdown Temperature
(Note 7)
TSD
188
°C
Thermal Shutdown Hysteresis
(Note 7)
TSH
33
°C
7. Values based on design and/or characterization.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
ORDERING INFORMATION
Package
Shipping†
NCD5703ADR2G
SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCD5703BDR2G
SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCD5703CDR2G
SOIC−8
(Pb−Free)
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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9
NCD5703A, NCD5703B, NCD5703C
TYPICAL CHARACTERISTICS
PROPAGATION DELAY (ns)
80
70
tpd−on
60
tpd−off
50
40
−40
−20
0
20
40
60
80
120
100
TEMPERATURE (°C)
Figure 5. Propagation Delay vs. Temperature
20
13
12
11
10
−40
IO (A)
RISE/FALL TIME (ns)
14
−20
0
20
40
60
80
100
15
trise
5
−20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 6. Fault to Output Low Delay
Figure 7. Output Rise/Fall Time
8
8
7
7
6
6
5
5
4
3
2
2
1
1
0
5
10
0
−5
15
0
5
10
VO (V, VCC = 15 V, VEE = −8 V)
VO (V, VCC = 15 V, VEE = −8 V)
Figure 8. Output Source Current vs. Output
Voltage
Figure 9. Output Sink Current vs. Output
Voltage
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10
120
4
3
0
−5
tfall
10
0
−40
120
IO (A)
FAULT TO OUTPUT DELAY (ms)
15
15
NCD5703A, NCD5703B, NCD5703C
5.05
5.05
5.04
5.04
5.03
5.03
5.02
5.02
5.01
5.01
VREF (V)
VREF (V)
TYPICAL CHARACTERISTICS
5.00
4.99
4.98
4.97
4.97
4.96
4.95
4.96
4.95
−40
0
2
4
6
8
10
VREF @ IREF = 10 mA
−20
0
20
40
60
80
100
IREF (mA)
TEMPERATURE (°C)
Figure 10. VREF Voltage vs. Current
Figure 11. VREF Voltage vs. Temperature
120
6.5
VDESAT (V)
IDESET−CHG (mA)
5.00
4.99
4.98
260
250
240
−40
−20
0
20
40
60
80
100
6.4
6.3
6.2
−40
120
−20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12. DESAT Charge Current vs.
Temperature
Figure 13. DESAT Threshold Voltage vs.
Temperature
120
20
15
15
10
UVLO−OUT−OFF
UVLO−OUT−ON
VO (V)
VO, OUTPUT VOLTAGE (V)
VREF @ IREF = 0 mA
10
5
5
0
0
10
11
12
13
14
−5
15
0
1
2
3
VCC, SUPPLY VOLTAGE (V)
VIN (V)
Figure 14. UVLO Threshold Voltages
Figure 15. VO vs. VIN at 255C
(VCC = 15 V, VEE = 0 V)
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4
5
NCD5703A, NCD5703B, NCD5703C
TYPICAL CHARACTERISTICS
1.0
2.5
VCLAMP (V)
0.5
1.5
1.0
0
−40
−20
0
20
40
60
80
100
0.5
−40
120
−20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 16. Fault Output, Sinking 15 mA
Figure 17. VCLAMP at 0.5 A (NCD5703A Only)
1.4
1.2
SUPPLY CURRENT (mA)
VFLT−L (V)
2.0
ICC
1.0
0.8
0.6
0.4
IEE (NCD5703B Only)
0.2
0
0
20
40
60
80
FREQUENCY (kHz)
Figure 18. Supply Current vs. Switching
Frequency (VCC = 15 V, VEE = −10 V, 255C)
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12
100
NCD5703A, NCD5703B, NCD5703C
Applications and Operating Information
This section lists the details about key features and
operating guidelines for the NCD5703.
High Drive Current Capability
The NCD5703 driver family is equipped with many
features which facilitate a superior performance IGBT
driving circuit. Foremost amongst these features is the high
drive current capability. The drive current of an IGBT driver
is a function of the differential voltage on the output pin
(VCC−VOH/VO for source current, VOL/VO−VEE for sink
current) as shown in Figure 19. Figure 19 also indicates that
for a given VOH/VOL value, the drive current can be
increased by using higher VCC/VEE power supply). The
drive current tends to drop off as the output voltage goes up
(for turn−on event) or goes down (for turn−off event). As
explained in many IGBT application notes, the most critical
phase of IGBT switching event is the Miller plateau region
where the gate voltage remains constant at a voltage
(typically in 9−11 V range depending on IGBT design and
the collector current), but the gate drive current is used to
charge/discharge the Miller capacitance (CGC). By
providing a high drive current in this region, a gate driver can
significantly reduce the duration of the phase and help
reducing the switching losses. The NCD5703 addresses this
requirement by providing and specifying a high drive
current in the Miller plateau region. Most other gate driver
ICs merely specify peak current at the start of switching –
which may be a high number, but not very relevant to the
application requirement. It must be remembered that other
considerations such as EMI, diode reverse recovery
performance, etc., may lead to a system level decision to
trade off the faster switching speed against low EMI and
reverse recovery. However, the use of NCD5703 does not
preclude this trade−off as the user can always tune the drive
current by employing external series gate resistor. Important
thing to remember is that by providing a high internal drive
current capability, the NCD5703 facilitates a wide range of
gate resistors. Another value of the high current at the Miller
plateau is that the initial switching transition phase is shorter
and more controlled. Finally, the high gate driver current
(which is facilitated by low impedance internal FETs),
ensures that even at high switching frequencies, the power
dissipation from the drive circuit is primarily in the external
series resistor and more easily manageable. Experimental
results have shown that the high current drive results in
reduced turn−on energy (EON) for the IGBT switching.
Figure 19. Output Current vs. Output Voltage Drop
When driving larger IGBTs for higher current
applications, the drive current requirement is higher, hence
lower RG is used. Larger IGBTs typically have high input
capacitance. On the other hand, if the NCD5703 is used to
drive smaller IGBT (lower input capacitance), the drive
current requirement is lower and a higher RG is used. Thus,
for most typical applications, the driver load RC time
constant remains fairly constant. Caution must be exercised
when using the NCD5703 with a very low load RC time
constant. Such a load may trigger internal protection
circuitry within the driver and disable the device. Figure 20
shows the recommended minimum gate resistance as a
function of IGBT gate capacitance and gate drive trace
inductance.
Figure 20. Recommended Minimum Gate Resistance
as a Function of IGBT Gate Capacitance
www.onsemi.com
13
NCD5703A, NCD5703B, NCD5703C
Gate Voltage Range
controller to initiate a more orderly/sequenced shutdown. In
case the controller fails to do so, the driver output shutdown
ensures IGBT protection after td1−OUT.
The negative drive voltage for gate (with respect to GND,
or Emitter of the IGBT) is a robust way to ensure that the gate
voltage does not rise above the threshold voltage due to the
Miller effect. In systems where the negative power supply is
available, the VEE option offered by NCD5703B allows not
only a robust operation, but also a higher drive current for
turn−off transition. Adequate bypassing between VEE pin
and GND pin is essential if this option is used.
The VCC range for the NCD5703 is quite wide and allows
the user the flexibility to optimize the performance or use
available power supplies for convenience.
Under Voltage Lock Out (UVLO)
This feature ensures reliable switching of the IGBT
connected to the driver output. At the start of the driver’s
operation when VCC is applied to the driver, the output
remains turned−off. This is regardless of the signals on VIN
until the VCC reaches the UVLO Output Enabled
(VUVLO−OUT−ON) level. After the VCC rises above the
VUVLO−OUT−ON level, the driver is in normal operation. The
state of the output is controlled by signal at VIN.
If the VCC falls below the UVLO Output Disabled
(VUVLO−OUT−OFF) level during the normal operation of the
driver, the Fault output is activated and the output is shut−down
(after a delay) and remains in this state. The driver output
does not start to react to the input signal on VIN until the VCC
rises above the VUVLO−OUT−ON again. The waveform
showing the UVLO behavior of the driver is in Figure 21.
In an IGBT drive circuit, the drive voltage level is
important for drive circuit optimization. If VUVLO−OUT−OFF
is too low, it will lead to IGBT being driven with insufficient
gate voltage. A quick review of IGBT characteristics can
reveal that driving IGBT with low voltage (in 10−12 V
range) can lead to a significant increase in conduction loss.
So, it is prudent to guarantee VUVLO−OUT−OFF at a
reasonable level (above 12 V), so that the IGBT is not forced
to operate at a non−optimum gate voltage. On the other hand,
having a very high drive voltage ends up increasing
switching losses without much corresponding reduction in
conduction loss. So, the VUVLO−OUT−ON value should not
be too high (generally, well below 15 V). These conditions
lead to a tight band for UVLO enable and disable voltages,
while guaranteeing a minimum hysteresis between the two
values to prevent hiccup mode operation. The NCD5703
meets these tight requirements and ensures smooth IGBT
operation. It ensures that a 15 V supply with ±8% tolerance
will work without degrading IGBT performance, and
guarantees that a fault will be reported and the IGBT will be
turned off when the supply voltage drops below 12.2 V.
A UVLO event (VCC voltage going below VUVLO−OUT−OFF)
also triggers activation of FLT output after a delay of td3−FLT.
This indicates to the controller that the driver has
encountered an issue and corrective action needs to be taken.
However, a nominal delay td1−OUT = 12 ms is introduced
between the initiation of the FLT output and actual turning
off of the output. This delay provides adequate time for the
Figure 21. UVLO Function and Limits
Timing Delays and Impact on System Performance
The gate driver is ideally required to transmit the input
signal pulse to its output without any delay or distortion. In
the context of a high−power system where IGBTs are
typically used, relatively low switching frequency (in tens of
kHz) means that the delay through the driver itself may not
be as significant, but the matching of the delay between
different drivers in the same system as well as between
different edges has significant importance. With reference to
Figure 22(a), two input waveforms are shown. They are
typical complementary inputs for high−side (HS) and
low−side (LS) of a half−bridge switching configuration. The
dead−time between the two inputs ensures safe transition
between the two switches. However, once these inputs are
through the driver, there is potential for the actual gate
voltages for HS and LS to be quite different from the
intended input waveforms as shown in Figure 22(a). The end
result could be a loss of the intended dead−time and/or
pulse−width distortion. The pulse−width distortion can
create an imbalance that needs to be corrected, while the loss
of dead−time can eventually lead to cross−conduction of the
switches and additional power losses or damage to the
system.
The NCD5703 driver is designed to address these timing
challenges by providing a very low pulse−width distortion
and excellent delay matching. As an example, the delay
matching is guaranteed to tDISTORT2 = ±25 ns while many
of competing driver solutions can be >250 ns.
www.onsemi.com
14
NCD5703A, NCD5703B, NCD5703C
Figure 22(a). Timing Waveforms (Other Drivers)
Figure 22(b). NCD5703 Timing Waveforms
Active Miller Clamp Protection
An alternative way is to provide an additional path from
gate to GND with very low impedance. This is exactly what
Active Miller Clamp protection does. Additional trace from
the gate of the IGBT to the Clamp pin of the gate driver is
introduced. After the VO output has gone below the Active
Miler Clamp threshold VMC−THR the Clamp pin is shorted
to GND and thus prevents the voltage on the gate of the
IGBT to rise above the threshold voltage as shown in
Figure 24. The Clamp pin is disconnected from GND as
soon as the signal to turn on the IGBT arrives to the gate
driver input. The fact that the Clamp pin is engaged only
after the gate voltage drops below the VMC−THR threshold
ensures that the function of this pin does not interfere with
the normal turn−off switching performance that is user
controllable by choice of RG.
This feature (offered by NCD5703A) is a cost savvy
alternative to a negative gate voltage. The main requirement
is to hold the gate of the turned−off (for example low−side)
IGBT below the threshold voltage during the turn−on of the
opposite−side (in this example high−side) IGBT in the half
bridge. The turn−on of the high−side IGBT causes high dv/dt
transition on the collector of the turned−off low−side IGBT.
This high dv/dt then induces current (Miller current) through
the CGC capacitance (Miller capacitance) to the gate
capacitance of the low−side IGBT as shown in Figure 23. If
the path from gate to GND has critical impedance (caused
by RG) the Miller current could rise the gate voltage above
the threshold level. As a consequence the low−side IGBT
could be turned on for a few tens or hundreds of
nanoseconds. This causes higher switching losses. One way
to avoid this situation is to use negative gate voltage, but this
requires second DC source for the negative gate voltage.
www.onsemi.com
15
NCD5703A, NCD5703B, NCD5703C
Figure 23. Current Path without Miller Clamp
Protection
Figure 24. Current Path with Miller Clamp Protection
Desaturation Protection (DESAT)
At the turned−on output state of the driver, the current
IDESAT−CHG from current source starts to flow to the
blanking capacitor CBLANK, connected to DESAT pin.
Appropriate value of this capacitor has to be selected to
ensure that the DESAT pin voltage does not rise above the
threshold level VDESAT−THR before the IGBT fully turns on.
The blanking time is given by following expression.
According to this expression, a 47 pF CBLANK will provide
a blanking time of (47p *6.5/0.25m =) 1.22 ms.
This feature monitors the collector−emitter voltage of the
IGBT in the turned−on state. When the IGBT is fully turned
on, it operates in a saturation region. Its collector−emitter
voltage (called saturation voltage) is usually low, well below
3 V for most modern IGBTs. It could indicate an overcurrent
or similar stress event on the IGBT if the collector−emitter
voltage rises above the saturation voltage, after the IGBT is
fully turned on. Therefore the DESAT protection circuit
compares the collector−emitter voltage with a voltage level
VDESAT−THR to check if the IGBT didn’t leave the saturation
region. It will activate FLT output and shut down driver
output (thus turn−off the IGBT), if the saturation voltage
rises above the VDESAT−THR. This protection works on
every turn−on phase of the IGBT switching period.
At the beginning of turning−on of the IGBT, the
collector−emitter voltage is much higher than the saturation
voltage level which is present after the IGBT is fully turned
on. It takes almost 1 ms between the start of the IGBT turn−on
and the moment when the collector−emitter voltage falls to
the saturation level. Therefore the comparison is delayed by
a configurable time period (blanking time) to prevent false
triggering of DESAT protection before the IGBT
collector−emitter voltage falls below the saturation level.
Blanking time is set by the value of the capacitor CBLANK.
The exact principle of operation of DESAT protection is
described with reference to Figure 25.
At the turned−off output state of the driver, the DESAT pin
is shorted to ground via the discharging transistor (QDIS).
Therefore, the inverting input holds the comparator output
at low level.
t BLANK + C BLANK @
V DESAT−THR
I DESAT−CHG
After the IGBT is fully turned−on, the IDESAT−CHG flows
through the DESAT pin to the series resistor RS−DESAT and
through the high voltage diode and then through the
collector and IGBT to the emitter. Care must be taken to
select the resistor RS−DESAT value so that the sum of the
saturation voltage, drop on the HV diode and drop on the
RS−DESAT caused by current IDESAT−CHG flowing from
DESAT source current is smaller than the DESAT threshold
voltage. Following expression can be used:
V DESAT−THR u
R S−DESAT @ I DESAT−CHG ) V F_HV diode ) V CESAT_IGBT
Important part for DESAT protection to work properly is
the high voltage diode. It must be rated for at least same
voltage as the low side IGBT. The safety margin is
application dependent.
The typical waveforms for IGBT overcurrent condition
are outlined in Figure 26.
www.onsemi.com
16
NCD5703A, NCD5703B, NCD5703C
Figure 25. Desaturation Protection Schematic
Figure 26. Desaturation Protection Waveforms
www.onsemi.com
17
NCD5703A, NCD5703B, NCD5703C
Input Signal
The input signal controls the gate driver output. Figure 27
shows the typical connection diagrams for isolated
applications where the input is coming through an
opto−coupler or a pulse transformer.
Figure 27. Opto−coupler or Pulse Transformer At Input
The relationship between gate driver input signal from a
pulse transformer (Figure 28) or opto−coupler (Figure 29)
and the output is defined by many time and voltage values.
The time values include output turn−on and turn−off delays
(tpd−on and tpd−off), output rise and fall times (trise and tfall)
and minimum input pulse−width (ton−min). Note that the
delay times are defined from 50% of input transition to first
10% of the output transition to eliminate the load
dependency. The input voltage parameters include input
high (VIN−H1) and low (VIN−L1) thresholds as well as the
input range for which no output change is initiated
(VIN−NC).
VIN-H1
VIN-NC
VIN
VIN-L1
tpd-on
trise
tpd-on
tfall
ton-min
90%
VOUT
10%
Figure 28. Input and Output Signal Parameters for Pulse Transformer
www.onsemi.com
18
NCD5703A, NCD5703B, NCD5703C
VIN-H1
VIN-NC
VIN
VIN-L1
tpd-on
trise
ton-min
tfall
tpd-on
VOUT
90%
10%
Figure 29. Input and Output Signal Parameters for Opto−coupler
Use of VREF Pin
highly stable over temperature and line/load variations (see
characteristics curves for details)
The NCD5703 provides an additional 5.0 V output
(VREF) that can serve multiple functions. This output is
capable of sourcing up to 10 mA current for functions such
as opto−coupler interface or external comparator interface.
The VREF pin should be bypassed with at least a 100 nF
capacitor (higher the better) irrespective of whether it is
being utilized for external functionality or not. VREF is
Fault Output Pin
This pin provides the feedback to the controller about the
driver operation. The situations in which the FLT signal
becomes active (low value) are summarized in the Table 6.
Table 6. FLT LOGIC TRUTH TABLE
VIN
UVLO
DESAT
Internal TSD
VOUT
FLT
L
Inactive
L
L
L
Open drain
Normal operation − Output Low
Notes
H
Inactive
L
L
H
Open drain
Normal operation − Output High
X
Active
X
L
L
L
UVLO activated − FLT Low (td3-FLT), Output Low
(td3-FLT + td1−OUT)
H
Inactive
H
L
L
L
DESAT activated (only when VIN is High) − Output
Low (td2_OUT), FLT Low
X
Inactive
X
H
L
L
Internal Thermal Shutdown − FLT Low (td3-FLT ), Output Low (td3-FLT + td1−OUT)
Thermal Shutdown
(12 ms), the output is pulled low and many of the internal
circuits are turned off. The 12 ms delay is meant to allow the
controller to perform an orderly shutdown sequence as
appropriate. Once the temperature goes below the second
threshold, the part becomes active again.
The NCD5703 also offers thermal shutdown function that
is primarily meant to self−protect the driver in the event that
the internal temperature gets excessive. Once the
temperature crosses the TSD threshold, the FLT output is
activated after a delay of td3-FLT. After a delay of td1−OUT
www.onsemi.com
19
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
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TECHNICAL SUPPORT
North American Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada
Phone: 011 421 33 790 2910
Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative
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