Half Bridge Gate Driver
(Isolated High &
Non-Isolated Low)
NCD57200
The NCD57200 is a high voltage gate driver with one non−isolated
low side gate driver and one galvanically isolated high or low side gate
driver. It can directly drive two IGBTs in a half bridge configuration.
Isolated high side driver can be powered with an isolated power supply
or with Bootstrap technique from the low side power supply.
The galvanic isolation for the high side gate driver guarantees
reliable switching in high power applications for IGBTs that operate
up to 800 V, at high dv/dt. The optimized output stages provide a mean
of reducing IGBT losses. Its features include two independent inputs
with deadtime and interlock, accurate asymmetric UVLOs, and short
and matched propagation delays. The NCD57200 operates with its
VDD/VBS up to 20 V.
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1
SOIC−8 NB
CASE 751−07
MARKING DIAGRAM
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
High Peak Output Current (+1.9 A/−2.3 A)
Low Output Voltage Drop for Enhanced IGBT Conduction
Floating Channel for Bootstrap Operation up to +800 V
CMTI up to 100 kV/ms
Reliable Operation for VS Negative Swing to −800 V
VDD & VBS Supply Range up to 20 V
3.3 V, 5 V, and 15 V Logic Input
Asymmetric Under Voltage Lockout Thresholds for High Side and
Low Side
Matched Propagation Delay 90 ns
Built−in 20 ns Minimum Pulse Width Filter (or Input Noise Filter)
Built−in 340 ns Dead−Time and High and Low Inputs Interlock
Non−Inverting Output Signal
This Device is Pb−Free, Halogen Free/BFR Free and is RoHS
Compliant
Typical Applications
•
•
•
•
Fans, Pumps
Home Appliances
Consumer Electronics
General Purpose Half Bridge Applications
8
NCD57200
ALYWX
G
1
NCD57200
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
VDD
VB
HIN
HO
LIN
VS
GND
LO
ORDERING INFORMATION
See detailed ordering and shipping information on page 15 of
this data sheet.
© Semiconductor Components Industries, LLC, 2019
July, 2020 − Rev. 1
1
Publication Order Number:
NCD57200/D
NCD57200
VB
VDD
VDD
UVLO2
Minimum
Pulse
Width
HIN
Input
Logic
HO
Output
Logic
VS
Deadtime
and
Interlock
VDD
Minimum
Pulse
Width
LIN
Matching
Delay
UVLO1
GND
Figure 1. Simplified Block Diagram
VDD
VDD
VB
HIN
HO
LIN
VS
GND
LO
Figure 2. Simplified Application Schematics
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LO
NCD57200
Table 1. FUNCTION DESCRIPTION
Pin Name
No.
I/O
Description
VDD
1
Power
Low side and main power supply. A good quality bypassing capacitor is required
from this pin to GND and should be placed close to the pins for best results.
The under voltage lockout (UVLO) circuit enables the device to operate at power
on when a typical supply voltage higher than VUVLO1−OUT−ON is present. Please
see Figure 5 for more details. A filter time tUVF1 helps to suppress noise on VDD
pin.
HIN
2
I
High side non-inverting gate driver input. It has an equivalent pull−down resistor
of 125 kW to ensure that output is low in the absence of an input signal.
A minimum positive or negative going pulse width is required at HIN before HO
reacts.
It adopts 3.3 V logic signal thresholds for input voltage up to VDD.
There is deadtime and interlocking logic between HIN and LIN.
LIN
3
I
Low side non-inverting gate driver input. It has an equivalent pull−down resistor
of 125 kW to ensure that output is low in the absence of an input signal.
A minimum positive or negative going pulse width is required at LIN before LO
reacts.
It adopts 3.3 V logic signal thresholds for input voltage up to VDD.
There is deadtime and interlocking logic between HIN and LIN.
GND
4
Power
LO
5
O
VS
6
Power
HO
7
O
VB
8
Power
Logic ground and low side driver return.
Low side driver output that provides the appropriate drive voltage and source/
sink current to the IGBT gate. LO is actively pulled low during startup and under
UVLO1 condition. There is deadtime and interlocking logic to prevent unintended
HO and LO cross conduction.
Bootstrap return or high side floating supply offset.
Galvanically isolated high side driver output that provides the appropriate drive
voltage and source/sink current to the IGBT gate. HO is actively pulled low
during startup and under UVLOx condition. There is deadtime and interlocking
logic to prevent unintended HO and LO cross conduction.
Bootstrap or high side floating power supply. A good quality bypassing capacitor
is required from this pin to VS and should be placed close to the pins for best
results.
The under voltage lockout (UVLO) circuit enables the device to operate at power
on when a typical supply voltage higher than VUVLO2−OUT−ON is present. Please
see Figure 5 for more details. A filter time tUVF2 helps to suppress noise on VB
pin.
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NCD57200
Table 2. ABSOLUTE MAXIMUM RATINGS (Note 1) Over operating free−air temperature range unless otherwise noted
Symbol
Minimum
Maximum
Unit
High−Side Offset Voltage (see Figure 2)
VS
−900
900
V
High−Side Supply Voltage (see Figure 2)
VB
−900
900
V
Low−Side Supply Voltage
VDD
−0.3
25
V
High−Side Floating Supply Voltage
VBS
−0.3
25
V
High−Side Output Voltage (HO) (see Figure 2)
VHO
VS−0.3
VBS+0.3
V
Low−Side Output Voltage (LO)
VLO
−0.3
VDD+0.3
V
Logic Input Voltage (HIN, LIN)
VIN
−0.3
VDD+0.3
V
±100
V/ns
Parameter
Allowable Offset Voltage Slew Rate (see Figure 32)
dVS/dt
Maximum Junction Temperature
Storage Temperature Range
TJ(max)
−40
150
°C
TSTG
−65
150
°C
ESD Capability, Human Body Model (Note 2)
ESDHBM
±4
kV
ESD Capability, Charged Device Model (Note 2)
ESDCDM
±2
kV
Moisture Sensitivity Level
MSL
1
−
Lead Temperature Soldering Reflow
TSLD
260
°C
(SMD Styles Only), Pb−Free Versions (Note 3)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114).
ESD Charged Device Model tested per AEC−Q100−011 (EIA/JESD22−C101).
Latchup Current Maximum Rating: ≤ 100 mA per JEDEC standard: JESD78, 125°C.
3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
Table 3. THERMAL CHARACTERISTICS
Parameter
Symbol
Value
Unit
Thermal Characteristics, SOIC−8 (Note 4)
Thermal Resistance, Junction−to−Air (Note 5)
RqJA
167
°C/W
4. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
5. Values based on copper area of 100 mm2 (or 0.16 in2) of 1 oz copper thickness and FR4 PCB substrate.
Table 4. RECOMMENDED OPERATING RANGES (Note 6)
Parameter
Symbol
Min
Max
Unit
High−Side Floating Supply Voltage
VBS
VS+UVLO2
VS+20
V
High−Side Offset Voltage (see Figure 2)
VS
−800
800
V
High−Side Output Voltage (HO) (see Figure 2)
VHO
VS
VBS
V
Low−Side Output Voltage (LO)
VLO
GND
VDD
V
Logic Input Voltage (HIN, LIN)
VIN
GND
VDD
V
Low−Side Supply Voltage
VDD
UVLO1
20
V
TA
−40
+125
°C
Ambient Temperature
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
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NCD57200
Table 5. ELECTRICAL CHARACTERISTICS VDD = VBS = 15 V.
For typical values TA = 25°C, for min/max values, TA is the operating ambient temperature range that applies, unless otherwise noted.
Test Conditions
Symbol
Min
Typ
Max
Unit
VBS Supply Under Voltage
Output Enabled
VUVLO2−OUT
11
11.5
12
V
VBS Supply Under Voltage
Output Disabled
VUVLO2−OUT
10
10.5
11
V
VBS Supply Voltage Output
Enabled/Disabled Hysteresis
VUVLO2−HYST
0.5
1.0
1.2
V
VDD Supply Under Voltage
Output Enabled
VUVLO1−OUT
12
12.5
13
V
VDD Supply Under Voltage
Output Disabled
VUVLO1−OUT
11
11.5
12
V
VDD Supply Voltage Output
Enabled/Disabled Hysteresis
VUVLO1−HYST
0.5
1.0
1.2
V
IHV_LEAK1
IHV_LEAK2
20
200
600
nA
Parameter
VOLTAGE SUPPLY
−ON
−OFF
−ON
−OFF
Leakage Current Between VS and
GND
VS = ± 800 V, TA = 25°C
VS = ± 800 V, TA = −40°C to 125°C
Quiescent Current VBS Supply
(VB Only)
HO = Low
IQBS1
260
325
mA
Quiescent Current VBS Supply
(VB Only)
HO = High
IQBS2
330
440
mA
Quiescent Current VDD Supply
(VDD Only)
VLIN = Float, VHIN = 0 V,
IQDD1
380
440
mA
Quiescent Current VDD Supply
(VDD Only)
VLIN = 3.3 V, VHIN = 0 V,
IQDD2
440
500
mA
Quiescent Current VDD Supply
(VDD Only)
VLIN = 0 V, VHIN = 3.3 V,
IQDD3
2.4
3
mA
0.9
V
LOGIC INPUT
Low Level Input Voltage
VIL
High Level Input Voltage
VIH
2.4
V
Logic “1” Input Bias Current
VLIN = 3.3 V, VHIN = 3.3 V
ILIN1+, IHIN1+
25
50
mA
Logic “1” Input Bias Current
VLIN = 20 V, VHIN = 20 V,
VDD = VBS = 20 V
ILIN2+, IHIN2+
100
150
mA
Logic “0” Input Bias Current
VLIN = 0 V, VHIN = 0 V
ILIN−, IHIN−
40
100
nA
ISINK = 200 mA, TA = 25°C
VOL1
0.2
0.3
V
ISINK = 200 mA,
TA = −40°C to 125°C
VOL2
ISOURCE = 200 mA, TA = 25°C
VOH1
14.4
ISOURCE = 200 mA,
TA = −40°C to 125°C
VOH2
14
DRIVER OUTPUT
Output Low State
Output High State
0.5
14.5
V
A
Peak Driver Current, Sink
(Note 7)
VHO = VLO = 15 V
IPK−SNK1
2.3
VHO = VLO = 9 V
(near Miller Plateau)
IPK−SNK2
2.1
Peak Driver Current, Source
(Note 7)
VHO = VLO = 0 V
IPK−SRC1
1.9
VHO = VLO = 9 V
(near Miller Plateau)
IPK−SRC2
1.5
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A
NCD57200
Table 5. ELECTRICAL CHARACTERISTICS VDD = VBS = 15 V.
For typical values TA = 25°C, for min/max values, TA is the operating ambient temperature range that applies, unless otherwise noted.
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
0.8
1.3
V
IGBT SHORT CIRCUIT CLAMPING
Clamping Voltage
(VHO – VB) / (VLO – VDD)
IHO = 100 mA, ILO = 100 mA
(pulse test, tCLPmax = 10 ms)
VCLAMP−OUT
DYNAMIC CHARACTERISTIC
HO High Propagation Delay
CLOAD = 1 nF, VIH to 10% of Output
Change for PW > 150 ns
tPD−ON−H
50
90
110
ns
HO Low Propagation Delay
CLOAD = 1 nF, VIL to 90% of Output
Change for PW > 150 ns
tPD−OFF−H
50
90
110
ns
Propagation Delay Distortion(HS)
(= tPD−ON−H − tPD−OFF−H)
PW >150 ns
tDISTORT−H
−25
0
25
ns
LO High Propagation Delay
CLOAD = 1 nF, VIH to 10% of Output
Change for PW > 150 ns
tPD−ON−L
50
90
110
ns
LO Low Propagation Delay
CLOAD = 1 nF, VIL to 90% of Output
Change for PW > 150 ns
tPD−OFF−L
50
90
110
ns
Propagation Delay Distortion(LS)
(= tPD−ON−L − tPD−OFF−L)
PW >150 ns
tDISTORT−L
−25
0
25
ns
High Propagation Delay Distortion
between High and Low Sides
PW > 150 ns
tDISTORT−HL−H
−25
0
25
ns
Low Propagation Delay Distortion
between High and Low Sides
PW > 150 ns
tDISTORT−HL−L
−25
0
25
ns
Rise Time (HO) (see Figure 3)
CLOAD = 1 nF,
10% to 90% of Output Change
tRISE−H
13
ns
Fall Time (HO) (see Figure 3)
CLOAD = 1 nF,
90% to 10% of Output Change
tFALL−H
8
ns
Rise Time (LO) (see Figure 3)
CLOAD = 1 nF,
10% to 90% of Output Change
tRISE−L
13
ns
Fall Time (LO) (see Figure 3)
CLOAD = 1 nF,
90% to 10% of Output Change
tFALL−L
8
ns
Deadtime, HO Delays (see Figure 6)
VLIN/HIN = 0 V and 3.3 V
tDT1
340
ns
Deadtime, LO Delays (see Figure 6)
VLIN/HIN = 0 V and 3.3 V
tDT2
350
ns
Deadtime Matching
Minimum Pulse Width Filtering Time
(see Figure 3)
tMDT
tMIN1, tMIN2
TA = 25°C
10
10
ns
40
ns
UVLO Fall Delay (HO and LO)
tUVF1, tUVF2
1300
ns
UVLO Rise Delay (HO and LO)
tUVR1, tUVR2
1100
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Values based on design and/or characterization.
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NCD57200
VIH
VIL
HIN/LIN
tRISE−X
tMIN2
tFALL−X
90%
tPD−ON−X
tMIN1
tPD−OFF−X
HO/LO
10%
Figure 3. Propagation Delay, Rise and Fall Time
VDD
HIN
LIN
Clamping
Circuit
Figure 4. Input Pin Structure
HIN/LIN
VUVLOx−OUT−ON
VUVLOx−OUT−OFF
VDD/VBS
tUVFX
tUVRX
VUVLOx−OUT−ON
VUVLOx−OUT−OFF
HO/LO
Figure 5. UVLO
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NCD57200
Figure 6. Deadtime, Interlock and Output Minimum Pulse Width
HIN
tMIN1
tMIN2
tDT1
tDT2
tMIN1
LIN
tMIN2
Figure 7. Input Circuit
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NCD57200
TYPICAL CHARACTERISTICS
0.45
0.45
0.4
0.35
IDD [mA]
0.5
IDD [mA]
0.5
(2)
−20
0
20
40
60
Temperature [°C]
80
100
(2)
(1)
0.35
(1)
0.3
−40
0.4
0.3
−40
120 125
−20
0
20
40
60
Temperature [°C]
80
100
120 125
(1) VDD = 20 V, VBS = 15 V, LIN = FLOAT, HIN = LOW
(2) VDD = 20 V, VBS = 15 V, LIN = 3.3 V, HIN = LOW
(1) VDD = 15 V, VBS = 15 V, LIN = FLOAT, HIN = LOW
(2) VDD = 15 V, VBS = 15 V, LIN = 3.3 V, HIN = LOW
Figure 8. IDD Supply Current VDD = 15 V
Figure 9. IDD Supply Current VDD = 20 V
0.5
8
7
(3)
6
0.45
IDD [mA]
IDD [mA]
5
0.4
(3)
(2)
0.35 (1)
4
3
2 (2)
1
0.3
−40
−20
0
20
40
60
Temperature [°C]
80
100
0
120 125
(1)
−40
−20
(1) VDD = 15 V, VBS = 15 V, LIN = FLOAT, HIN = LOW
(2) VDD = 20 V, VBS = 15 V, LIN = FLOAT, HIN = LOW
(3) VDD = 25 V, VBS = 15 V, LIN = FLOAT, HIN = LOW
1
2
0.9
1.8
0.8
1.6
0.2
IBS [mA]
IBS [mA]
100
120 125
Figure 11. IDD Supply Current VDD = 15–25 V,
LIN = HIN = 20 kHz / 50%
(3)
1.2
0.5
0.3
80
1.4
(3)
0.6
0.4
20
40
60
Temperature [°C]
(1) VDD = 15 V, VBS = 15 V, LIN = HIN = 20 kHz / 50%
(2) VDD = 20 V, VBS = 15 V, LIN = HIN = 20 kHz / 50%
(3) VDD = 25 V, VBS = 15 V, LIN = HIN = 20 kHz / 50%
Figure 10. IDD Supply Current VDD = 15–25 V, Input Float
0.7
0
(2)
0.8
0.6
(1)
0.1
0
−40
1
−20
0
20
40
60
Temperature [°C]
80
100
120 125
0.4
(2)
0.2
(1)
0
−40
(1) VDD = 15 V, VBS = 15 V, LIN = LOW, HIN = LOW
(2) VDD = 15 V, VBS = 15 V, LIN = LOW, HIN = 3.3V
(3) VDD = 15 V, VBS = 15 V, LIN = LOW, HIN = 50%
−20
0
20
40
60
Temperature [°C]
80
100
120 125
(1) VDD = 15 V, VBS = 25 V, LIN = LOW, HIN = LOW
(2) VDD = 15 V, VBS = 25 V, LIN = LOW, HIN = 3.3 V
(3) VDD = 15 V, VBS = 25 V, LIN = LOW, HIN = 20 kHz / 50%
Figure 12. IBS Supply Current VBS = 15 V
Figure 13. IBS Supply Current VBS = 25 V
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NCD57200
TYPICAL CHARACTERISTICS (continued)
2
1.6
2.2
(3)
2
Input Voltage Level [V]
1.8
IBS [mA]
1.4
1.2 (2)
1
0.8
0.6
(1)
0.4
(1)
1.8
1.6
1.4
1.2
0.2
0
−40
−20
(4)
1
−40
0
20
40
60
80
100 120 125
Temperature [°C]
(1) VDD = 15 V, VBS = 15 V, LIN = LOW, HIN = 50%
(2) VDD = 15 V, VBS = 20 V, LIN = LOW, HIN = 50%
(3) VDD = 15 V, VBS = 25 V, LIN = LOW, HIN = 50%
−20
0
20
40
60
80
100 120 125
Temperature [°C]
(1) VIH, LIN = HIGH
(2) VIH, HIN = HIGH
(4) VIL, HIN = LOW
(3) VIL, LIN = LOW
Figure 15. Input Voltage Level
13
12.5 (1)
1.1
12
Voltage [V]
1
Voltage [V]
(3)
Figure 14. IBS Supply Current VBS = 15–25 V,
HIN = 20 kHz / 50%
1.2
0.9
0.8
(2)
11.5
(3)
11
(2)
0.7 (1)
0.6
−40
(2)
10.5
−20
0
20
40
60
80
100
(4)
10
−40
120 125
−20
0
Temperature [°C]
20
40
60
80
100
120 125
Temperature [°C]
(1) VUVLO1−HYST
(2) VUVLO2−HYST
(1) VUVLO1−OUT−ON
(2) VUVLO1−OUT−OFF
Figure 16. UVLO Hysteresis
(3) VUVLO2−OUT−ON
(4) VUVLO2−OUT−OFF
Figure 17. UVLO Threshold Voltage
28
105
Input Current [mA]
Input Current [mA]
27
26
25
100
95
(2)
(2)
(1)
(1)
24
−40
−20
0
20
40
60
80
100
120 125
90
−40
Temperature [°C]
−20
0
20
40
60
80
100
120 125
Temperature [°C]
(1) ILIN1+, LIN = 3.3 V, VDD = VBS = 15V
(2) IHIN1+, HIN = 3.3 V, VDD = VBS = 15V
(1) ILIN2+, LIN = 20 V, VDD = VBS = 20 V
(2) IHIN2+, HIN = 20 V, VDD = VBS = 20 V
Figure 18. Input Current VDD = VBS = 15 V
Figure 19. Input Current VDD = VBS = 20 V
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NCD57200
TYPICAL CHARACTERISTICS (continued)
1
100
95
(2)
0.9
Time [ns]
Voltage [V]
(1)
90 (4)
(2)
0.8
85
(1)
0.7
−40
−20
0
20
40
60
Temperature [°C]
(1) VHO−VBS
80
100
120 125
(3)
80
−40 −20
(2) VLO−VDD
0
20
40
60
Temperature [°C]
80
100
120 125
(1) tPD−ON−H VBS = 15 V
(3) tPD−ON−H VBS = 20 V
(2) tPD−OFF−H VBS = 15 V
(4) tPD−OFF−H VBS = 20 V
Figure 20. IGBT Short Circuit CLAMP Voltage Drop
Figure 21. HO Propagation Delay
24
100
22
20
Time [ns]
Time [ns]
95
90
(2) (4)
(3)
16 (1)
14
(4)
12
85
(1) (3)
80
−50
18
(2)
10
8
−25
0
25
50
75
100
125
−40
−20
0
40
(1) tRISE−H VBS = 15 V
(3) tPD−ON−L VDD = 20 V
(4) tPD−OFF−L VDD = 20 V
(1) tPD−ON−L VDD = 15 V
(2) tPD−OFF−L VDD = 15 V
20
60
80
100
120 125
Temperature [°C]
Temperature [°C]
(2) tFALL−H VBS = 15 V
(3) tRISE−H VBS = 20 V
(4) tFALL−H VBS = 20 V
Figure 23. HO Rise – Fall Time
Figure 22. LO Propagation Delay
18
380
17
370
15
Deadtime [ns]
Time [ns]
16
(1) (3)
14
13
360
350
(2) (4)
12
(2)
(1)
340
11
10
−50
−25
0
25
50
75
100
125
330
−40
Temperature [°C]
(1) tRISE−L VDD = 15 V
(2) tFALL−L VDD = 15 V
−20
0
20
40
60
Temperature [°C]
80
100
(1) tDTX VDD = 15 V, VBS = 15 V
(2) tDTX VDD = 20 V, VBS = 20 V
(3) tRISE−L VDD = 20 V
(4) tFALL−L VDD = 20 V
Figure 24. LO Rise – Fall Time
Figure 25. Deadtime
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11
120 125
NCD57200
TYPICAL CHARACTERISTICS (continued)
24
(4)
23
22.5
22
21.5
(4)
25
(3)
Minimum Pulse Width [ns]
Minimum Pulse Width [ns]
23.5
26
(3)
24
23
22
(1)
21
(2)
20
(1)
(2)
21
−40 −20
0
20
40
60
80
100
120 125
19
−40
−20
0
20
(1) tMIN1−L VDD = 15 V
(3) tMIN2−L VDD = 15 V
(2) tMIN1−L VDD = 20 V
(4) tMIN2−L VDD = 20 V
20
(4)
100
120 125
(3) tMIN2−H VBS = 15 V
(4) tMIN2−H VBS = 20 V
(2)
(1)
16
Supply Current IDD / IB [mA]
(1)
UVLO DELAY [ms]
(3)
18
1.7
(2)
1.6
(3)
1.4
1.3
1.2
−40
80
Figure 27. Minimum Pulse Width Filtering
Time (HO)
1.8
1.5
60
(1) tMIN1−H VBS = 15 V
(2) tMIN1−H VBS = 20 V
Figure 26. Minimum Pulse Width Filtering
Time (LO)
1.9
40
Temperature [°C]
Temperature [°C]
14
12
10
8
6
4
2
0
−20
0
20
40
60
80
100
120 125
1
10
(1) tUVF1
(3) tUVF2
100
1000
Frequency [kHz]
Temperature [°C]
(1) CG = 1 nF
(3) CG = 100 nF
(2) tUVR1
(4) tUVR2
Figure 28. UVLO Delay
(2) CG = 10 nF
Figure 29. Power Supply Current vs. Switching
Frequency (Duty Cycle 50%)
www.onsemi.com
12
NCD57200
Under Voltage Lockout (UVLO)
For reliable high output current suitable external power
capacitors are required. Parallel combination of 100 nF +
4.7 mF ceramic capacitors is optimal for a wide range of
applications using IGBT. For reliable driving of IGBT
modules (containing several parallel IGBTs) a higher
capacitance is required (typically 100 nF + 10 mF).
Capacitors should be as close as possible to the driver’s
power pins.
Power supply of isolated (HO) channel can be provided by
an external DC power supply or Bootstrap circuit.
UVLO ensures correct switching of IGBT connected to
the driver output.
• The IGBT is turned−off, if the supply VDD drops below
VUVLO1−OUT−OFF or VBS drops below
VUVLO2−OUT−OFF
• The driver output does not start to react to the input
signal on HIN or LIN until the VDD or VBS rises above
the VUVLOX−OUT−ON
Power Supply (VDD, VBS)
NCD57200 is designed to support unipolar power supply
on both individual channels.
VDD
+
100 n
−
10 mF
VDD
VB
HIN
HO
LIN
VS
GND
LO
10 mF
100 n
+
VBS
−
Figure 30. Unipolar Power Supply
+
−
VDD
100 n
10 mF
VDD
VB
HIN
HO
LIN
VS
GND
LO
10 mF
100 n
RGH
RGL
Figure 31. Bootstrap Power Supply
WARNING: When the application uses an independent or
separate power supply for the control unit on
the input side of the driver, all inputs should
be protected by a serial resistor (In case of
a power failure of the driver, the driver may
be damaged due to overloading of the input
protection circuits).
Signal Inputs (HIN, LIN)
Inputs of NCD57200 are active high. Outputs are in phase
with inputs signals respecting internal logic (see Figure 5, 6,
7).
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13
NCD57200
Common Mode Transient Immunity (CMTI)
10 mF
15 V
+
−
+
VDD
VB
S1
−
HIN
HO
LIN
VS
GND
LO
HO must remain stable
15 V
10 mF
+
−
HV PULSE
FLOATING
Figure 32. CMTI Test Setup
(Test Conditions: HV PULSE = ±900 V, dV/dt = 1−100 V/ns, VDD = 15 V, VB = 15 V)
NOTE:
Purple − recommended isolation gap.
Figure 33. Recommended Layout
10 mils
0.25 mm
10 mils
0.25 mm
High-speed signals
Ground plane
40 mils
1 mm
Keep this space free
10 mils
from traces, pads and
0.25 mm
vias
10 mils
0.25 mm
40 mils
1 mm
10 mils
0.25 mm
Power plane
Low-speed signals
157 mils
(4 mm)
Figure 34. Recommended Layer Stack
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14
NCD57200
ORDERING INFORMATION
Device
Package
Shipping†
NCD57200DR2G
SOIC−8 (Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
15
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
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Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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