12-Bit Low Power SAR ADC
NCD98010, NCD98011
The NCD98010 (unsigned output) and the NCD98011 (signed
output) ADC products provide an extremely low power solution for
analog to digital conversion applications using a capacitor−based
successive−approximation architecture. Optimized for low power and
speed, the NCD98010/1 can achieve a sample rate of 2 MSPS while
consuming less than 1 mW of power. The device also features a large
input voltage range of 1.65 V to 3.3 V for various applications for both
analog and digital supplies. The SPI−compatible interface provides a
straight−forward data−acquisition method.
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MARKING
DIAGRAMS
Features
•
•
•
•
•
•
•
Nanowatt Power Consumption
Fully Differential Input
2−MSPS Throughput
Small Package Size
Pre−Calibrated
SPI Interface
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
•
•
•
•
•
•
•
•
VINP
VINN
US8 (SSOP8)
MX SUFFIX
CASE 493
XXM
XX
M
= Specific Device Code
= Date Code
VINN
CSN
1
OUT
2
CLK
3
8
4
7
VINP
6
VCC
5
GND
VDD
X2QFN8 (Top View)
VDD
+
Switched
Capacitive
DAC
XXM
PIN CONFIGURATION
Low−Power Data Acquisition
Battery−powered Equipment
Level Sensors
Ultrasonic Flow Meters
Motor Controls
Wearable Fitness
Portable Medical Equipment
Glucose Meters
VCC
X2QFN8
DP SUFFIX
CASE 722AM
CSN
VDD 1
8 GND
CLK 2
7 VCC
OUT 3
6 VINP
CSN 4
5 VINN
US8 (Top View)
Comparator
Serial
Interface
CLK
ORDERING INFORMATION
Device
Successive Approximation Register
OUT
Digital Control
NCD98010XMXTAG
NCD98011XMXTAG
NCD98010XDPT3G*
GND
NCD98011XDPT3G*
Figure 1. Block Diagram
Package
X2QFN
Shipping†
5000 / Tape &
Reel
SSOP8
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
* These products are currently under development.
Please contact Sales regarding their availability.
© Semiconductor Components Industries, LLC, 2020
October, 2020 − Rev. 2
1
Publication Order Number:
NCD9801/D
NCD98010, NCD98011
PIN DESCRIPTION
X2QFN
Pin No.
SSOP
Pin No.
Name
1
4
CSN
Chip select (active low)
2
3
OUT
Data Output (serialized)
3
2
CLK
Clock
4
1
VDD
Digital I/O supply voltage
5
8
GND
Common ground for all pins
6
7
VCC
Analog supply and ADC reference voltage
7
6
VINP
Analog input, positive signal
8
5
VINN
Analog input, negative signal
Function
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Supply Voltage Range
VCC
−0.3 to 3.63
V
Supply Voltage Range
VDD
−0.3 to 3.63
V
Input Voltage Range
VINP
−0.3 to 3.63
V
Input Voltage Range
VINN
−0.3 to 3.63
V
Output Voltage Range
VOUT
−0.3 to 3.63
V
CSN Input Voltage Range
VEN
−0.3 to 3.63
V
Storage Temperature Range
TSTG
−40 to 150
°C
Lead Temperature, Soldering (10 sec.)
TSLD
260
°C
ESD Capability, Human Body Model (Note 1)
ESDHBM
2.0
kV
ESD Capability, Charged Device Model (Note 1)
ESDCDM
500
V
LU
100
mA
Latch−up Current Immunity (Note 1)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Tested by the following methods @ TA = 25°C:
ESD Human Body Model tested per JESD22−A114
ESD Charged Device Model per ESD STM5.3.1
Latch−up Current tested per JESD78.
RECOMMENDED OPERATING CONDITIONS
Rating
Symbol
Min
Max
Unit
Analog Supply Voltage
VCC
1.65
3.6
V
Digital I/O Supply Voltage
VDD
1.65
3.6
V
Ground
GND
0
V
Ambient Temperature
TA
−40
120
°C
Junction Temperature
TJ
−40
125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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2
NCD98010, NCD98011
ELECTRICAL CHARACTERISTICS (TJ = 25°C, VCC = 3 V, unless otherwise noted)
Parameter
Conditions
Symbol
Min
Typ
Max
Unit
VCC
1.65
3
3.6
V
VDD
1.65
POWER SUPPLY REQUIREMENTS
Analog Supply and ADC reference
Digital I/O Supply
2 MSPS for VCC = 3.6 V
Analog Supply Current
Analog Power Dissipation
Digital Supply Current
Dependent on SDO loading
(tested with ~7 pF)
1 MSPS for VCC = 3 V
V
mA
7.6
1 MSPS for VCC = 1.8 V
30
2 MSPS for VCC = 3.6 V
300
1 MSPS for VCC = 3 V
150
PVCC
100 kSPS for VCC = 3.6 V
15
mA
20
mA
mA
540
mW
mW
72
mW
1 MSPS for VCC = 1.8 V
54
mW
2 MSPS for VDD = 3.6 V
852
mA
425
mA
45
mA
136
mA
1 MSPS for VDD = 3 V
IVDD
100 kSPS for VDD = 3.6 V
1 MSPS for VDD = 1.8 V
Standby current (CSN high)
(Note 2)
3.6
150
50
IVCC
100 kSPS for VCC = 3.6 V
3
100
VCC = 3.6 V
ISTNDBY
3.9
6
mA
−VCC
VCC
Vppd
−0.2
VCC + 0.1
V
ANALOG INPUT
Full−Scale Voltage Span
Absolute Voltage Range
Sampling Capacitance
Common Mode Voltage=VCC/2
Vfs
Vinp to GND
Vinn to GND
−0.2
Measured with 1kHz, 1V Stimuli
CS
VCC + 0.1
V
2
pF
12
Bits
SYSTEM PERFORMANCE
Resolution
Integral Nonlinearity (Note 3)
Differential Nonlinearity (Note 3)
Offset Error
Effective Number of bits
VCC = 1.8 V
INL
VCC = 3.3 V
VCC = 1.8 V
DNL
VCC = 3.3 V
VCC = 1.8 V
EO
VCC = 3.3 V
VCC = 1.8 V
0
2
−2
0
2
−1
0
1.5
−1
0
1.5
0
−10
VCC = 3.3 V
EG
VCC = 3.3 V
Gain error drift with temperature
Missing Codes
10
LSB
LSB
11.2
dVOS/dT
VCC = 1.8 V
0
LSB
10
ENOB
Offset error drift with temperature
Gain Error
−2
0.02
−0.6
0.3
ppm/°C
0.6
0.3
%FS
0.0006
%FS/°C
0
Codes
SAMPLING DYNAMICS
Acquisition Time
62.5
Maximum throughput rate
2
ns
MSPS
DYNAMIC CHARACTERISTICS
Signal−to−Noise Ratio
fIN = 1 kHz VCC = 3.3 V
SNR
fIN = 1 kHz VCC = 1.8 V
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3
70
65
dB
NCD98010, NCD98011
ELECTRICAL CHARACTERISTICS (TJ = 25°C, VCC = 3 V, unless otherwise noted)
Parameter
Conditions
Symbol
Min
Typ
Max
Unit
DYNAMIC CHARACTERISTICS
Total−Harmonic Distortion
fIN = 1 kHz VCC = 3.3 V
fIN = 1 kHz VCC = 1.8 V
Signal−to−Noise and Distortion
(Note 4)
fIN = 1 kHz VCC = 3.3 V
Spurious−Free Dynamic Range
(Note 4)
fIN = 1 kHz VCC = 3.3 V
−80
THD
SINAD
fIN = 1 kHz VCC = 1.8 V
SFDR
fIN = 1 kHz VCC = 1.8 V
dB
−80
68
69
dB
62
69
80
dB
74
DIGITAL INPUT/OUTPUT
High−Level Input Voltage
VIH
Low−Level Input Voltage
VIL
High−Level Output Voltage
2 mA drive
VOH
Low−Level Output Voltage
2 mA drive
VOL
VDD*0.7
V
VDD*0.3
VDD − 0.5 V
V
V
GND+0.5
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Standby current includes both digital and analog currents.
3. INL and DNL parameters were verified via bench testing and are not used for production screening.
4. SINAD and SFDR are tested at production and guaranteed by correlation to bench test results.
TIMING CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Conditions
Symbol
Min
Typ
Max
Unit
2
MSPS
TIMING SPECIFICATIONS
Throughput
fTHROUGH
Cycle Time
fCYCLE
0.5
ms
Conversion Time
fCONV
437.5
ns
Data Delay
1
cycle
TIMING REQUIREMENTS
Acquisition Time (CSN high)
tACQ
CLK Frequency
fCLK
32
MHz
CLK Period
tCLK
31.25
ns
CSN Falling to
1st
SCLK falling edge
Last SCLK falling edge to CSN rising
Falling SCLK to SDO valid (Note 5)
Assumed 10 pF Load
62.5
tCSN_SCLK
15.75
tSCLK_CSN
15.75
tSDO_VALID
ns
ns
ns
30
ns
5. When SCLK is running at higher frequencies, the tSDO_VALID of 30 ns requires SDO to be sampled on the falling edge of SCLK at the end
of the bit width just before SDO changes to the next output. This will ensure acquisition of the correct data. For example, location A shown
below would be the best place to sample SDO for the acquisition of bit 9.
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4
NCD98010, NCD98011
tCYCLE
Sample: N
A
tSCLK
D11
D10
Sample: N+1
tSCLK_CSN
tCSN_SCLK
CSN
SCLK
OUT
tAQU
tCONV
D9
D8
D7
D6
D5
D4
D3
D2
tSDO_VALID
Data: N-1
Figure 2. Serial Interface Timing
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5
D1
D0
NCD98010, NCD98011
TYPICAL CHARACTERISTICS
95
76
74
73
SNR (dB)
SNR (dB)
85
80
75
0
5
10
15
20
25
30
35
−40
−20
0
20
40
80
60
TEMPERATURE (°C)
Figure 3. SNR vs. SCLK Frequency
Figure 4. SNR vs. Temperature
100
12.0
11.8
11.6
85
11.4
ENOB (bits)
SNDR (dB)
SNDR
SCLK FREQUENCY (MHz)
90
80
75
11.2
11.0
10.8
10.6
70
10.4
65
10.2
0
5
10
15
20
25
30
10.0
35
0
5
10
15
20
25
30
SCLK FREQUENCY (MHz)
SCLK FREQUENCY (MHz)
Figure 5. SNDR vs. SCLK Frequency
Figure 6. ENOB vs. SCLK Frequency
95
45
90
40
35
DVDD = 3.3 V
35
CURRENT (mA)
85
THD (dB)
70
67
66
−60
95
80
75
70
30
25
DVDD = 1.8 V
20
15
10
65
60
SNR
71
68
65
60
72
69
70
60
THD
75
90
5
0
5
10
15
20
25
30
0
−60
35
−40
−20
0
20
40
60
80
SCLK FREQUENCY (MHz)
TEMPERATURE (°C)
Figure 7. THD vs. SCLK Frequency
Figure 8. DVDD Current vs. Temperature
(SCLK = 2 kHz)
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6
100
NCD98010, NCD98011
TYPICAL CHARACTERISTICS
10
400
9
CURRENT (mA)
350
CURRENT DRAW (mA)
450
DVDD
300
250
200
150
AVDD
100
50
0
7
6
5
4
2
1
0
5
10
15
20
25
30
0
−60
35
−20
0
20
40
60
80
TEMPERATURE (°C)
Figure 9. Current vs. SCLK Frequency
Figure 10. AVDD Current vs. Frequency
20
15
10
5
1.5
−40
SCLK (MHz)
25
SDO DELAY (ns)
AVDD = 1.8 V
3
30
0
AVDD = 3.3 V
8
2.0
2.5
3.0
3.5
DVDD (V)
Figure 11. SDO Delay from Falling Edge of
SCLK
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7
100
NCD98010, NCD98011
ADC Digital
Output Codes
TERMINOLOGY
Understanding how ADC metrics affect application
performance is key to obtaining desired performance. Key
terminology are defined below and should be used when
determining overall system performance when using the
NDC98010/1.
Offset and Gain Error
(2 n−1)
V inputRange
Negative
Offset Error
(eq. 1)
ADC Analog
Input (V)
Figure 13. Offset Error Example
V CM
Any deviation from an offset of 0 and the ideal gain is
considered error. Although these errors can be calibrated
out, any initial gain error reduces the ADCs dynamic range.
The plots below shows examples of these errors. Calibrating
these errors out would be achieved by adding / subtracting
codes to get the digitized output to 0 when the inputs are
shorted together at VCM. After the offset (for signed output
format) has been calibrated, samples can be taken at both
polarities to determine the gain error. The output can be
multiplied by a scale factor (after the offset has been
adjusted) to compensate for the gain error.
ADC Digital
Output Codes
Ideal ADC
0
Offset and gain, if characterized, can be calibrated out post
digitization. An ideal ADC has a linear transfer function
following the equation y = m*x + b, where m is the gain and
b is the offset. Ideally the offset would be 0, and the gain
would be
m+
Positive Offset
Error
SNR = (6.02N + 1.76) dB, where N is the number of bits.
A 12 bit converter has a theoretical SNR of 74 dB.
SINAD (or SNDR)
SINAD is the signal to noise and distortion ratio. SINAD
is the ratio of the RMS signal amplitude to the mean value
of the root sum square (RSS) of all other spectral
components, including harmonics, but excluding DC.
SINAD is useful because it provides a metric for the ADCs
overall dynamic performance, as it includes all components
which make up noise and distortion.
Positive Gain
Error
SFDR
SFDR is the Spurious Free Dynamic Range. SFDR is the
ratio of the RMS value of the signal to the RMS value of the
highest magnitude spurious signal regardless of where it
falls in the frequency spectrum. The highest spur might not
be a harmonic, though it typically is.
0
Ideal ADC
THD
THD is the total harmonic distortion, defined as ratio of
the RMS of the primary signal and the mean of the root sum
squared of all the harmonics. Generally only the first 5
harmonics are considered. The figure below shows an
example of these AC metrics in the frequency domain.
Negative Gain
Error
VCM
ȡǸH 22 ) H 23 ) H 24 ) H 25ȣ
THD + 20 logȧ
ȧ
H
Ȣ
Ȥ
ADC Analog
Input (V)
1
Figure 12. Gain Error Example
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8
(eq. 2)
NCD98010, NCD98011
ADC TRANSFER FUNCTION
ADC Full Scale
The NCD98010/1 offers a full input range of 0 V to VCC.
The format of the digital output is offered in an unsigned
format (NCD98010) and a signed format (NCD98011). The
output code resulting from VINN and VINP tied together and
held at VCC/2 is therefore 0h000 for the NCD98011 and
0h100 for the NCD98010. This distinction is shown below
in Figures 16 and 17.
ADC Input (Sinusiod)
SNR: RMS of Signal to RMS
of noise floor
SFDR (dBc)
dB
SINAD: RMS of Signal to RMS
of noise + Harmonics
SFDR: Signal to largest nonfundamental content
Harmonics
Noise Floor
NCD98010
Unsigned Output Format
THD: RMS of Signal to mean
value of RSS of its harmonics
111111111111
111111111110
111111111101
111111111100
..
.
fSAMPLE/2
Frequency
Figure 14. Spurious Free Dynamic Range in the
Frequency Domain
100000000001
100000000000
011111111111
011111111110
..
.
ENOB
The effective number of bits describes the dynamic range
of the ADC. It quantifies the actual resolution of the ADC
taking into account noise and distortion. ENOB typically
changes over ADC input frequency, and is an important
metric for non−DC applications. It is defined as:
ENOB + SINAD * 1.76
6.02
000000000100
000000000010
000000000001
000000000000
(eq. 3)
−Full Scale
THEORY OF OPERATION
The NCD98010/1 uses a successive approximation
architecture. Conversion from an analog signal to a digital
signal occurs in 2 different stages over 16 clock cycles. The
first stage is a differential sample and hold operation, where
the input Vinn and Vinp voltages are sampled onto a
differential charge re−distribution capacitive array. The
second stage implements a binary decision tree, bit cycling
through 1/2N divisions of the reference. The internal digital
control block steps through each of 12 bits to determine
whether that bit in the digital output code is higher or lower
than the sampled signal. VCC acts as the analog supply and
the ADC reference. This allows for a maximum input range
of 0 V to VCC.
ADC
Operation
Sample/Hold
0 LSB
Full Scale
VINP − VINN
Figure 16. NCD98010 Unsigned Output Definition
NCD98011
Signed Output Format
011111111111
011111111110
011111111101
011111111100
..
.
000000000010
000000000001
000000000000
111111111111
111111111110
..
.
100000000011
100000000010
100000000001
100000000000
Bit Cycling for Current Sample and Data Transmission for Previous Sample
SCLK
CSN
−Full Scale
Must be high for at least
2 clock cycles
0 LSB
VINP − VINN
Full Scale
Figure 17. NCD98011 Signed Output Definition
Figure 15. SAR ADC Internal Operation
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9
NCD98010, NCD98011
APPLICATION INFORMATION
The NCD98010/1 supports many application due to its small size and low power. The typical connection diagram for the
NCD98010/1 maximizing performance is shown below in Figure 18.
Input Buffer
Anti-Aliasing Filter
VCC
RCM
VCM
-
1μF
1μF
10kΩ
+
VDD
CCM
VCC
VDD
INP
CSN
CDIFF
RCM
OUT
SCLK
INN
GND
CCM
10kΩ
NCD98010
1μF
MCU / GPU or FPGA
VCC
1μF
NCS20032
Differential Analog Input
10kΩ
10kΩ
Figure 18. NCD Connection Diagram
Buffering
The common mode filter cutoff frequency should be no
greater than the Nyquist frequency (FSAMPLE / 2). Set the
differential cutoff frequency to be one decade less than the
common−mode cutoff frequency by increasing the
differential capacitor (CDIFF) by a factor of 10 over CCM.
This will help to reduce errors caused by common mode
filter component mismatch. Selecting the appropriate values
for the anti−aliasing filter is important to maintain peak
performance. Adding resistors to the signal path will
introduce noise. Keeping RCM as small as possible will
mitigate additional noise and error. The thermal noise
introduced by the filter resistors can be calculated by:
Many applications of the NCD98010/1 benefit by a
differential input buffer. A unity gain buffer provides current
drive to support the anti−aliasing filter and the 2 pF of ADC
input capacitance for applications where very high input
impedance is required. Input buffers also allow for control
of the common mode voltage to maximize the full scale
range of the ADC by setting VCM to VCC/2. Input buffers
are recommended for applications where the source of the
differential analog inputs require extremely high input
impedance. Noise introduced by the input buffers should be
less than the quantization noise of the ADC (74 dB SNR) to
avoid becoming the dominant noise source. Use buffers with
sufficient bandwidth (> Nyquist: FSAMPLE / 2) and an offset
less than 1/2 LSB to avoid introducing additional noise and
offset errors.
ǒ Ǔ
V n nV + Ǹ4 @ k @ T @ R CM
ǸHz
(3) Noise introduced by series anti−aliasing filter.
Where k = 1.38E−23 J/K (Boltzmann’s constant) and T is the
temperature in degree Kelvin.
Using smaller resistors and larger capacitors to achieve
the desired cutoff frequency will help mitigate noise and
charge injection. When choosing anti−aliasing filter
components, ensure that the settling time is short enough for
the input to be within 1/2 LSB of the desired value before the
CSN goes low to begin the conversion.
Anti−Alias Filter
The use of 2 common mode filters in addition to a
differential filter is recommended to maintain high common
mode rejection. These anti−aliasing filter are built using
RCM, CCM, and CDIFF as shown above in Figure 12 in the
Anti−Aliasing Filter box. The equations for determining the
cutoff frequencies of each filter are as follows:
f cutoff_CM(HZ) +
1
2p @ R CM @ C CM
(eq. 4)
Power Supply Decoupling
Local ADC supply decoupling is essential for maintaining
high power supply rejection ratio. For the NCD98010/1, the
analog supply (VCC) is also the reference for the ADC. Any
noise or drift greater than 1/2 LSB will affect the DNL and
INL of the converter. Use local decoupling capacitors of
(1) Cutoff frequency for the common mode filters.
f cutoff_DIFF(HZ) +
1
2p @ 2R CM @ C DIFF
(eq. 6)
(eq. 5)
(2) Cutoff frequency for the differential filter.
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10
NCD98010, NCD98011
Minimal Component Realization
1 mF. All decoupling capacitors must connect directly to a
low impedance ground plane in order to be effective. Short
traces or vias are required to minimize additional series
inductance. Ceramic capacitors are recommended based on
their low ESR and ESL. X7R ceramic capacitors are
recommended for applications involving a wide
temperature range.
For applications where minimizing board space trumps
ADC performance, the NCD98010/1 connection diagram
can be reduced as shown in Figure 19 below. The removal
of the input buffering may be an option depending on the
nature of the differential analog input source. Removing the
anti−aliasing filter would come at the expense of reduced
ENOB due to the digitization of aliased signals.
Anti-Aliasing Filter
VDD
1μF
CCM
+
VCC
VDD
INP
CSN
RCM
OUT
SCLK
INN
-
MCU / GPU or FPGA
Differential Analog Input
1μF
RCM
GND
CCM
NCD98010
Figure 19. Reduced Component Connection Diagram
Output Timing / Definition
Figure 20 below shows the NCD98010/1 output format. There is a 1 sample latency associated with the output data. The
digital data for analog input sampled are clocked out of the ADC by SCLK one conversion later, as shown in the diagram below.
Sample: N
CSN
SCLK
OUT
Sample: N+1
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Sample: N+2
D11
D10
D9
Data: N-1
D8
D7
D6
D5
D4
D3
D2
D1
D0
Data: N
Figure 20. NCD98010/1 Output Format
Layout Guidelines
signals. Keep the analog input signals and the VCC supply
/ reference signal away from noise digital signals.
Recommended bypass capacitances should be places as
close as possible to the VCC and VDD pins, and the path to
ground needs to be a low inductance low resistance local
connection.
Ideal PCB layouts have a ground plane placed underneath
the device and the PCB is partitioned into digital and analog
sections supporting the analog inputs to the ADC on one
side, and the digital interface on the other side. To avoid the
coupling of digital noise into the analog partition, care must
be taken not to cross digital signals with the analog input
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11
NCD98010, NCD98011
PACKAGE DIMENSIONS
US8
CASE 493
ISSUE D
X Y
A
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSION OR GATE BURR. MOLD
FLASH. PROTRUSION AND GATE BURR SHALL
NOT EXCEED 0.14MM (0.0055”) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH
AND PROTRUSION SHALL NOT EXCEED 0.14MM
(0.0055”) PER SIDE.
5. LEAD FINISH IS SOLDER PLATING WITH
THICKNESS OF 0.0076−0.0203MM (0.003−0.008”).
6. ALL TOLERANCE UNLESS OTHERWISE
SPECIFIED ±0.0508MM (0.0002”).
J
5
DETAIL E
B
L
1
4
R
S
G
P
U
C
SEATING
PLANE
T
D
H
0.10 (0.004) T
K
0.10 (0.004)
M
N
R 0.10 TYP
T X Y
V
M
F
DETAIL E
DIM
A
B
C
D
F
G
H
J
K
L
M
N
P
R
S
U
V
RECOMMENDED
SOLDERING FOOTPRINT*
8X
0.30
8X
0.68
3.40
1
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
12
MILLIMETERS
MIN
MAX
1.90
2.10
2.20
2.40
0.60
0.90
0.17
0.25
0.20
0.35
0.50 BSC
0.40 REF
0.10
0.18
0.00
0.10
3.00
3.20
0_
6_
0_
10 _
0.23
0.34
0.23
0.33
0.37
0.47
0.60
0.80
0.12 BSC
INCHES
MIN
MAX
0.075
0.083
0.087
0.094
0.024
0.035
0.007
0.010
0.008
0.014
0.020 BSC
0.016 REF
0.004
0.007
0.000
0.004
0.118
0.128
0_
6_
0_
10 _
0.010
0.013
0.009
0.013
0.015
0.019
0.024
0.031
0.005 BSC
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
X2QFN8, 1.5x1.5, 0.5P
CASE 722AM
ISSUE O
DATE 20 JUL 2018
GENERIC
MARKING DIAGRAM*
XXMG
G
X
= Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON94548G
X2QFN8, 1.5x1.5, 0.5P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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