NCH-RSL10-101WC51-ABG

Bluetooth) 5 Radio System-on-Chip (SoC) RSL10 Introduction RSL10 is an ultra−low−power, highly flexible multi−protocol 2.4 GHz radio specifically designed for use in high−performance wearable and medical applications. With its Arm® Cortex®−M3 Processor and LPDSP32 DSP core, RSL10 supports Bluetooth low energy technology and 2.4 GHz proprietary protocol stacks, without sacrificing power consumption. www.onsemi.com Key Features • • • • • • • • • • • • • • • • • Rx Sensitivity (Bluetooth Low Energy Mode, 1 Mbps): −94 dBm Data Rate: 62.5 to 2000 kbps Transmitting Power: −17 to +6 dBm Peak Rx Current = 5.6 mA (1.25 V VBAT) Peak Rx Current = 3.0 mA (3 V VBAT) Peak Tx Current (0 dBm) = 8.9 mA (1.25 V VBAT) Peak Tx Current (0 dBm) = 4.6 mA (3 V VBAT) Bluetooth 5 Certified Support for Bluetooth 5 features: LE 2−Mbit PHY (High Speed), as well as backwards compatibility and support for earlier Bluetooth Low Energy specifications Arm Cortex−M3 Processor Clocked at up to 48 MHz LPDSP32 for Audio Codec Supply Voltage Range: 1.1 − 3.3 V Current Consumption (1.25 V VBAT): ♦ Deep Sleep, IO Wake−up: 50 nA ♦ Deep Sleep, 8 kB RAM Retention: 300 nA ♦ Audio Streaming at 7 kHz Audio BW: 1.8 mA RX, 1.8 mA TX Current Consumption (3 V VBAT): ♦ Deep Sleep, IO Wake−up: 25 nA ♦ Deep Sleep, 8 kB RAM Retention: 100 nA ♦ Audio Streaming at 7 kHz Audio BW: 0.9 mA RX, 0.9 mA TX 384 kB of Flash Memory Highly−integrated System−on−Chip (SoC) Supports FOTA (Firmware Over−The−Air) Updates WLCSP51 CASE 567MT 1 48 QFN48 CASE 485BA RSL10 AWLYYWWG RSL10 AWLYWW G (QFN48) (WLCSP51) XXXXXX A WL Y or YY WW G or G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION Package Shipping† NCH−RSL10− 101WC51−ABG WLCSP51 (Pb−Free) 5000 / Tape & Reel NCH−RSL10− 101Q48−ABG QFN48 (Pb−Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2016 May, 2020 − Rev. 4 1 Publication Order Number: RSL10/D RSL10 FEATURES • Arm Cortex−M3 Processor: A 32−bit core for • • • • • • • • Flexible Supply Voltage: RSL10 integrates high− real−time applications, specifically developed to enable high−performance low−cost platforms for a broad range of low−power applications. LPDSP32: A 32−bit Dual Harvard DSP core that efficiently supports audio codecs required for wireless audio communication. Various codecs are available to customers through libraries that are included in RSL10’s development tools. Radio Frequency Front−End: Based on a 2.4 GHz RF transceiver, the RFFE implements the physical layer of the Bluetooth low energy technology standard and other proprietary or custom protocols. Protocol Baseband Hardware: Bluetooth 5 certified and includes support for a 2 Mbps RF link and custom protocol options. The RSL10 baseband stack is supplemented by support structures that enable implementation of ON Semiconductor and customer designed custom protocols. Highly−Integrated SoC: The dual−core architecture is complemented by high−efficiency power management units, oscillators, flash and RAM memories, a DMA controller, along with a full complement of peripherals and interfaces. Deep Sleep Mode: RSL10 can be put into a Deep Sleep Mode when no operations are required. Various Deep Sleep Mode configurations are available, including: ♦ “IO wake−up” configuration. The power consumption in deep sleep mode is 50 nA (1.25 V VBAT). ♦ Embedded 32 kHz oscillator running with interrupts from timer or external pin. The total current drain is 90 nA (1.25 V VBAT). ♦ As above with 8 kB RAM data retention. The total current drain is 300 nA (1.25 V VBAT). ♦ The DC−DC converter can be used in buck mode or LDO mode during Sleep Mode, depending on VBAT voltage. Standby Mode: Can be used to reduce the average power consumption for off−duty cycle operation, ranging typically from a few ms to a few hundreds of ms. The typical chip power consumption is 30 mA in Standby Mode. Multi−Protocol Support: Using the flexibility provided by LPDSP32, the Arm Cortex−M3 processor, and the RF front−end; proprietary protocols and other custom protocols are supported. • • • • • • • efficiency power regulators and has a VBAT range of 1.1 to 3.3 V. See Table 2. RECOMMENDED OPERATING CONDITIONS. Highly Configurable Interfaces: I2C, UART, two SPI interfaces, PCM interface, multiple GPIOs. It also supports a digital microphone interface (DMIC) and an output driver (OD). The Asynchronous Sample Rate Converter (ASRC) Block and Audio Sink Clock Blocks: Provides a means of synchronizing the audio sample rate between an audio source and an audio sink. The audio sink clock also provides a high accuracy mechanism to measure an input clock used for the RTC or protocol timing. Flexible Clocking Scheme: RSL10 must be clocked from the XTAL/PLL of the radio front−end at 48 MHz when transmitting or receiving RF traffic. When RSL10 is not transmitting/receiving RF traffic, it can run off the 48 MHz XTAL, the internal RC oscillators, the 32 kHz oscillator, or an external clock. A low frequency RTC clock at 32 kHz can also be used in Deep Sleep Mode. It can be sourced from either the internal XTAL, the RC oscillator, or a digital input pad. Diverse Memory Architecture: 76 kB of SRAM program memory (4 kB of which is PROM containing the chip boot−up program, and is thus unavailable to the user) and 88 kB of SRAM data memory are available. A total of 384 kB of flash is available to store the Bluetooth stack and other applications. The Arm Cortex−M3 processor can execute from SRAM and/or flash. Security: AES128 encryption hardware block for custom secure algorithms and code protection with authenticated debug port access (JTAG ‘lock’) Ultra−Low Power Consumption Application Examples: ♦ Audio Signal Streaming: IDD = 1.8 mA @ VBAT 1.25 V in Rx Mode for receiving, decoding and sending an 7 kHz bandwidth audio signal to the SPI interface using a proprietary custom audio protocol from ON Semiconductor. ♦ Low Duty Cycle Advertising: IDD 1.1 mA for advertising at all three channels at 5 second intervals @ VBAT 3 V, DCDC converter enabled. RoHS Compliant Device www.onsemi.com 2 RSL10 RSL10 INTERNAL BLOCK DIAGRAM The block diagram of the RSL10 chip is shown in Figure 1. Power Management Unit DC/DC, LDO Antenna Interface (No ext. Balun) DMA Sample Rate Converter A/D Converter (4 ext. channels) Bluetooth® Low Energy Radio (Bluetooth5) AES128 Encryption Engine SPI (2x) (Master/Slave) I2C Oscillators Data Memory 88 kB RAM 32-bit Dual-MAC DSP Core (LPDSP32) PWM (2x) UART GPIO (16x) 32 kHz XTAL 48 MHz XTAL RC Oscillator DIO Interface Switch MUX Program Memory 384 kB Flash 72 kB RAM EXT Clock I/O 4 kB ROM Arm® Cortex®-M3 processor 2-wire JTAG GP Timers (4x, 24bit) Wakeup (1x direct, 2x mapped to DIO) SYSTICK Timer Figure 1. RSL10 Block Diagram Table 1. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Min Max Unit VBAT Power supply voltage 3.63 V VDDO I/O supply voltage 3.63 V VSSRF RF front−end ground −0.3 V VSSA Analog ground −0.3 V VSSD Digital core and I/O ground −0.3 V Vin T functional T storage Voltage at any input pin VSSD−0.3 VDDO + 0.3 (Note 1) V Functional temperature range −40 85 °C Storage temperature range −40 85 °C Caution: Class 2 ESD Sensitivity, JESD22−A114−B (2000 V) The QFN package meets 450 V CDM level Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Up to a maximum of 3.63 V www.onsemi.com 3 RSL10 Table 2. RECOMMENDED OPERATING CONDITIONS Description Supply voltage operating range Symbol VBAT Conditions Input supply voltage on VBAT pin (Note 2) Min Typ Max Units 1.18 1.25 3.3 V Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 2. In order to be able to use a VBAT Min of 1.1 V, the following reduced operating conditions should be observed: − Maximum Tx power 0 dBm. − SYSCLK ≤ 24 MHz. − Functional temperature range limited to 0−50 °C The following trimming parameters should be used: − VCC = 1.10 V − VDDC = 0.92 V − VDDM = 1.05 V, will be limited by VCC at end of battery life − VDDRF = 1.05 V, will be limited by VCC at end of battery life. VDDPA should be disabled RSL10 should enter in end−of−battery−life operating mode if VCC falls below 1.03 V. VCC will remain above 1.03 V if VBAT ≥ 1.10 V under the restricted operating conditions described above. Table 3. ELECTRICAL PERFORMANCE SPECIFICATIONS Unless otherwise noted, the specifications mentioned in the table below are valid at 25°C for VBAT = VDDO = 1.25 V in LDO mode, or VBAT = VDDO = 3 V in DC−DC (buck) mode. Description Symbol Conditions Min Typ Max Units Current consumption RX, VBAT = 1.25 V, low latency IVBAT RX Mode, ON Semiconductor proprietary audio streaming protocol at 7 kHz audio BW, 5.5 ms delay. 1.8 mA Current consumption TX, VBAT = 1.25 V, low latency IVBAT TX Mode, ON Semiconductor |proprietary audio streaming protocol at 7 kHz audio BW, 5.5 ms delay. Transmit power: 0 dBm 1.8 mA Current consumption RX, VBAT = 1.25 V IVBAT RX Mode, ON Semiconductor proprietary audio streaming protocol at 7 kHz audio BW, 37 ms delay. 1.15 mA Deep sleep current, example 1, VBAT = 1.25 V Ids1 Wake up from wake up pin or DIO wake up. 50 nA Deep sleep current, example 2, VBAT = 1.25 V Ids2 Embedded 32 kHz oscillator running with interrupts from timer or external pin. 90 nA Deep sleep current, example 3, VBAT = 1.25 V Ids3 As Ids2 but with 8 kB RAM data retention. 300 nA Standby Mode current, VBAT = 1.25 V Istb Digital blocks and memories are not clocked and are powered at a reduced voltage. 30 mA Current consumption RX, VBAT = 3 V IVBAT RX Mode, ON Semiconductor proprietary audio streaming protocol at 7 kHz audio BW, 5.5 ms delay. 0.9 mA Current consumption TX, VBAT = 3 V IVBAT TX Mode, ON Semiconductor proprietary audio streaming protocol at 7 kHz audio BW, 5.5 ms delay. Transmit power: 0 dBm 0.9 mA Deep sleep current, example 1, VBAT = 3 V Ids1 Wake up from wake up pin or DIO wake up. 25 nA Deep sleep current, example 2, VBAT = 3 V Ids2 Embedded 32 kHz oscillator running with interrupts from timer or external pin. 40 nA Deep sleep current, example 3, VBAT = 3 V Ids3 As Ids2 but with 8 kB RAM data retention. 100 nA Standby Mode current, VBAT = 3 V Istb Digital blocks and memories are not clocked and are powered at a reduced voltage. 17 mA Arm Cortex−M3 processor running from RAM, VBAT= 3.0 V, IAR C/C++ Compiler for ARM 8.20.1.14183 1090 ULP Mark OVERALL EEMBC ULPMark BENCHMARK, CORE PROFILE ULPMark CP 3.0 V www.onsemi.com 4 RSL10 Table 3. ELECTRICAL PERFORMANCE SPECIFICATIONS (continued) Unless otherwise noted, the specifications mentioned in the table below are valid at 25°C for VBAT = VDDO = 1.25 V in LDO mode, or VBAT = VDDO = 3 V in DC−DC (buck) mode. Description Symbol Conditions Min Typ Max Units EEMBC ULPMark BENCHMARK, CORE PROFILE ULPMark CP 2.1 V Arm Cortex−M3 processor running from RAM, VBAT= 2.1 V, IAR C/C++ Compiler for ARM 8.20.1.14183 1260 ULP Mark EEMBC CoreMark BENCHMARK for the Arm Cortex−M3 Processor and the LPDSP32 DSP Arm Cortex−M3 processor running from RAM At 48 MHz SYSCLK. Using the IAR 8.10.1 C compiler, certified 159 Core Mark LPDSP32 running from RAM At 48 MHz SYSCLK Using the 2020.03 release of the Synopsys LPDSP32 C compiler 174 Core Mark Arm Cortex−M3 processor and LPDSP32 running from RAM, VBAT = 1.25 V At 48 MHz SYSCLK 119 Core Mark/ mA Arm Cortex−M3 processor and LPDSP32 running from RAM, VBAT = 3 V At 48 MHz SYSCLK 284 Core Mark/ mA Arm Cortex−M3 processor running CoreMark from RAM, VBAT = 1.25 V At 48 MHz SYSCLK 29.1 mA/MHz Arm Cortex−M3 processor running CoreMark from RAM, VBAT = 3 V At 48 MHz SYSCLK 12.3 mA/MHz Arm Cortex−M3 processor running CoreMark from Flash, VBAT = 1.25 V At 48 MHz SYSCLK 34.3 mA/MHz Arm Cortex−M3 processor running CoreMark from Flash, VBAT = 3 V At 48 MHz SYSCLK 14.6 mA/MHz LPDSP32 running CoreMark from RAM, VBAT = 1.25 V At 48 MHz SYSCLK 19.5 mA/MHz LPDSP32 running CoreMark from RAM, VBAT = 3 V At 48 MHz SYSCLK 8.2 mA/MHz INTERNALLY GENERATED VDDC: Digital Block Supply Voltage Supply voltage: operating range VDDC 0.92 Supply voltage: trimming range VDDCRANGE 0.75 Supply voltage: trimming step VDDCSTEP 1.15 1.32 (Note 3) V 1.38 V 10 mV INTERNALLY GENERATED VDDM: Memories Supply Voltage Supply voltage: operating range VDDM 1.05 Supply voltage: trimming range VDDMRANGE 0.75 Supply voltage: trimming step VDDMSTEP 1.15 1.32 (Note 4) V 1.38 V 10 mV INTERNALLY GENERATED VDDRF: Radio Front end supply voltage Supply voltage: operating range VDDRF 1.00 Supply voltage: trimming range VDDRFRANGE 0.75 Supply voltage: trimming step VDDRFSTEP 1.10 1.32 (Notes 5 and 6) 1.38 10 V V mV INTERNALLY GENERATED VDDPA: Optional Radio Power Amplifier Supply Voltage Supply voltage: operating range VDDPA 1.05 Supply voltage: trimming range VDDPARANGE 1.05 Supply voltage: trimming step VDDPASTEP 1.3 10 www.onsemi.com 5 1.68 V 1.68 V mV RSL10 Table 3. ELECTRICAL PERFORMANCE SPECIFICATIONS (continued) Unless otherwise noted, the specifications mentioned in the table below are valid at 25°C for VBAT = VDDO = 1.25 V in LDO mode, or VBAT = VDDO = 3 V in DC−DC (buck) mode. Description Symbol Conditions Min Typ Max Units INTERNALLY GENERATED VDDPA: Optional Radio Power Amplifier Supply Voltage Supply voltage: trimming step DCDCSTEP 10 mV VDDO PAD SUPPLY VOLTAGE: Digital Level High Voltage Digital I/O supply VDDO 1.1 1.25 3.3 V 1.4 3.3 V 1.1 3.3 V 1.32 V INDUCTIVE BUCK DC−DC CONVERTER VBAT range when the DC−DC converter is active (Note 7) IN_RANGE VBAT range when the LDO is active IN_RANGE Output voltage: trimming range DCDC LDO DCDC 1.1 1.2 OUT_RANGE Supply voltage: trimming step DCDCSTEP 10 mV POWER−ON RESET POR voltage VBATPOR 0.4 0.8 1.0 V −8 dB 3000 kbps 4000 kbps 2000 kbps RADIO FRONT−END: General Specifications RF input impedance Zin Single ended Input reflection coefficient S11 All channels Data rate FSK / MSK / GFSK RFSK OQPSK as MSK 62.5 1000 Data rate 4−FSK On−air data rate bps W 50 GFSK 250 RADIO FRONT−END: Crystal and Clock Specifications Xtal frequency Equiv. series Res. Differential equivalent load capacitance FXTAL ESRXTAL CLXTAL Fundamental 48 RSL10 has internal load capacitors, additional external capacitors are not required 20 Internal load capacitors (NO EXTERNAL LOAD CAPACITORS REQUIRED) 6 Settling time MHz 80 W 8 10 pF 0.5 1.5 ms 2500 MHz RADIO FRONT−END: Synthesizer Specifications Frequency range FRF Supported carrier frequencies 2360 RX frequency step RX Mode frequency synthesizer resolution 100 Hz TX frequency step TX Mode frequency synthesizer resolution 600 Hz PLL Settling time, RX tPLL_RX RX Mode 15 25 ms PLL Settling time, TX tPLL_TX TX mode, BLE modulation 5 10 ms RADIO FRONT−END: Receive Mode Specifications Current consumption at 1 Mbps, VBAT = 1.25 V IBATRFRX VDDRF = 1.1 V, 100% duty cycle 5.6 mA Current consumption at 2 Mbps, VBAT = 1.25 V IBATRFRX VDDRF = 1.1 V, 100% duty cycle 6.2 mA Current consumption at 1 Mbps, VBAT = 3 V, DC−DC IBATRFRX VDDRF = 1.1 V, 100% duty cycle 3.0 mA Current consumption at 2 Mbps, VBAT = 3 V, DC−DC IBATRFRX VDDRF = 1.1 V, 100% duty cycle 3.4 mA RX Sensitivity, 0.25 Mbps 0.1% BER (Notes 8, 9) −97 dBm RX Sensitivity, 0.5 Mbps 0.1% BER (Notes 8, 9) −96 dBm www.onsemi.com 6 RSL10 Table 3. ELECTRICAL PERFORMANCE SPECIFICATIONS (continued) Unless otherwise noted, the specifications mentioned in the table below are valid at 25°C for VBAT = VDDO = 1.25 V in LDO mode, or VBAT = VDDO = 3 V in DC−DC (buck) mode. Description Symbol Conditions Min Typ Max Units RADIO FRONT−END: Receive Mode Specifications RX Sensitivity, 1 Mbps, BLE 0.1% BER (Notes 8, 9) Single−ended on chip antenna match to 50 W −94 dBm RX Sensitivity, 2 Mbps, BLE 0.1% BER (Notes 8, 9) −92 dBm RSSI effective range Without AGC 60 dB 2.4 dB 48 dB 6 dB 5 dBm Tx power 0 dBm, VDDRF = 1.07 V, VDDPA: off, LDO mode 8.9 mA Tx power 3 dBm, VDDRF = 1.1 V, VDDPA = 1.26 V, LDO mode 17.4 mA Tx power 6 dBm, VDDRF = 1.1 V, VDDPA = 1.60 V, LDO mode 25 mA Tx power 0 dBm, VDDRF = 1.07 V, VDDPA: off, DC−DC mode 4.6 mA Tx power 3 dBm, VDDRF = 1.1 V, VDDPA = 1.26 V, DC−DC mode 8.6 mA Tx power 6 dBm, VDDRF = 1.1 V, VDDPA = 1.60 V, DC−DC mode 12 mA RSSI step size RX AGC range RX AGC step size Programmable Max usable signal level 0.1% BER 0 RADIO FRONT−END: Transmit Mode Specifications Tx peak power consumption at VBAT = 1.25 V (Note 10) Tx peak power consumption at VBAT = 3 V (Note 10) IBATRFTX IBATRFTX Transmit power range BLE or 802.15.4 OQPSK −17 +6 Transmit power step size Full band. Transmit power accuracy Tx power 3 dBm. Full band. Relative to the typical value. −1.5 +1 dB Tx power 0 dBm. Full band. Relative to the typical value. −1.5 1.5 dB 1 dBm dB Power in 2nd harmonic 0 dBm mode. 50 W for “Typ” value. (Note 11) −31 −18 dBm Power in 3rd harmonic 0 dBm mode. 50 W for “Typ” value. (Note 11) −40 −31 dBm Power in 4th harmonic 0 dBm mode. 50 W for “Typ” value. (Note 11) −49 −42 dBm 12 ADC Resolution Input voltage range INL DNL Channel sampling frequency ADCRES 8 14 bits ADCRANGE 0 2 V ADCINL −2 +2 mV ADCDNL ADCCH_SF For the 8 channels sequentially, SLOWCLK = 1 MHz −1 +1 mV 0.0195 6.25 kHz 50 kHz 32 kHz ON−CHIP RC OSCILLATOR Untrimmed Frequency Trimming steps FreqUNTR 20 Steps 32 1.5 % 3 MHz ON−CHIP RC OSCILLATOR Untrimmed Frequency FreqUNTR 2 3 5 MHz Trimming steps Steps 1.5 % Hi Speed mode Fhi 10 MHz www.onsemi.com 7 RSL10 Table 3. ELECTRICAL PERFORMANCE SPECIFICATIONS (continued) Unless otherwise noted, the specifications mentioned in the table below are valid at 25°C for VBAT = VDDO = 1.25 V in LDO mode, or VBAT = VDDO = 3 V in DC−DC (buck) mode. Description Symbol Conditions Min Typ Max Units 32 kHz ON−CHIP CRYSTAL OSCILLATOR (Note 12) Output Frequency Freq32k Depends on xtal parameters 32768 Startup time 1 Internal load trimming range Steps of 0.4 pF Load Capacitance No external load capacitors required. Maximum external parasitic capacity allowed (package, routing, etc.) 0 ESR Duty Cycle 40 50 Hz 3 s 25.2 pF 3.5 pF 100 kW 60 % DC CHARACTERISTICS OF THE DIGITAL PADS − With VDDO = 2.97 V – 3.3 V, nominal: 3.0 V Logic Voltage level for high input VIH 2 VDDO+0.3 V Voltage level for low input VIL VSSD− 0.3 0.8 V DC CHARACTERISTICS OF THE DIGITAL PADS − With VDDO = 1.1 V – 1.32 V, nominal: 1.2 V Logic Voltage level for high Input VIH 0.65* VDDO VDDO+0.3 V Voltage level for low input VIL VSSD− 0.3 0.35* VDDO V IDIO 2 12 mA DIO DRIVE STRENGTH DIO drive strength 12 FLASH SPECIFICATIONS Endurance of the 384 kB of flash 100,000 write/ erase cycles Endurance for sections NVR1, NVR2, and NVR3 (6 kB in total) 1000 write/ erase cycles 25 years Retention Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. The maximum VDDC voltage cannot exceed the VBAT input voltage or the VCC output from the buck converter. 4. The maximum VDDM voltage cannot exceed the VBAT input voltage or the VCC output from the buck converter. 5. The maximum VDDRF voltage cannot exceed the VBAT input voltage or the VCC output from the buck converter. 6. The VDDRF calibrated targets are: − 1.10 V (TX power > 0 dBm, with optimal RX sensitivity) − 1.07 V (TX power = 0 dBm) − 1.20 V (TX power = 2 dBm) The VDDPA calibrated targets are: − 1.30 V − 1.26 V (TX power = 3 dBm, assumes VDDRF = 1.10 V) − 1.60 V (TX power = 6 dBm, assumes VDDRF = 1.10 V) 7. The LDO can be used to regulate down from VBAT and generate VCC. For VBAT values higher than 1.5 V, the LDO is less efficient and it is possible to save power by activating the DC−DC converter to generate VCC. 8. Signal generated by RF tester. 9. 0.5 to 1.0 dB degradation in the RX sensitivity is present on the QFN package vs WLCSP. This is attributed to the presence of the metal slug of the QFN package which is in close proximity to on−chip inductors. 10. All values are based on evaluation board performance at the antenna connector, including the harmonic filter loss 11. The values shown here are without RF filter. Harmonics need to be filtered with an external filter (See “RF Filter” on Table 6). 12. These specifications have been validated with the Epson Toyocom MC – 306 crystal www.onsemi.com 8 RSL10 Table 4. VDDM Target Trimming Voltage in Function of VDDO Voltage NOTE: VDDM Voltage (V) DIO_PAD_CFG DRIVE Maximum VDDO Voltage (V) 1.05 1 2.7 1.05 0 3.2 1.10 0 3.3 These are trimming targets at room/ATE temperature 25X30°C. Table 5. VDDC Target Trimming Voltage in Function of SYSCLK Frequency NOTE: VDDC Voltage (V) Maximum SYSCLK Frequency (MHz) Restriction 0.92 ≤ 24 The ADC will be functional in low frequency mode and between 0 and 85°C only. 1.00 ≤ 24 Fully functional 1.05 48 Fully functional These are trimming targets at room/ATE temperature 25X30°C. Table 6. RECOMMENDED EXTERNAL COMPONENTS: Components Function Recommended typical value Tolerance Cap (VBAT−VSSA) VBAT decoupling 4.7 mF // 100 pF (Note 13) ±20% Cap (VDDO−VSSD) VDDO decoupling 1 mF ±20% Cap (VDDRF−VSSRF) VDDRF decoupling 2.2 mF ±20% VCC decoupling Low ESR 2.2 mF (Note 14) or 4.7 mF ±20% Cap (VDDA−VSSA) VDDA decoupling 1 mF ±20% Cap (CAP0−CAP1) Pump capacitor for the charge pump 1 mF ±20% Inductor (DC−DC) DC−DC converter inductance Low ESR 2.2 mH (See Table 7 below) ±20% Xtal_32 kHz Xtal for 32 kHz oscillator − MC – 306, Epson − CM8V−T1A, Micro Crystal Switzerland WMRAG32K76CS1C00R0, Murata Xtal_48 MHz Xtal for 48 MHz oscillator 8Q−48.000MEEV−T, TXC Corporation, Taiwan XRCTD48M000NXQ2ER0, Murata External harmonic filter 1.5 pF / 3 nH / 1.5 pF / 1.8 nH Cap (VCC−VSSA) RF filter (Note 15) ±20% NOTE: All capacitors used must have good RF performance. 13. The recommended decoupling capacitance uses 2 capacitors with the values specified. 14. Example: AMK105BJ225_P, Taiyo Yuden. 15. For improved harmonic performance in environments where RSL10 is operating in close proximity to smartphones or base stations, FBAR filters such as the Broadcom ACPF−7924 can be applied instead of the suggested discrete harmonic filter. Table 7. RECOMMENDED DC−DC CONVERTER INDUCTANCE TABLE Manufacturer Part Number Case Size Comments Taiyo Yuden CKP2012N_2R2 0805 SMD with Tmax = 1.0 mm A degradation of 1 dB in the RX sensitivity is expected in DC−DC mode (Vbat = 3.3 V) versus LDO mode operation. Taiyo Yuden CBMF1608T2R2M 0603 SMD with Tmax = 1.0 mm A degradation of