NCID9211

DATA SHEET www.onsemi.com High Speed Dual-Channel, Bi-Directional Ceramic Digital Isolator NCID9211 SOIC16 W CASE 751EN Description The NCID9211 is a galvanically isolated full duplex, bi−directional, high−speed dual−channel digital isolator with output enable. This device supports isolated communications thereby allowing digital signals to communicate between systems without conducting ground loops or hazardous voltages. It utilizes onsemi’s patented galvanic off−chip capacitor isolation technology and optimized IC design to achieve high insulation and high noise immunity, characterized by high common mode rejection and power supply rejection specifications. The thick ceramic substrate yields capacitors with ~25 times the thickness of thin film on−chip capacitors and coreless transformers. The result is a combination of the electrical performance benefits that digital isolators offer with the safety reliability of a >0.5 mm insulator barrier similar to what has historically been offered by optocouplers. The device is housed in a 16−pin wide body small outline package. MARKING DIAGRAM AWLYWW 9211 A WL Y WW 9211 = Assembly Location = Wafer Lot / Assembly Lot = Year = Work Week = Specific Device Code Features • Off−Chip Capacitive Isolation to Achieve Reliable High Voltage • • • • • • • • • Insulation ♦ DTI (Distance Through Insulation): ≥ 0.5 mm ♦ Maximum Working Insulation Voltage: 2000 Vpeak Full Duplex, Bi−directional Communication 100 KV/ms Minimum Common Mode Rejection High Speed: ♦ 50 Mbit/s Data Rate (NRZ) ♦ 25 ns Maximum Propagation Delay ♦ 10 ns Maximum Pulse Width Distortion 8 mm Creepage and Clearance Distance to Achieve Reliable High Voltage Insulation. Specifications Guaranteed Over 2.5 V to 5.5 V Supply Voltage and −40°C to 125°C Extended Temperature Range Over Temperature Detection Output Enable Function (Primary and Secondary Side) NCIV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable (Pending) Safety and Regulatory Approvals ♦ UL1577, 5000 VRMS for 1 Minute ♦ DIN EN/IEC 60747−17 (Pending) Typical Applications • Isolated PWM Control • Industrial Fieldbus Communications • Microprocessor System Interface (SPI, I2C, etc.) © Semiconductor Components Industries, LLC, 2020 September, 2021 − Rev. 3 ORDERING INFORMATION See detailed ordering and shipping information on page 10 of this data sheet. • Programmable Logic Control • Isolated Data Acquisition System • Voltage Level Translator 1 Publication Order Number: NCID9211/D NCID9211 PIN CONFIGURATION BLOCK DIAGRAM 1 16 V DD 2 GND 1 2 15 GND 2 NC 3 14 NC EN 1 4 13 EN 2 V OA 5 12 V INA V INB 6 11 V OB NC 7 10 NC GND 1 8 9 ISOLATION V DD1 GND 2 Figure 2. Functional Block Diagram Figure 1. Pin and Channel Configuration PIN DEFINITIONS Pin No. Name Description 1 VDD1 Power Supply, Primary Side 2 GND1 Ground, Primary Side 3 NC No Connect 4 EN1 Enable, Primary Side 5 VOA Output, Channel A 6 VINB Input, Channel B 7 NC No Connect 8 GND1 Ground, Primary Side 9 GND2 Ground, Secondary Side 10 NC No Connect 11 VOB Output, Channel B 12 VINA Input, Channel A 13 EN2 Enable, Secondary Side 14 NC No Connect 15 GND2 Ground, Secondary Side 16 VDD2 Power Supply, Secondary Side TRUTH TABLE (Note 1) VINX ENX VDDI VDDO VOX H H / NC Power Up Power Up H Normal Operation L H / NC Power Up Power Up L Normal Operation X L Power Up Power Up Hi−Z X H / NC Power Down Power Up L Default low; VOX return to normal operation when VDDI change to Power Up X H / NC Power Up Power Down Undetermined (Note 2) VOX return to normal operation when VDDO change to Power Up Comment 1. VINX = Input signal of a given channel (A or B). ENX = Enable pin for primary or secondary side (1 or 2). VOX = Output signal of a given channel (A or B). VDDI = Input−side VDD. VDDO = Output−side VDD. X = Irrelevant. H = High level. L = Low level. NC = No Connection. 2. The outputs are in undetermined state when VDDO < VUVLO. www.onsemi.com 2 NCID9211 SAFETY AND INSULATION RATINGS As per DIN EN/IEC 60747−17, this digital isolator is suitable for “safe electrical insulation” only within the safety limit data. Compliance with the safety ratings must be ensured by means of protective circuits. Parameter Symbol Min. Installation Classifications per DIN VDE 0110/1.89 Table 1 Rated Mains Voltage Typ. < 150 VRMS I–IV < 300 VRMS I–IV < 450 VRMS I–IV < 600 VRMS I–IV < 1000 VRMS I–III Climatic Classification Max. Units 40/125/21 Pollution Degree (DIN VDE 0110/1.89) 2 CTI Comparative Tracking Index (DIN IEC 112/VDE 0303 Part 1) 600 VPR Input−to−Output Test Voltage, Method b, VIORM x 1.875 = VPR, 100% Production Test with tm = 1 s, Partial Discharge < 5 pC 3750 Vpeak Input−to−Output Test Voltage, Method a, VIORM x 1.6 = VPR, Type and Sample Test with tm = 10 s, Partial Discharge < 5 pC 3200 Vpeak VIORM Maximum Working Insulation Voltage 2000 Vpeak VIOTM Highest Allowable Over Voltage 8000 Vpeak External Creepage 8.0 mm External Clearance 8.0 mm Insulation Thickness 0.50 mm TCase Safety Limit Values – Maximum Values in Failure; Case Temperature 150 °C PS,INPUT Safety Limit Values – Maximum Values in Failure; Input Power 100 mW PS,OUTPUT Safety Limit Values – Maximum Values in Failure; Output Power 600 mW Insulation Resistance at TS, VIO = 500 V 109 Ω RIO ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise specified) Symbol Value Units TSTG Storage Temperature −55 to +150 °C TOPR Operating Temperature −40 to +125 °C Junction Temperature −40 to +150 °C 260 for 10sec °C TJ Parameter TSOL Lead Solder Temperature (Refer to Reflow Temperature Profile) VDD Supply Voltage (VDDx) −0.5 to 6 V V Voltage (VINx, VOx, ENx) −0.5 to 6 V IO Average Output Current 15 mA PD Power Dissipation 210 mW Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 3 NCID9211 RECOMMENDED OPERATING CONDITIONS Symbol TA VDD1 VDD2 Parameter Min. Max. Unit Ambient Operating Temperature −40 +125 °C Supply Voltage (Notes 3, 4) 2.5 5.5 V 0.7 x VDDI VDDI V 0 0.1 x VDDI V VINH High Level Input Voltage VINL Low Level Input Voltage VUVLO+ Supply Voltage UVLO Rising Threshold 2.2 V VUVLO− Supply Voltage UVLO Falling Threshold 2.0 V Supply Voltage UVLO Hysteresis 0.1 V IOH High Level Output Current −2 IOL Low Level Output Current − 2 mA DR Signaling Rate 0 50 Mbps UVLOHYS − mA Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 3. During power up or down, ensure that both the input and output supply voltages reach the proper recommended operating voltages to avoid any momentary instability at the output state. 4. For reliable operation at recommended operating conditions, VDD supply pins require at least a pair of external bypass capacitors, placed within 2 mm from VDD pins 1 and 16 and GND pins 2 and 15. Recommended values are 0.1 mF and 1 mF. ISOLATION CHARACTERISTICS Apply over all recommended conditions. All typical values are measured at TA = 25°C. Symbol Parameter Conditions VISO Input−Output Isolation Voltage TA = 25°C, Relative Humidity < 50%, t = 1.0 minute, II−O v 10 mA, 50 Hz (Notes 5, 6, 7) RISO Isolation Resistance VI−O = 500 V (Note 5) CISO Isolation Capacitance VI−O = 0 V, Frequency = 1.0 MHz (Note 5) Min. Typ. Max. 5000 Units VRMS 1011 1 pF 5. Device is considered a two−terminal device: pins 1 to 8 are shorted together and pins 9 to 16 are shorted together. 6. 5,000 VRMS for 1−minute duration is equivalent to 6,000 VRMS for 1−second duration. 7. The input−output isolation voltage is a dielectric voltage rating per UL1577. It should not be regarded as an input−output continuous voltage rating. For the continuous working voltage rating, refer to equipment−level safety specification or DIN EN/IEC 60747−17 Safety and Insulation Ratings Table on page 3. ELECTROSTATIC DISCHARGE RATINGS Symbol Parameter Conditions Ratings Units V HBM Human Body Model JS−001−2017; AEC−Q100−002−Rev E (Note 9) ±3000 CDM Charged Device Model JS−002−2018; AEC−Q100−011−Rev D (Note 10) ±1000 ESDI Contact Discharge IEC 61000−4−2 Insulation Barrier Withstand Test (Note 8) ±8000 Air Discharge ±15000 8. Device is considered a two−terminal device: pins 1 to 8 are shorted together and pins 9 to 16 are shorted together. 9. ESD Human Body Model for NCID9211 tested per JEDEC JS−001−2017 standard; NCIV9211 tested per AEC−Q100−002−Rev E standard. 10. ESD Charged Device Model for NCID9211 tested per JEDEC JS−002−2018 standard; NCIV9211 tested per AEC−Q100−011−Rev D standard. www.onsemi.com 4 NCID9211 ELECTRICAL CHARACTERISTICS Apply over all recommended conditions, TA =−40°C to +125°C, VDD1 = VDD2 = 2.5 V to 5.5 V, unless otherwise specified. All typical values are measured at TA = 25°C. Symbol Parameter Conditions VOH High Level Output Voltage IOH = –4 mA VOL Low Level Output Voltage IOL = 4 mA Min. 0.11 Rising Input Voltage Threshold VINT− Falling Input Voltage Threshold 0.1 x VDDI Input Threshold Voltage Hysteresis 0.1 x VDDI IINH High Level Input Current VIH = VDDI IINL Low Level Input Current VIL = 0 V CMTI CIN Units Figure V 7 0.4 V 8 0.7 x VDDI V V 0.2 x VDDI V 1 −1 Common Mode Transient Immunity VI = VDDI or 0 V, VCM = 1500 V Input Capacitance Max. VDDO – 0.4 VDDO – 0.1 VINT+ VINT(HYS) Typ. 100 VIN = VDDI/2 + 0.4 x sin (2pft), f = 1MHz, VDD = 5 V μA μA 150 kV/ms 2 pF 12 Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. SUPPLY CURRENT CHARACTERISTICS Apply over all recommended conditions, TA =−40°C to +125°C unless otherwise specified. All typical values are measured at TA = 25°C. Symbol IDD1 IDD2 Parameter DC Supply Current Input Low Conditions VDD = 5 V, EN = 0 V / 5 V, VIN = 0 V IDD2 VDD = 5 V, EN = 0 V / 5 V, VIN = 5 V 11.8 VDD = 2.5 V, EN = 0 V / 2.5 V, VIN = 2.5 V AC Supply Current 1 Mbps IDD2 IDD1 IDD2 AC Supply Current 10 Mbps IDD1 IDD2 IDD1 IDD2 IDD2 IDD1 IDD2 IDD1 IDD2 6 14.5 mA 11.7 14.3 11.6 14.3 11.8 IDD1 IDD1 6.1 11.9 IDD2 IDD2 Figure 12.1 VDD = 3.3 V, EN = 0 V / 3.3 V, VIN = 3.3 V IDD1 IDD1 4.4 4.3 IDD2 IDD2 mA 4.8 DC Supply Current Input High IDD1 IDD1 Units 6.3 VDD = 2.5 V, EN = 0 V / 2.5 V, VIN = 0 V IDD2 IDD2 Max. 4.5 4.9 IDD1 IDD1 Typ. 5.0 VDD = 3.3 V, EN = 0 V / 3.3 V, VIN = 0 V IDD1 Min. AC Supply Current 50 Mbps VDD = 5 V, EN = 5 V, CL = 15 pF VIN = 5 V Square Wave 8.3 VDD = 3.3 V, EN = 3.3 V, CL = 15 pF VIN = 3.3 V Square Wave 8.1 VDD = 2.5 V, EN = 2.5 V, CL = 15 pF VIN = 2.5 V Square Wave 8.0 VDD = 5 V, EN = 5 V, CL = 15 pF VIN = 5 V Square Wave 9.9 10.3 8.5 10.1 8.4 12 mA 10.2 8.9 VDD = 2.5 V, EN = 2.5 V, CL = 15 pF VIN = 2.5 V Square Wave 8.6 VDD = 5 V, EN = 5 V, CL = 15 pF VIN = 5 V Square Wave 14.8 VDD = 3.3 V, EN = 3.3 V, CL = 15 pF VIN = 3.3 V Square Wave 12.1 VDD = 2.5 V, EN = 2.5 V, CL = 15 pF VIN = 2.5 V Square Wave 11.1 5 mA 8.7 VDD = 3.3 V, EN = 3.3 V, CL = 15 pF VIN = 3.3 V Square Wave www.onsemi.com 10.5 11 9.3 10.5 9.0 17.5 15.2 14.3 12.6 11.6 13 mA 3,4 NCID9211 SWITCHING CHARACTERISTICS Apply over all recommended conditions, TA =−40°C to +125°C unless otherwise specified. All typical values are measured at TA = 25°C. Symbol Parameter tPHL Propagation Delay to Logic Low Output (Note 8) tPLH PWD tPSK(PP) Conditions Min. Typ. Max. Units Figure VDD = EN = 5 V, VIN Square Wave, CL = 15 pF 17.0 25 ns 6,9 VDD = EN = 3.3 V, VIN Square Wave, CL = 15 pF 18.3 25 ns 10 ns 10 ns VDD = EN = 2.5 V, VIN Square Wave, CL = 15 pF 20.0 Propagation Delay VDD = EN = 5 V, VIN Square Wave, CL = 15 pF to Logic High Output VDD = EN = 3.3 V, VIN Square Wave, CL = 15 pF (Note 9) VDD = EN = 2.5 V, VIN Square Wave, CL = 15 pF 13.0 Pulse Width Distortion | tPHL – tPLH | (Note 10) VDD = EN = 5 V, VIN Square Wave, CL = 15 pF 3.6 VDD = EN = 3.3 V, VIN Square Wave, CL = 15 pF 3.8 VDD = EN = 2.5 V, VIN Square Wave, CL = 15 pF 3.8 Propagation Delay Skew (Part to Part) (Note 11) VDD = EN = 5 V, VIN Square Wave, CL = 15 pF 14.5 16.0 −10 VDD = EN = 3.3 V, VIN Square Wave, CL = 15 pF VDD = EN = 2.5 V, VIN Square Wave, CL = 15 pF tR tF tPZL tPLZ tPZH tPHZ Output Rise Time (10% to 90%) Output Fall Time (90% to 10%) High Impedance to Logic Low Output Delay (Note 12) Logic Low to High Impedance Output Delay (Note 13) High Impedance to Logic High Output Delay (Note 14) Logic High to High Impedance Output Delay (Note 15) VDD = EN = 5 V, VIN Square Wave, CL = 15 pF 1.1 VDD = EN = 3.3 V, VIN Square Wave, CL = 15 pF 1.5 VDD = EN = 2.5 V, VIN Square Wave, CL = 15 pF 2.2 VDD = EN = 5 V, VIN Square Wave, CL = 15 pF 1.1 VDD = EN = 3.3 V, VIN Square Wave, CL = 15 pF 1.4 VDD = EN = 2.5 V, VIN Square Wave, CL = 15 pF 3.0 VDD = 5 V, RL = 1 kW 8.1 VDD = 3.3 V, RL = 1 kW 9.7 VDD = 2.5 V, RL = 1 kW 12.0 VDD = 5 V, RL = 1 kW 10.4 VDD = 3.3 V, RL = 1 kW 12.2 VDD = 2.5 V, RL = 1 kW 16.5 VDD = 5 V, RL = 1 kW 0.54 VDD = 3.3 V, RL = 1 kW 0.51 VDD = 2.5 V, RL = 1 kW 0.50 VDD = 5 V, RL = 1 kW 11.0 VDD = 3.3 V, RL = 1 kW 12.3 VDD = 2.5 V, RL = 1 kW 14.0 ns ns 25 ns 25 ns 1 μs 25 ns 10 11 11. Propagation delay tPHL is measured from the 50% level of the falling edge of the input pulse to the 50% level of the falling edge of the VO signal. 12. Propagation delay tPLH is measured from the 50% level of the rising edge of the input pulse to the 50% level of the rising edge of the VO signal. 13. PWD is defined as | tPHL – tPLH | for any given device. 14. Part−to−part propagation delay skew is the difference between the measured propagation delay times of a specified channel of any two parts at identical operating conditions and equal load. 15. Enable delay tPZL is measured from the 50% level of the rising edge of the EN pulse to the 50% of the falling edge of the VO signal as it switches from high impedance state to low state. 16. Disable delay tPLZ is measured from the 50% level of the falling edge of the EN pulse to 0.5 V level of the rising edge of the VO signal as it switches from low state to high impedance state. 17. Enable delay tPZH is measured from the 50% level of the rising edge of the EN pulse to the 50% of the rising edge of the VO signal as it switches from high impedance state to high state. 18. Disable delay tPHZ is measured from the 50% level of the falling edge of the EN pulse to VOH − 0.5 V level of the falling edge of the VO signal as it switches from high state to high impedance state. www.onsemi.com 6 NCID9211 TYPICAL PERFORMANCE CHARACTERISTICS 20 TA = 25°C IDD1 LOAD = No Load IDD2 15 IDD1, IDD2 − SUPPLY CURRENT (mA) IDD1, IDD2 − SUPPLY CURRENT (mA) 20 VDD = 3.3 V VDD = 5 V 10 VDD = 2.5 V 5 0 0 10 20 30 40 TA = 25°C IDD1 LOAD = 15 pF IDD2 15 10 VDD = 2.5 V 5 0 50 0 10 20 DATA RATE (Mbps) 40 50 Figure 4. Supply Current vs. Data Rate (Load = 15 pF) 25 3.0 tP − PROPAGATION DELAY (ns) VUVLO − Supply Voltage UVLO Threshold (V) 30 DATA RATE (Mbps) Figure 3. Supply Current vs. Data Rate (No Load) 2.5 VUVLO+ VUVLO− 2.0 1.5 −40 −20 0 20 40 60 80 100 5 −40 VOL − LOW LEVEL OUTPUT VOLTAGE (V) VDD = 5 V VDD = 3.3 V VDD = 2.5 V 2 1 −6 −4 −2 0 20 40 60 80 100 120 Figure 6. Propagation Delay vs. Ambient Temperature 3 −8 −20 tPLH VDD = 5 V TA - AMBIENT TEMPERATURE (°C ) 4 0 −10 tPLH VDD = 3.3 V tPLH VDD = 2.5 V 10 120 6 5 tPHL VDD = 2.5 V tPHL VDD = 3.3 V 15 Figure 5. Supply Voltage UVLO Threshold vs. Ambient Temperature TA = 25 °C tPHL VDD = 5 V 20 TA - AMBIENT TEMPERATURE (°C) VOH − HIGH LEVEL OUTPUT VOLTAGE (V) VDD = 3.3 V VDD = 5 V 0 1.0 TA = 25 °C 0.8 0.6 VDD = 2.5 V 0.4 VDD = 3.3 V VDD = 5 V 0.2 0.0 IOH - HIGH LEVEL OUTPUT CURRENT (mA ) 0 2 4 6 8 10 IOL - LOW LEVEL OUTPUT CURRENT (mA ) Figure 7. High Level Output Voltage vs. Current Figure 8. Low Level Output Voltage vs. Current www.onsemi.com 7 NCID9211 VDDI + − ISOLATION TEST CIRCUITS V VIN VO + − VEN + − 50% VI VDDO tPLH tPHL 90% CL 50% VO 10% tR tF Figure 9. VIN to VO Propagation Delay Test Circuit and Waveform VDDI ISOLATION RL + − + − VIN VO VI + − 50% VI VDDO tPZL tPLZ VO CL 0.5 V 50% VEN VDDI ISOLATION Figure 10. EN to Logic Low VO Propagation Delay Test Circuit and Waveform + − + − VIN VO VI CL + − VDDO 50% VI tPZH RL VO tPHZ 50% 0.5 V VEN 1 VDDI 2 VIN S 0 ISOLATION Figure 11. EN to Logic High VO Propagation Delay Test Circuit and Waveform VO VDDO S at 0, V O remain consistently low S at 1, V O remain consistently high S at 2, V O data same as VIN data VCM Figure 12. Common Mode Transient Immunity Test Circuit www.onsemi.com 8 NCID9211 APPLICATIONS INFORMATION Theory of Operation below the components, power plane below the ground plane, signal lines and power fill on top, and signal lines and ground fill at the bottom. The alternating polarities of the layers creates interplane capacitances that aids the bypass capacitors required for reliable operation at digital switching rates. In the layout with digital isolators, it is required that the isolated circuits have separate ground and power planes. The section below the device should be clear with no power, ground or signal traces. Maintain a gap equal to or greater than the specified minimum creepage clearance of the device package. NCID9211 is a dual−channel digital isolator that enables bi−directional communication between two isolated circuits. It uses off−chip ceramic capacitors that serve both as the isolation barrier and as the medium of transmission for signal switching using on−off keying (OOK) technique, illustrated in the single channel operational block diagram in Figure 13. At the transmitter side, the VIN input logic state is modulated with a high frequency carrier signal. The resulting signal is amplified and transmitted to the isolation barrier. The receiver side detects the barrier signal and demodulates it using an envelope detection technique. The output signal determines the VO output logic state when the output enable control EN is at high. When EN is at low, output VO is at high impedance state. VO is at default state low when the power supply at the transmitter side is turned off or the input VIN is disconnected. ISOLATION BARRIER TRANSMITTER VIN TX Amplif ier OOK Modulator RX Amplif ier Envelope Detec tor No Trace VDD1 Plane Signal Lines / GND2 Fill Figure 16. 4−Layer PCB for Digital Isolator For NCID9211, it is highly advised to connect at least a pair of low ESR supply bypass capacitors, placed within 2mm from the power supply pins 1 and 16 and ground pins 2 and 15. Recommended values are 1 mF and 0.1 mF, respectively. Place them between the VDD pins of the device and the via to the power planes, with the higher frequency, lower value capacitor closer to the device pins. Directly connect the device ground pins 1, 8, 9 and 15 by via to their corresponding ground planes. OFF− CHIP CAPACITORS OSC VDD2 Plane Signal Lines / GND1 Fill VO IO GND2 Plane GND1 Plane EN RECEIVER Signal Lines / VDD2 Fill Signal Lines / VDD1 Fill Figure 13. Operational Block Diagram of Single Channel VIN ISOLATION BARRIER VDD1 GND1 1μF 0.1μF 0.1μF 1μF VDD2 GND2 VO Figure 14. On−Off Keying Modulation Signals OFF− CHIP CAPACITIVE ISOLATION BARRIER EN1 VOA + VTX − RX IO GND1 VINA IO TX Figure 17. Placement of Bypass Capacitors OSC VINB IO TX + VTX − RX GND2 EN2 Over Temperature Detection VOB IO NCID9211 has a built−in Over Temperature Detection (OTD) feature that protects the IC from thermal damage. The output pins will automatically switch to default state when the ambient temperature exceeds the maximum junction temperature at threshold of approximately 160°C. The device will return to normal operation when the temperature decreases approximately 20°C below the OTD threshold. OSC Figure 15. NCID9211 Operational Block Diagram Layout Recommendation Layout of the digital circuits relies on good suppression of unwanted noise and electromagnetic interference. It is recommended to use 4−layer FR4 PCB, with ground plane www.onsemi.com 9 NCID9211 ORDERING INFORMATION Grade Package Shipping† NCID9211 Industrial SOIC16 W 50 Units / Tube NCID9211R2 Industrial SOIC16 W 750 Units / Tape & Reel NCIV9211* (pending) Automotive SOIC16 W 50 Units / Tube NCIV9211R2* (pending) Automotive SOIC16 W 750 Units / Tape & Reel Part Number †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. *NCIV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. www.onsemi.com 10 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC16 W CASE 751EN ISSUE A GENERIC MARKING DIAGRAM* AWLYWW XXXXXXXXXX XXXXXXXXXX DOCUMENT NUMBER: DESCRIPTION: XXXX A WL Y WW 98AON13751G SOIC16 W DATE 24 AUG 2021 = Specific Device Code *This information is generic. Please refer to = Assembly Location device data sheet for actual part marking. = Wafer Lot Pb−Free indicator, “G” or microdot “G”, may = Year or may not be present. Some products may = Work Week not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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Buyer is responsible for its products and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. 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