Power Factor Controller,
High-Efficiency,
Enhanced for Lighting
NCL2801
The 8−pin PFC controller NCL2801 is designed to drive PFC boost
stages. It is based on an innovative Valley Count Frequency
Fold−back (VCFF) method. The circuit classically operates in
Critical conduction Mode (CrM) for high load values. When the load
decreases a Discontinuous Conduction Mode DCM is forced by
forcing a dead time which, by construction corresponds to a fixed
number of valleys. The lower the output power, the higher the number
of valleys corresponding to the dead time. After DCM works down to
6th valley switching and if the load continues to decrease, a dead time
is continuously added to the 6th valley. The end of additional dead time
is synchronized with the drain voltage valley. The maximum
switching period is limited to 36.5 ms. VCFF maximizes the
efficiency during DCM and light load. In particular, the stand−by
losses are reduced to a minimum. Like in FCCrM controllers, internal
circuitry allows near−unity power factor even when the switching
frequency is reduced. Housed in a SO−8 package, the circuit also
incorporates the features necessary for robust and compact PFC
stages, with few external components.
General Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Near−Unity Power Factor
Critical Conduction Mode (CrM)
Valley Count Frequency Fold−Back (VCFF)
Peak Current Control Mode to Maintain a Proper Current Shaping in
VCFF Mode
Fast Line / Load Transient Compensation (Dynamic Response
Enhancer) Option
Brown−out Detection
Two−level Line Feed−Forward (HL&LL)
Valley Turn−on (No Valley Hoping by Construction)
High Drive Capability: −500 mA / +800 mA
VCC Range: from 10.5 V to 27 V
Low Start−up Consumption for :
[*C*]& [*D*] Option: Low VCC Start−up Level (12.5 V)
[*A*]& [*B*] Option: High VCC Start−up Level (17.0 V)
[*E*]& [*F*] Option: High VCC Start−up Level (10.5 V)
This is a Pb−Free Device
© Semiconductor Components Industries, LLC, 2018
September, 2019 − Rev. 3
1
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8
1
SOIC−8
CASE 751
MARKING DIAGRAMS
8
L2801abc
ALYW
G
1
L2801abc = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
PIN CONNECTIONS
FB 1
VCC
VCTRL
DRV
MULT
GND
CS
ZCD
(Top Views)
ORDERING INFORMATION
See detailed ordering and shipping information on page 25 of
this data sheet.
Publication Order Number:
NCL2801/D
NCL2801
Safety Features
•
•
•
•
•
•
•
•
Typical Applications
•
•
•
•
Thermal Shutdown
Non−latching, Over−Voltage Protection (3 Prog Levels)
Over Current Limitation
Low Duty−Cycle Operation if the Bypass Diode is
Shorted
Open Ground Pin Fault Monitoring
Pin CS shorted to GND or open Monitoring
Pin ZCD open tested before controller starts
Controller not allowed to start if MULT pin is left open
PC Power Supplies
Lighting Ballasts (LED, Fluorescent)
Flat TV
All Off Line Appliances Requiring Power Factor
Correction
Several product configurations coded with three letters
(L1,L2, L3) marked on the package will be available
Table 1. NCL2801 1ST LETTER CODING OF PRODUCT VERSIONS
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
L1
Soft OVP (% of VREF)
Fast OVP (% of VREF)
A
Disabled
112.5
B
Disabled
110.0
C (default)
105.0
107.0
1. The NCL2801 SO8 package is marked L1L2L3
Table 2. NCL2801 2ND LETTER CODING OF PRODUCT VERSIONS
L2
VCC Startup Level (V)
DRE (After Startup)
DRE (During Startup)
A
17.0
NO
YES
B
17.0
YES
YES
C
12.5
NO
YES
D (default)
12.5
YES
YES
E
10.5
NO
YES
F
10.5
YES
YES
2. The NCL2801 SO8 package is marked L1L2L3
Table 3. NCL2801 3RD LETTER CODING OF PRODUCT VERSIONS
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
L3
Brown−in & Brown−out
Line Range Detection w/ 2−level Line Feed−Forward
A (default)
YES
YES
B
YES
NO
C
NO
YES
D
NO
NO
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NCL2801
D2
Vin
IL
L
Np
D1
Naux
RZCD
AC line
V bulk
Rfb1
VCC
Rmult1
Cbulk
Cin
EMI
Filter
FB
VCTRL
MULT
CS
Rmult2
Rz
Cp
1
8
2
7
3
6
4
5
DRV
GND
Q1
Rfb2
ZCD
RCS
Cz
LOAD
VCC
Rsense
Figure 1. NCL2801 Application Schematic
Table 4. NCL2801 3RD LETTER CODING OF PRODUCT VERSIONS
Pin
Number
Name
Function
FB
This pin receives a portion of the PFC output voltage for the regulation and the optional Dynamic Response
Enhancer (DRE) that drastically speeds−up the loop response when the output voltage drops below 95.5 % of
the desired output level.
FB pin voltage VFB is also the input signal for the (non−latching) Over−Voltage (OVP). The UVP comparator
prevents operation as long as FB pin voltage is lower than VUVPH internal voltage reference. A SOFTOVP comparator gradually reduces the duty−ratio when FB pin voltage
exceeds 105% of VREF (option dependent). If despite of this, the output voltage still increases, the driver is immediately disabled by fast OVP if the output voltage exceeds x% of the desired level (option dependent)..
A 250−nA sink current is built−in to trigger the UVP protection and disable the part if the feedback pin is
accidently left open.
2
VCTRL
The error amplifier output is available on this pin. The network connected between this pin and ground adjusts
the regulation loop bandwidth that is typically set below 20 Hz to achieve high Power Factor ratios.
VCTRL pin is internally pulled down when the circuit is off so that when it starts operation, the power increases
slowly to provide a soft−start function.
VCTRL pin must not be controlled or pulled down externally.
Pulled to GND if BO and at startup (pseudo−soft start). Just a switch.
3
MULT
Multiplier input pin. This pin receives a scaled down rectified mains voltage by the means of a resistor voltage
divider connected between Vin and GND.
.
1
This pin senses the MOSFET current in order to end the on−time when the current reaches the control value or
the maximum current limit.
Just before startup, the value of the resistance between CS pin and GND pin is sensed for determining the
VCTRL value of the CrM to DCM threshold.
4
CS
5
ZCD
This pin uses the auxiliary winding voltage to determine the inductor current zero crossing.
6
GND
Connect this pin to the PFC stage ground.
7
DRV
The high−current capability of the totem pole gate drive (−0.5/+0.8 A) makes it suitable to effectively drive high
gate charge power MOSFETs.
8
VCC
This pin is the positive supply of the IC. The circuit starts to operate when VCC exceeds 17.0 V ([*A*] & [*B*]
Versions) or 12.5 V ([*C*] & [*D*] Versions) or 10.5 V ([*E*] & [*F*] Options) and turns off when VCC goes below
10.0 V (typ) for [*C*] & [*D*] Options and below 9.0 V (typ) for [*A*] & [*B*] &[*E*] & [*F*] Options. After start−up,
the operating range is 10.0 V (or 9 V depending on option) up to 27 V.
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NCL2801
Table 5. MAXIMUM RATINGS TABLE
Symbol
Pin
Rating
Value
Unit
FB
1
Feedback Pin
−0.3, +9
V
VCTRL
2
VCONTROL pin
−0.3, Vctrl,max
(Note 3)
V
MULT
3
Multiplier Input pin
−0.3, +9
V
CS
4
CS Pin
−0.3, +9
V
ZCD
5
ZCD Pin
−0.3, VCC+0.3
V
DRV
7
Driver Voltage
Driver Current
−0.3, VDRV (Note 3)
−500, +800
V
mA
VCC
8
Power Supply Input
−0.3, + 27
V
PD
Rqja
Power Dissipation and Thermal Characteristics
Maximum Power Dissipation @ TA=70°C
Thermal Resistance Junction to Air
300
180
mW
°C/W
TJ
Operating Junction Temperature Range
−40 to + 125
°C
TJ,max
Maximum Junction Temperature
150
°C
TS,max
Storage Temperature Range
−65 to 150
°C
TL,max
Lead Temperature (Soldering, 10s)
300
°C
MSL
Moisture Sensitivity Level
1
−
ESD Capability, HBM model (Note 4)
> 2000
V
ESD Capability, Machine Model (Note 4)
> 200
V
ESD,CDM
1000
V
3. “Vctrl,max” is the VCTRL pin clamp voltage. “VDRV” is the DRV clamp voltage (VDRVhigh) if VCC is higher than (VDRVhigh). “VDRV” is VCC
otherwise.
4. This device(s) contains ESD protection and exceeds the following tests: Human Body Model 2000 V per JEDEC Standard JESD22−A114E
Machine Model Method 200 V per JEDEC Standard JESD22−A115−A
5. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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NCL2801
Table 6. ELECTRICAL CHARACTERISTICS (Conditions: VCC = 18 V, TJ = −40°C to +125°C, unless otherwise specified) (Note 6)
Symbol
Rating
Min
Typ
Max
Unit
VCC,on
Start−Up Threshold, VCC increasing:
[*E*] & [*F*] Versions
[*C*] & [*D*] Versions
[*A*] & [*B*] Versions
9.75
11.6
15.6
10.5
12.50
16.7
11.25
13.4
18.00
V
V
V
VCC,off
Minimum Operating Voltage, VCC falling
[*C*] & [*D*] Versions
[*A*] & [*B*] & [*E*] & [*F*]
9.3
8.4
10.0
9.0
10.7
9.6
V
V
6.50
7.2
7.80
V
VCC,hyst
Hysteresis (VCC ,on − VCC ,off)
[*E*] & [*F*] Versions
[*C*] & [*D*] Versions
[*A*] & [*B*] Versions
0.75
1.25
6.00
1.6
2.5
7.7
3.0
3.75
10
V
V
V
ICC,start
Start−Up Current, VCC = 9.4 V, below startup voltage
0
10
60
mA
ICC,op1
Operating Consumption, no switching.
0
0.4
1.00
mA
ICC,op2
Operating Consumption, 50−kHz switching, no load on DRV pin
1.0
2.00
3.00
mA
tR
Output voltage rise−time @ CL = 1 nF, 10−90% of output signal
15
30
90
ns
tF
Output voltage fall−time @ CL = 1 nF, 10−90% of output signal
10
20
50
ns
ROH
Source resistance @ 200 mV under High VCC
4
10
20
W
ROL
Sink resistance @ 200mV above Low VCC
2
7
15
W
VDRV,low
DRV pin level for VCC = VCC ,off + 200 mV
(10−kW resistor between DRV and GND)
[*A*] & [*B*] & [*E*] & [*F*]
[*C*] & [*D*] Versions
8.6
9.6
9.2
10
10
11
V
V
VDRV,high
DRV pin level at VCC = 27 V (RL = 33 kW & CL = 1 nF)
10
12
14
V
VDRV,L
Maximum DRV voltage while forcing zero at DRV pin and injecting 10 mA
into DRV pin @ VCC = 12 V
0
100
200
mV
VREF
Feedback Voltage Reference
2.45
2.50
2.55
V
IEA
Error Amplifier Current Capability (source and sink)
15
20
25
mA
GEA
Error Amplifier Gain
110
200
290
mS
Vctrl,max Vctrl,min
VCTRL pin Voltage (Vctrl ):
− @ VFB = 2 V (OTA is sourcing 20 mA)
− @ VFB = 3 V (OTA is sinking 20 mA)
4.4
0.4
4.5
0.5
4.6
0.6
V
VCS_OCP(th)
Current Sense Voltage Reference for option w/o line level detection
[**B]&[**D] Options
At tLEB,OCP
0.97
1.07
1.19
V
VCS_OVS(th)
Current Sense Overstress Voltage Reference for option w/o line level
detection
[**B]&[**D] Options
At tLEB,OVS
1.45
1.60
1.78
V
VCS_OCP_LL(th)
Current Sense Voltage Reference when Low Line is detected
[**A]&[**C] Options
At tLEB,OCP
0.97
1.07
1.19
V
VCS_OVS_LL(th)
Current Sense Overstress Voltage Reference when Low Line is detected
[**A]&[**C] Options
At tLEB,OVS
1.45
1.60
1.78
V
START−UP AND SUPPLY CIRCUIT
Voltage at which IC completely restarts
ICC drops to ~ ICC,start
VCC,rst
(Min and Max values are guaranteed by functional testing)
GATE DRIVE
REGULATION BLOCK
CURRENT SENSE BLOCK
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NCL2801
Table 6. ELECTRICAL CHARACTERISTICS (Conditions: VCC = 18 V, TJ = −40°C to +125°C, unless otherwise specified) (Note 6)
Symbol
Rating
Min
Typ
Max
Unit
VCS_OCP_HL(th)
Current Sense Voltage Reference when High Line is detected
[**A]&[**C] Options
At tLEB,OCP**
0.53
0.58
0.66
V
VCS_OVS_HL(th)
Current Sense Overstress Voltage Reference when High Line is detected
[**A]&[**C] Options
At tLEB,OVS
0.79
0.87
0.97
V
tLEB,OCP
Leading edge Blanking Time for current control
125
200
275
ns
tLEB,OVS
Leading edge Blanking Time for Overstress
50
100
150
ns
tOCP
Over−Current Protection Delay from VCS >VCS(th) to
DRV low
Test: VCS > VCS + 100 mV
10
40
200
ns
tWDG(OS)
Watch Dog Timer in “OverStress” Situation
400
800
1200
ms
ZERO CURRENT DETECTION BLOCK
VCL(pos)
ZCD positive clamp (VCC = 12 V, IZCD = 5 mA)
12.6
12.9
13.2
V
VZCD(th)H
Zero Current Detection, VZCD rising
675
750
825
mV
VZCD(th)L
Zero Current Detection, VZCD falling
200
250
300
mV
VZCD(hyst)
Hysteresis of the Zero Current Detection Comparator
375
500
625
mV
IZCD,bias
ZCD pin input leakage current
0
250
500
nA
tZCD
(VZCD < VZCD (th )L ) to (DRV high)
20
80
200
ns
tSYNC
Minimum ZCD Pulse Width (Guaranteed by Design)
−
60
−
ns
tWDG
Watch Dog Timer
If no ZCD detected
80
200
320
ms
IZCD,pu
Pull−up current source to detect ZCD open pin
At startup only
0.85
1
1.15
mA
VREF,ZCD,open
Voltage reference to test ZCD pin short during startup
150
200
250
mV
Kmult
Multiplier Gain (Note 2) for option w/o line level detection
[**B]&[**D] Options
0.34
0.38
0.42
1/V
Kmult,HL
Multiplier Gain (Note 2) when High Line is detected
[**A]&[**C] Options
0.22
0.24
0.28
1/V
Kmult,LL
Multiplier Gain (Note 2) when Low Line is detected
[**A]&[**C] Options
0.72
0.80
0.88
1/V
Kmult,Ratio
Ration between Kmult,LL and Kmult,HL
[**A]&[**C] Options
2.9
3.3
3.7
Koffset
Koffset.Vton voltage added at the multiplier output
[**A]&[**C] Options (w/ Line Detection)
0.10
0.140
0.20
Koffset_nld
Koffset.Vton voltage added at the multiplier output
[**B]&[**D] Options (w/o Line Detection)
0.040
0.075
0.12
Imult_pd
Current pull−down on Mult pin
200
280
350
nA
Vmult_max
Maximum MULT pin voltage
Controller disabled if MULT pin voltage goes above this threshold
2.88
3.2
3.52
V
tON,max,A,2
@ VCTRL = 4.50 V
26
30
36
ms
tON,max,A,1
@ VCTRL = 0.55 V
3.6
5
6.9
ms
MULTIPLIER
MAXIMUM ON−TIME
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NCL2801
Table 6. ELECTRICAL CHARACTERISTICS (Conditions: VCC = 18 V, TJ = −40°C to +125°C, unless otherwise specified) (Note 6)
Symbol
Rating
Min
Typ
Max
Unit
RCS VALUE IDENTIFICATION REFERENCE VOLTAGES
IRCS
Internal current sourced by CS pin into a 1% RCS resistor just before the
startup generates a voltage drop VCS
0.96
1.0
1.04
mA
VRCS,REF,1
Internal voltage reference for identifying the RCS resistor value
CS pin is said shorted to GND if VCS < VRCS,REF,1
20
50
100
mV
VRCS,REF,2
Internal voltage reference for identifying the RCS resistor value
RCS = 150 W if RCS,REF,1 < VCS < VRCS,REF,2
180
230
280
mV
VRCS,REF,3
Internal voltage reference for identifying the RCS resistor value
RCS = 330 W if VRCS,REF,2 < VCS < VRCS,REF,3
400
460
530
mV
VRCS,REF,4
Internal voltage reference for identifying the RCS resistor value
RCS = 620 W if VRCS,REF,3 < VCS < VRCS,REF,4
720
790
880
mV
VRCS,REF,5
Internal voltage reference for identifying the RCS resistor value
RCS = 1000 W if VRCS,REF,4 < VCS < VRCS,REF,5
CS pin open if VCS >VRCS,REF,5
RCS open do not allow the controller to start
1190
1300
1400
mV
FREQUENCY FOLDBACK THRESHOLDS & HYSTERESIS
VCTRL,th,12,1000
VCTRL threshold for valley1 to valley2 forcing @RCS = 1000 W
1.971
2.19
2.409
V
VCTRL,th,23, 1000
VCTRL threshold for valley2 to valley3 forcing @RCS = 1000 W
1.647
1.83
2.013
V
VCTRL,th,34, 1000
VCTRL threshold for valley3 to valley4 forcing @RCS = 1000 W
1.332
1.48
1.628
V
VCTRL,th,45, 1000
VCTRL threshold for valley4 to valley5 forcing @RCS = 1000 W
1.008
1.12
1.232
V
VCTRL,th,56, 1000
VCTRL threshold for valley5 to valley6 forcing @RCS = 1000 W
0.693
0.77
0.847
V
VCTRL,th,65, 1000
VCTRL threshold for valley6 to valley5 forcing @RCS = 1000 W
1.008
1.12
1.232
V
VCTRL,th,54, 1000
VCTRL threshold for valley5 to valley4 forcing @RCS = 1000 W
1.332
1.48
1.628
V
VCTRL,th,43, 1000
VCTRL threshold for valley4 to valley3 forcing @RCS = 1000 W
1.647
1.83
2.013
V
VCTRL,th,32, 1000
VCTRL threshold for valley3 to valley2 forcing @RCS = 1000 W
1.971
2.19
2.409
V
VCTRL,th,21, 1000
VCTRL threshold for valley2 to valley1 forcing @RCS = 1000 W
2.286
2.54
2.794
V
VCTRL,hyst, 1000
VCTRL hysteresis when changing forced valley @RCS = 1000 W
300
356
420
mV
VCTRL,th,12,620
VCTRL threshold for valley1 to valley2 forcing @RCS = 620 W
1.647
1.830
2.013
V
VCTRL,th,23, 620
VCTRL threshold for valley2 to valley3 forcing @RCS = 620 W
1.413
1.570
1.727
V
VCTRL,th,34, 620
VCTRL threshold for valley3 to valley4 forcing @RCS = 620 W
1.170
1.300
1.430
V
VCTRL,th,45, 620
VCTRL threshold for valley4 to valley5 forcing @RCS = 620 W
0.927
1.030
1.133
V
VCTRL,th,56, 620
VCTRL threshold for valley5 to valley6 forcing @RCS = 620 W
0.693
0.770
0.847
V
VCTRL,th,65, 620
VCTRL threshold for valley6 to valley5 forcing @RCS = 620 W
0.927
1.030
1.133
V
VCTRL,th,54, 620
VCTRL threshold for valley5 to valley4 forcing @RCS = 620 W
1.170
1.300
1.430
V
VCTRL,th,43, 620
VCTRL threshold for valley4 to valley3 forcing @RCS = 620 W
1.413
1.570
1.727
V
VCTRL,th,32, 620
VCTRL threshold for valley3 to valley2 forcing @RCS = 620 W
1.647
1.830
2.013
V
VCTRL,th,21, 620
VCTRL threshold for valley2 to valley1 forcing @RCS = 620 W
1.890
2.100
2.310
V
VCTRL,hyst, 620
VCTRL hysteresis when changing forced valley @RCS = 620 W
200
267
320
mV
VCTRL,th,12, 330
VCTRL threshold for valley1 to valley2 forcing @RCS = 330 W
1.332
1.480
1.628
V
VCTRL,th,23, 330
VCTRL threshold for valley2 to valley3 forcing @RCS = 330 W
1.170
1.300
1.430
V
VCTRL,th,34, 330
VCTRL threshold for valley3 to valley4 forcing @RCS = 330 W
1.008
1.120
1.232
V
VCTRL,th,45, 330
VCTRL threshold for valley4 to valley5 forcing @RCS = 330 W
0.846
0.940
1.034
V
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NCL2801
Table 6. ELECTRICAL CHARACTERISTICS (Conditions: VCC = 18 V, TJ = −40°C to +125°C, unless otherwise specified) (Note 6)
Symbol
Rating
Min
Typ
Max
Unit
VCTRL,th,56, 330
VCTRL threshold for valley5 to valley6 forcing @RCS = 330 W
0.693
0.770
0.847
V
VCTRL,th,65, 330
VCTRL threshold for valley6 to valley5 forcing @RCS = 330 W
0.846
0.940
1.034
V
VCTRL,th,54, 330
VCTRL threshold for valley5 to valley4 forcing @RCS = 330 W
1.008
1.120
1.232
V
VCTRL,th,43, 330
VCTRL threshold for valley4 to valley3 forcing @RCS = 330 W
1.170
1.300
1.430
V
VCTRL,th,32, 330
VCTRL threshold for valley3 to valley2 forcing @RCS = 330 W
1.332
1.480
1.628
V
VCTRL,th,21, 330
VCTRL threshold for valley2 to valley1 forcing @RCS = 330 W
1.494
1.660
1.826
V
VCTRL,hyst, 330
VCTRL hysteresis when changing forced valley @RCS = 330 W
120
178
230
mV
VCTRL,th,12,150
VCTRL threshold for valley1 to valley2 forcing @RCS = 150 W
1.008
1.120
1.232
V
VCTRL,th,23, 150
VCTRL threshold for valley2 to valley3 forcing @RCS = 150 W
0.927
1.030
1.133
V
VCTRL,th,34, 150
VCTRL threshold for valley3 to valley4 forcing @RCS = 150 W
0.846
0.940
1.034
V
VCTRL,th,45, 150
VCTRL threshold for valley4 to valley5 forcing @RCS = 150 W
0.774
0.860
0.946
V
VCTRL,th,56, 150
VCTRL threshold for valley5 to valley6 forcing @RCS = 150 W
0.693
0.770
0.847
V
VCTRL,th,65, 150
VCTRL threshold for valley6 to valley5 forcing @RCS = 150 W
0.774
0.860
0.946
V
VCTRL,th,54, 150
VCTRL threshold for valley5 to valley4 forcing @RCS = 150 W
0.846
0.940
1.034
V
VCTRL,th,43, 150
VCTRL threshold for valley4 to valley3 forcing @RCS = 150 W
0.927
1.030
1.133
V
VCTRL,th,32, 150
VCTRL threshold for valley3 to valley2 forcing @RCS = 150 W
1.008
1.120
1.232
V
VCTRL,th,21, 150
VCTRL threshold for valley2 to valley1 forcing @RCS = 150 W
1.089
1.210
1.331
V
VCTRL,hyst, 150
VCTRL hysteresis when changing forced valley @RCS = 150 W
35
89
135
mV
14
0
20
0.1
−
0.4
ms
ms
SWITCHING CYCLE DEAD TIME
Dead time added after 6th valley
Vctrl = 0.50 V
Vctrl = 0.77 V
tADT
FEED−BACK OVER AND UNDER−VOLTAGE PROTECTIONS (OVP)
RsoftOVP,C
Ratio (Soft OVP Threshold, VFB rising) over VREF (Options [C**])
103.5
105
106.5
%
RsoftOVP(HYST)
Ratio (Soft OVP Hysteresis) over VREF .
0.8
1.3
3.2
%
RfastOVP,A
Ratio (Fast OVP Threshold, VFB rising) over VREF (Options [A**])
108.5
112.5
116.5
%
RfastOVP,B
Ratio (Fast OVP Threshold, VFB rising) over VREF (Option [B**])
106.1
110
113.9
%
RfastOVP,C
Ratio (Fast OVP Threshold, VFB rising) over VREF (Option [C**])
103.2
107
110.8
%
RfastOVP(HYST)
Ratio (Fast OVP Hysteresis) over VREF
3.0
4.0
5.7
%
IB,FB
FB pin pull−down Current @ VFB = VOV P and VFB = VUVP
Pulls down the FB pin in case the pin is open (solder failure)
50
200
450
nA
DYNAMIC RESPONSE ENHANCER (DRE)
RDRE
Ratio (DRE Threshold, VFB falling) over VREF
94.0
95.7
97.5
%
RDRE(HYST)
Ratio (DRE Hysteresis) over VREF
0.8
2.0
3.0
%
IVCTRL,Startup
Current measured out of VCTRL pin (DRE current source
minus max OTA current)
@ VFB=1V (PFCOK=0 ⇔ Startup)
80
100
120
mA
IVCTRL,1,Steady
Current measured out of VCTRL pin (DRE current source
minus max OTA current )
@ VFB=1V (PFCOK=1 ⇔ Steady State)
[*B*], [*D*], [*F*] Product Options
160
200
240
mA
UNDER VOLTAGE PROTECTION / DISABLE
VUVPH
UVP Threshold, VFB increasing
380
450
520
mV
VUVPL
UVP Threshold, VFB decreasing
150
200
250
mV
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8
NCL2801
Table 6. ELECTRICAL CHARACTERISTICS (Conditions: VCC = 18 V, TJ = −40°C to +125°C, unless otherwise specified) (Note 6)
Symbol
Rating
Min
Typ
Max
Unit
VUVP(HYST)
UVP Hysteresis
200
250
300
mV
BROWN−OUT PROTECTION AND LINE FEED FORWARD
VBOH
Brown−In Threshold, Vmains increasing
Note: Vline,BOH,rms = 74, 80, 87 V assuming 1/Km = 144
725
787
860
mV
VBOL
Brown−Out Threshold, Vmains decreasing
Note: Vline,BOL,rms = 64, 72, 78 V assuming 1/Km = 144
634
709
770
mV
VBO(HYST)
Brown−Out Comparator Hysteresis
50
75
130
mV
tBO(blank)
Brown−Out Blanking Time
36
50
67
ms
IVCTRL(BO)
VCTRL pin sink current during BO condition
20
30
42
mA
VHL
Comparator Threshold for Line Range Detection VMULT rising
Note: Vline,HL,rms = 157,165,174 V assuming 1/Km = 144
1.543
1.625
1.706
V
VLL
Comparator Threshold for Line Range Detection VMULT falling
Note: Vline,HL,rms = 137,145,152 V assuming 1/Km = 144
1.350
1.422
1.493
V
VHL(hyst)
Comparator Hysteresis for Line Range Detection
37
218
300
mV
tHL(blank)
Blanking Time for Line Range Detection
(must stay below VLLfor 25 ms before changing to LL)
13
25
43
ms
TLIMIT
Thermal Shutdown Threshold
150
−
−
°C
HTEMP
Thermal Shutdown Hysteresis
−
50
−
°C
THERMAL SHUTDOWN
6. The above specification gives the targeted values of the parameters. The final specification will be available once the complete circuit
characterization has been performed.
7. In CrM mode, Gmult = VCS(th)/[(VCTRL−0.5)*(1.5/4.0)*VMULT], VCS(th) is the CS pin voltage threshold at which DRV pin goes low (end of
on−time). Koffset is set to zero in test mode, otherwise the formula is more complex.
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9
NCL2801
VREF,LLINE
MULT
OTA
SOURCING
LINE & BO
MANAGMENT
FB
VREF
VREF,BONOK
PFCOK
FFTH
FFTH
SENSE
OFF
BONOK
VREGUL
VCTRL
MANAGMENT
FB
MANAGMENT
DRE
STATICOVP
VREF,DRE
V REF,UVP
UVP
VREF,OVS
SOFTOVP
VREF,SOFT_OVP
FASTOVP
VREF,FAST_OVP
OVERSTRESS
DRV
CURRENT
SENSE
V REF
VREF,XXXX
OCP
ISENSE
THERMAL
SHUTDOWN
VREF,OCP
VCC
VDD
TSD
BONOK
UVP
DRV
ZERO
CROSSING
DETECTION
OFF
FAULT
MANAGMENT
ZCD
STATICOVP
VREF,VCC
UVLO
OFF
STATICOVP
STOP
FASTOVP
SOURCING
PFCOK
OCP
Q
S
OVERSTRESS
R
OFF
LLINE
BONOK
MULT
ISENSE
ON TIME
MANAGMENT
TONMX
RST
DRV
FFTH
VREGUL
DRV
ZCD
OVERSTRESS
PFCOK
UVLO
CLK & DT
MANAGMENT
VCC
CLK
VTON
S
CLK
DT
VREGUL
DT
SOFTOVP
Q
R
Vton
Processing
Circuitry
VTON
All RS latches are
reset dominat
Figure 2. NCL2801 Block Diagram (SOURCING Flag is High When OTA Sources
Current, if Sourcing Less Than 1nA SOURCING Flag Goes Low)
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10
Output
Buffer
NCL2801
DETAILED OPERATING DESCRIPTION
Introduction
NCL2801 is designed for working with LED Lighting
applications coping with high ripple voltage on bulk
capacitor and providing optimized line current THD and
good efficiency. In addition, it incorporates protection
features for robust operation. More generally, NCL2801 is
ideal in systems where cost−effectiveness, reliability, low
line current THD, low stand−by power and high efficiency
are key requirements:
• Valley Count Frequency Fold−back: NCL2801 is
designed to drive PFC boost stages in so−called Valley
Count Frequency Fold−back (VCFF). In high load
current condition, the circuit classically operates in
Critical conduction Mode (CrM) also called 1st valley
switching. When output power is decreasing, if a
threshold is reached (determined by sensing the CS pin
impedance during initial power up), a dead time based
on a number of valleys is added. The number of valleys
will increase, each time a dead time window (based on
VCTRL value) is entered. By construction, this counting
process will avoid valley hoping during the mains
voltage period. If the output power continues
decreasing and the 6th valley is reached, extra “analog”
dead time will be added based on a voltage ramp (see
Figure 4). On−time will be synchronized with a valley.
A timer will clamp the total switching period to not
exceed 36.5 ms (the switching frequency will never go
under about 27.4 kHz). The switching frequency
depends on output voltage, input voltage, and boost
inductor value, and increases as the load power
increases. Hysteresis and added to the VCTRL control
windows to avoid valley hopping during steady state
conditions. VCFF maximizes the efficiency at both
nominal and light load. Similarly to FCCrM
controllers, an internal circuitry allows near−unity
power factor even when the switching frequency is
reduced.
• Low Start−up Current: The start−up consumption of the
circuit is minimized to allow the use of high impedance
start−up resistors to precharge the VCC capacitor. Also,
the minimum value of the UVLO hysteresis is 6 V to
avoid the need for large VCC capacitors and help
shorten the start−up time without the need for excessive
dissipation in the start−up circuit. The [*C*] & [*D*]
version is preferred in applications where the circuit is
fed by an external power source (from an auxiliary
power supply or from a downstream converter). After
start−up, the high VCC maximum rating allows a large
operating range from 10.5 V up to 27 V.
• Fast Line / Load Transient Compensation (Dynamic
Response Enhancer): Since PFC stages exhibit low loop
bandwidth, abrupt changes in the load or input voltage
(e.g. at start−up) may cause excessive over or
•
under−shoot. This circuit limits possible deviations
from the regulation level as follows:
− NCL2801 linearly decays the power delivery to zero
when the output voltage exceeds the soft OVP limit
(105% of VREF) for option [C**]). Soft OVP feature
is disabled on options [A**] &[B**]. If this soft
OVP is too smooth and the output continues to rise,
the circuit immediately (priority to Fast OVP)
interrupts the power delivery when the output
voltage is 112.5 % above its desired level (Fast
OVP) for options [A**]. Options [B**] & [C**] are
providing lower Fast OVP thresholds. Fast OVP
threshold is higher than Soft OVP threshold for
option [C**].
− While disabled on options [*A*], [*C*] and [*E*]
after startup time, NCL2801 has a DRE (Dynamic
Response Enhancer) circuitry on options [*B*],
[*D*]&[*F*] which dramatically speeds−up the
regulation loop when the output voltage goes below
95.5 % of its regulation level. The DRE function is
enabled only after the PFC stage has started−up to
allow normal soft−start operation to occur. For all
the product options, the DRE is active during the
start−up phase to accelerate the start−up (VCTRL
pin voltage is brought at its higher value by the by
half of the 200−mA DRE current source which
charges the capacitors of the compensation network)
Soft−OVP / Fast−OVP ( Over Voltage Protection)
There are cases (for example during an high−load to
low−load rapid transition) were the bulk capacitor
voltage goes up very rapidly above the voltage
regulation level triggering Over−Voltage protection.
When the bulk capacitor voltage Vbulk reaches typically
105% of its nominal value, the Soft−OVP protection is
triggered, causing the duty−ratio to decrease gradually
down to zero. As a consequence, Vbulk decreases and
when Vbulk reaches the low level of Soft−OVP
threshold (typically 103% of nominal Vbulk) the
protection is released and the voltage regulation loop
takes−over .If Vbulk rises faster and reaches the
Fast−OVP threshold (typically 107% of nominal
Vbulk), the switching is instantaneously stop (DRV
signal is disabled). As a consequence, Vbulk decreases
and when the low level of Fast−OVP threshold is
reached (typically 103% of nominal Vbulk) the
protection is released and the voltage regulation loop
takes−over. Soft−OVP has only one level and can be
disabled dependent on product option. Three Fast_OVP
levels are available by product options : typically 107,
110 and 112% of nominal Vbulk. The 112% option is
well suited for applications using a low value bulk
capacitor were the two−times mains frequency Vbulk
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11
NCL2801
•
•
ripple voltage is high (in this case Soft−OVP is
disabled)
Safety Protections: Permanently monitoring the input
and output voltages, the MOSFET current and the die
temperature to protect the system from possible
over−stress makes the PFC stage extremely robust and
reliable. In addition to the OVP protection, the
following methods of protection are provided :
− Maximum Current Limit: The circuit senses the
MOSFET current and turns off the power switch if
the set current limit is exceeded. In addition, the
circuit enters a low duty−cycle operation mode when
the current reaches 150% of the current limit as a
result of the inductor saturation or a short of the
bypass diode.
− Thermal Shutdown: An internal thermal circuitry
disables the gate drive when the junction
temperature exceeds 150°C (typically). The circuit
resumes operation once the temperature drops below
approximately 100°C (50°C hysteresis).
Output Stage Totem Pole: NCL2801 incorporates a −0.5
A / +0.8 A gate driver to efficiently drive most TO220
or TO247 power MOSFETs.
−
−
NCL2801 Operation Modes
As mentioned, NCL2801 PFC controller implements a
Valley Count Frequency Fold−back (VCFF) where:
− The circuit operates in classical Critical conduction
Mode (CrM) when output power is high and VCTRL
pin voltage greater than a threshold (VCTRL,th,12 for
VCTRL decreasing and VCTRL,th,21 for VCTRL
increasing) which value is determined by the value the
resistance RCS placed between CS pin and top of
Rsense which bottom is connected to GND (Rsense
being negligible versus RCS, it is the RCS value which
is sensed). RCS value is sensed just before the startup
phase (see Table 6).
− When the output power decreases the NCL2801
reduces the operating frequency by means of increasing
−
−
valley number count up to 6 valleys (the number of
valleys between end of inductor demagnetization and
power MOSFET turn−on determines the dead time
value). After counting is done, the power MOSFET
turns on at drain voltage valley. When 6th valley is
reached and VCTRL voltage stays under 0.77 V, an extra
“analog” dead time is added based on a voltage ramp
(see Figure 4). The added analog dead time tADT is
based on 0.77 V minus VCTRL value. tADT will be equal
to zero when (0.5 V−VCTRL) = 0 V and will increase
monotonically versus VCTRL decreases while VCTRL is
under the 0.77 V threshold corresponding to
VCTRL,th,56. The analog dead time added tADT will
equal typically 20 ms when VCTRL=0.5 V.
When additional “analog” dead time is added, the
power MOSFET turn−on will, by default, be
synchronized with the falling edge of ZCD signal
(valley turn−on) and there will be possible, upon
request, of no valley synchronization for the on−time
start. The total dead−time (number of valleys and extra
dead−time) will not exceed 36.5 ms (A timer will be
clamping the dead time).
When the output power increases, the extra ”analog”
dead−time plus number of valleys dead time will
decrease ,according in which VCTRL pin voltage
window VCTRL pin voltage is, down to 1st valley
switching which is the CrM mode. The VCTRL pin
voltage window in which VCTRL pin voltage is will be
detected with comparators having an hysteresis to avoid
valley hopping due to VCTRL pin voltage ripple.
It will be the responsibility of the application designer
not to allow a VCTRL pin voltage ripple (at 2 times the
mains frequency) greater than the hysteresis of VCTRL
windows.
Valley hopping can lead to audible noise. The
NCL2801 avoids this activity by locking the operating
valley before turning on the MOSFET during steady
state operation.
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12
NCL2801
High Load Current
One valley (CrM )
Counting 1 valley
Low Load Current
More valleys (DCM)
Counting 3 valleys
Lower Load Current
More valleys (DCM)
Counting 6 valleys
tADT
Extremely Low Load Current
More valleys (DCM)
Plus analog dead time
Counting 6 valleys + t ADT
Figure 3. Valley Switching Operation in CrM and DCM Modes Seen Through Power MOSFET
Drain Voltage
means of counting the falling edges of the ZCD signal until
the counter reaches the number of valleys set by the window
in which the VCTRL pin voltage is (see Figure 4). The 3−bit
counter allows to work “Valley synchronized” up to 6
valleys. When the 6th valley is reached, and VCTRL is lower
than 0.770 V (VCTRL,th,56 = 0.770 V whatever frequency
foldback threshold setting), an additional analog dead time
will be added to the 6 valleys dead time and there will be
valley synchronization turn−on of the power MOSFET
(ADT_nosync = 0 by default) based on falling edge of ZCD
signal. The total dead−time (number of valleys and extra
analog dead−time) will not exceed 36.5 ms. As a result of this
timer the minimum switching frequency will not go under
27.4 kHz.
As illustrated in Figure 3, under high load conditions, the
boost stage is operating in CrM (only one valley is counted
before turning on the power MOSFET). The second
example shows a DCM state of operation where 3 valleys
have been counted before turning on the power MOSFET.
The third example shows a DCM state with lower output
power than the previous one where 5 valleys have been
counted before turning on the power MOSFET.The fourth
example shows how additional dead time is added after 6th
valley.
Valley Count Frequency Foldback (VCFF)
The turn−on of the power MOSFET is synchronized with
the valley of the power MOSFET drain voltage signal by the
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13
NCL2801
VCTRL
ZCD
DIGITAL
COMPARATOR
CMPOUT
UP
COUNTER
CLK
RST
DRV
Rz
Cz
Cp
RCS
VCTRL
CS
RCS
stored
R CS – VCTRL,th,ij
Lookup−Table
36.5 −us TIMER
RST
Rsense
DRV
VCTRL,max
VCTRL,th,12
DIGITAL NBR OF
VALLEYS CODING
VCTRL,th,21
VCTRL,th,23
VCTRL,th,32
VCTRL,th,34
VCTRL,th,43
VCTRL,th,45
VCTRL,th,54
VCTRL,th,56
VCTRL,th,65
0
ADT
IADT ADT_nosync
V2I
1/RADT
CMPOUT
D
Q
R
C ADT
VADT
ADT
DRV
ZCDbar
Figure 4. Valley Count Turn−on Block Diagram
The system relies on the counting of ZCD pulses to
determine dead−time periods. Should the ZCD pulses
diminish in voltage so that the event timing can’t be used, an
internal copy of the last reliable first−to−second falling edge
timing is substituted for the natural ZCD ring. The substitute
timing for a second falling edge is allowed 1us beyond the
recorded value before being asserted. The substitute timing
for the third falling edge and afterward is allowed 250 ns
beyond the recorded value before a ZCD pulse is asserted.
The NCL2801 PFC controller, depending on the
application power output which is correlated with the
This Valley Counting (VC) method avoids “valley
hoping” during the half period of mains voltage which is on
other designs, the cause of undesired mains current ringing
glitches due to the excitation of the input EMI filter by a dead
time discontinuity. The NCL2801 circuitry acts so that the
PFC controller transitions from the n valley to (n+1) valley
or from the n valley to (n−1) and stays on this valley number
is long as the VCTRL pin voltage stays in a the voltage
window corresponding to this valley number. If no
demagnetization is sensed the power MOSFET will be
turned−on after a watchdog timing of 200−ms.
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14
NCL2801
VCTRL pin voltage level, starts adding a dead−time tDT. The
system adjusts the on−time tON (by means of peak current
control) versus tDT (see Figure 5) and consequently the
tON
Iind
output power in order to ensure that the instantaneous mains
current remains in phase with the mains instantaneous
voltage (creating a unity PF).
t DEMAG
Ipeak ,max
0
Tsw
CLK
t DT
DT
DRV
time
Figure 5. NCL2801 Clock, Dead Time and tON waveforms
the maximum power is given just under to the maximum
VCTRL pin voltage VCTRL which is 4.5 V. Zero ouput
power will be supplied for VCTRL=0.5 V
For adjusting at which VCTRL value the transition from
CrM to DCM mode will happen, the resistance value
between CS pin and GND will be sensed before start−up and
its value stored digitally (see Figure 6). The sensed
resistance is equal to RCS plus Rsense, but because Rsense
value is much lower than RCS, it is the RCS value which will
be sensed.
This resistor sense will be done after VCC,on level is
reached and just before the controller starts switching in
order to avoid any noise perturbation the sensing (see Figure
6). The IRCS 1−mA (+/− 4%) current source, active when
RCS flag is high will generate a voltage drop through RCS
(+/−1%) resistor and this voltage drop will be compared to
internal voltage references to identify which is the RCS
resistor value and set the internal frequency foldback
settings.
When the output power is at the maximum available for
a given application and the inductor peak current limitation
is not triggering, VCTRL pin voltage (VCTRL), is above the
frequency foldback threshold (VCTRL,th,21) making the
controller to work in CrM mode. When output power
decreases VCTRL will go under the frequency foldback
threshold (VCTRL,th,12) and DCM mode will be forced by
adding dead time as explained before.
Adding dead−time will naturally decrease the switching
frequency, hence the FF (standing for Frequency Foldback)
which is part of the name VCFF.
The switching frequency in DCM mode is given by the
following equation..
F SW,DCM +
1
t DT ) t ON ) t DEMAG
(eq. 1)
The value of the external resistor placed between CS pin
and Rsense will determine the value of the VCTRL pin
voltage frequency foldback threshold.
CrM−DCM Threshold
For a given application, Rsense and Rmult divider ratio of
the resistors bridge connected to MULT pin are set such as
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15
NCL2801
Controller starts
switching
VCC_CMP_new
RCS
I RCS
RCS
(+/−1%)
VCC_CMP
Open_RCS
CS
RCS
VRCS,REF,5
VRCS,REF,4
D
VRCS,REF,3
Q
CLK Q b
VRCS,REF,2
VRCS,REF,1
RCS ó VCTRL ,th,12
Lookup−Table
RCS value
is stored
here
RCS
Figure 6. RCS Sensing Method And Schematic
Table 7.
RCS (W)
VCTRL,th,12 (V)
1000
2.19
620
1.83
330
1.48
150
1.12
gives the digital code used in Figure 6 corresponding to
the RCS resistor value which in turn will be used to set the
CrM to DCM threshold (when output power is decreasing).
There will be a different DCM to CrM threshold than CrM
to DCM making an hysteresis to avoid valley hopping (see
Table 7 and Figure 4).
During this RCS identification phase which main purpose
is to setting the the frequency foldback thresholds and
number of valley for dead time, if it happen that VCS voltage
is greater than VRCS,REF,5 an OPEN CS pin fault will be
triggered and latched disabling the startup of the controller,
the fault will be released if VCC pin voltage falls unders
VCC,rst. On the other hand if it happen that VCS voltage is
lower than VRCS,REF,1 a SHORT CS pin fault will be
triggered and latched disabling the startup of the controller,
the fault will be released if VCC pin voltage falls unders
VCC,rst.
DCMn−DCMn+1 and DCMn+1−DCMn Transition
Hysteresis
As explained before, DCM mode is driven by the number
of valleys counted before the power MOSFET turns on.
As shown in Figure 7, the forced number of valleys,
shown in the Y−axis, depends on 5 VCTRL pin voltage
windows,
the X−Axis representing the VCTRL pin voltage. In order
to avoid valley hopping due to VCTRL pin voltage ripple,
we have included an hysteresis. We can clearly see in Figure
www.onsemi.com
16
NCL2801
7 that the VCTRL hysteresis voltage is defined by: VCTRL,hyst
= VCTRL,th43 − VCTRL,th,34 and more generally by VCTRL,hyst
= VCTRL,th,ij − VCTRL,th,ji. If VCTRL pin peak−to−peak
ripple voltage stays under VCTRL,hyst there will be no valley
hopping.
VCTRL,hyst can be calculated for each frequency foldback
option determined by RCS value from the thresholds
specified in Table 7. While the hysteresis between two
adjacent valley numbers is constant for one frequency
foldback option, it decreases for options having a lower
CrM to DCM VCTRL threshold. This should not be a
problem as the two times mains frequency ripple also
decreases when VCTRL pin voltage decreases which
results from output power decrease. We can also mention
looking at Figure 7 and the specified frequency foldback
thresholds of Table 7 that VCTRL,th,56 which is the VCTRL
threshold at which we force counting 6 valleys, has always
the same value. This threshold is also called VCTRL,ADT
because when VCTRL pin voltage falls under this threshold,
an analog dead−time starts to be added to the dead−time
determined by counting 6 valleys. The lower VCTRL pin
voltage goes under VCTRL,ADT threshold, the more analog
dead time is added. An example on how the analog dead time
can be added is shown in the circuit of Figure 4 and the
correspond power MOSFET drain voltage is shown in
Figure 3.
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17
NCL2801
Forced Valley #
VCTRL,th,65
6
@RCS = 1000 W
VCTRL,th,54
5
VCTRL,th,56
VCTRL,th,43
4
VCTRL,th,45
VCTRL,hyst
VCTRL,th,32
3
VCTRL,th,34
VCTRL,th,21
2
VCTRL,th,23
1
VCTRL,th,12
0.5
1.0
Forced Valley #
1.5
VCTRL (V)
2.0
2.5
3.5
4.0
4.5
VCTRL ,ADT
Entering Forced Valley #
VCTRL,th,65
6
3.0
Exiting Forced Valley #
VCTRL ,th,54
5
4
VCTRL,th,56
VCTRL ,th,43
@RCS = 330 W
VCTRL,hyst
VCTRL,th,32
VCTRL,th,45
3
VCTRL,th,34
VCTRL ,th,21
2
VCTRL,th,23
1
VCTRL,th,12
0.5
1.0
VCTRL (V)
1.5
2.0
2.5
3.0
3.5
4.0
4.5
Figure 7. Forced Valley Number versus VCTRL Pin Voltage For a Two Different RCS
Values of the Mandatory List {150 W, 330 W, 620 W, 1000 W}
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18
NCL2801
NCL2801 On−time Modulation and VTON Processing
Circuit
One can show that the ac line current is given by:
Let’s analyze the ac line current absorbed by the PFC
boost stage. The initial inductor current at the beginning of
each switching cycle is always zero. The coil current ramps
up when the MOSFET is on. The slope is (Vin/L) where L is
the coil inductance. At the end of the on−time (t1 ), the
inductor starts to demagnetize. The inductor current ramps
down until it reaches zero. The duration of this phase is (t2 ).
In some cases, the system enters then the dead−time (t3 ) that
lasts until the next clock is generated.
I in + V in
t 1(t 1 ) t 2)
Where
T + t1 ) t2 ) t3
Vin
Iind
L1
Cin
DRV
t1
t2
D1
Vout
Cbulk
Q1
Rsense
time
Iind
(eq. 3)
is the switching period and Vin is the ac line rectified
voltage.
In light of this equation, we immediately note that Iin is
proportional to Vin if [t1.(t1+t2)/T] is a constant.
Vin
Ipeak,max
(eq. 2)
2TL
t3
time
0
T
Figure 8. PFC boost converter and Inductor Current in DCM
of the NCL2801 because at steady state, what results from
a current control is a constant on−time.
NCL2801 operates in current control mode. As portrayed
by Figure 8 & Figure 10, the MOSFET on−time t1 results
from a current control mode circuitry which is using a
dedicated circuitry monitoring Vctrl and dead−time t3
ensuring [t1.(t1+t2)/T] is constant and as a result making Iin
proportional to Vin (PF=1)
On−time t1, also called tON, has a high value clamp called
tON,max, generated by an internal circuitry. This 30−ms
clamp value is given for maximum VCTRL pin voltage
(VCTRL=4.5 V) but reduces down to 5 ms when VCTRL pin
voltage reaches 0.5 V which is its minimum value.
The input current is then proportional to the input voltage.
Hence, the ac line current is properly shaped.
One can note that this analysis is also valid in the CrM
case. This condition is just a particular case of this
functioning where (t3=0), which leads to (t1+t2=T) and
(Vton=Vregul). That is why the NCL2801 automatically
adapts to the conditions and transitions from DCMn to
DCMn+1 and DCMn+1 to DCMn without power factor
degradation and without discontinuity in the power delivery.
This analysis while carried−out for constant on−time
architecture is also valid for the current control architecture
Current Control Mode & THD Enhancer
In order for the mains current to have very good THD, the
Current Control Mode depicted in Figure 10 mode is
preferred.
To improve the mains current THD, an offset voltage is
added to the multiplier output (see Figure 9).
The added offset is equal to Koffset.Vton
The role of this offset is to add on−time and this added
on−time will be very beneficial close to line zero crossing
where, without this offset, the inductor peak current is low
and comparable to the inductor negative peak current
resulting to zero line current. Adding this offset greatly
reduces the time width during which the line current is equal
to zero (line voltage cross−over distortion) and by doing
improve the line current THD.
A traditional scheme, where the inductor current during
on−time multiplied by Rsense is compared to a scaled down
rectified mains voltage Vin multiplied by Vton is used. What
may sound strange is the Vton, but Vton is equal to Vregul
when in CrM.
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NCL2801
Iind
Rsense
RCS
PWM
Vin
Vipeak
Vm
Rmult1
End of on−time
when high
Rmult2
Vton
Vton
Figure 9. Simplified Current Control Circuit (Max On−Time and Blanking Not Shown)
V regul + (V VCTRL * 0.5V)
1.5V
4.0V
In DCM mode, the Vton input of the multiplier is modified
thanks to the Vton processing block in order to maintain the
mains current proportional to the mains voltage.
It can be demonstrated that the maximum peak inductor
current is given by the following equation
(eq. 4)
The range of Vregul is equal to 1.5 V and Vregul operates
between 0 V and 1.5 V.
The range of VCTRL is equal to 4.0 V and VCTRL operates
between 0.5 V and 4.5 V.
I ind,peak,max +
V ipeak,max
R sense
+
ǒKmKmult Ǹ2 Vmains,rms ) KoffsetǓ @ VTON
R sense
(eq. 5)
From Iind,peak,max, assuming we are in CrM we can get the
rms line current by :
I mains,rms +
V ind,peak,max
2 Ǹ2
+
ǒKmKmult Ǹ2 Vmains,rms ) KoffsetǓ @ VTON
2 Ǹ2 R sense
(eq. 6)
Then,
P mains,rms +
(K mK mult Ǹ2 V 2mains,rms ) K offsetV mains,rms) @ V TON
2 Ǹ2 R sense
(eq. 7)
To better see the effect of Koffset on Pmains,rms the previous
equation can be re−written as follows
P mains,rms +
K mK multV 2 mains,rmsV TON
2R sense
In both previous equations Kmult is the multiplier gain
and Km is given by the following:
Km +
R mult2
R mult1 ) R mult2
)
K offsetV mains,rmsV TON
2 Ǹ2 R sense
(eq. 8)
The multiplier gain, for product options having no line
level detection ([**B]&[**D] has a value which does not
vary versus Vmains value.
For product options having line level detection
([**A]&[**C], the multiplier gain has an High Line value
(Kmult,HL) and a Low Line value (Kmult,LL). These two line
(eq. 9)
It is important to mention that in CrM mode so particularly
at max output power, VTON=Vregul.
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NCL2801
options. For the product options where the DRE is enabled,
an internal comparator monitors the FB pin voltage (VFB )
and when VFB is lower than 95.5% of its nominal value, it
connects the 220−mA current source to VCTRL pin in order
to speed−up the charge of the compensation network.
Effectively this appears as a 10x increase in the loop gain.
The circuit also detects overshoot using the Soft OVP
circuitry and immediately reduces the power delivery when
the output voltage exceeds a value which is product option
dependent.
The error Operational Transconductance Amplifier OTA
and the OVP and DRE comparators share the same input
information. Based on the typical value of their parameters
and if Vbulk,nom is the bulk nominal voltage value (e.g., 400
V), we can deduce:
• Output Regulation Level:
Vbulk,nom
• Output DRE Level:
Vbulk,dre =
level dependent multiplier gain values act as a two−level line
feed forward.
NCL2801 Maximum on−time
In order to avoid the on−time to go too high close to line
voltage zero crossing, a VCTRL dependent maximum on
time circuitry has been added. The on−time limiting values
are linearly depending on VCTRL pin voltage as follows:
30−ms @VCTRL = 4.5 V and 5−ms @VCTRL = 0.55 V
NCL2801 Regulation Block and Output Voltage Control
A trans−conductance error amplifier (OTA) with access to
its inverting input (FB pin) and to its output pin (VCTRL
pin) is provided. It features a typical trans−conductance gain
of 200 mS and a maximum current capability of +/−20 mA.
The output voltage of the PFC stage is typically scaled down
by a resistors divider and monitored by the OTA inverting
input (pin FB). Bias current is minimized (less than 500 nA)
to allow the use of a high impedance feed−back network.
However, it is high enough so that the pin remains in low
state if the pin is not connected.
The output of the error amplifier is brought to pin VCTRL
for external loop compensation. Typically a type−2 network
is applied between pin VCTRL and ground, to set the
regulation bandwidth below about 20 Hz and to provide a
decent phase boost.
The swing of the error amplifier output is limited within
an operating range:
− It is forced above a voltage drop (VF ) by a dedicated
circuitry.
− It is clamped not to exceed 4.0 V + the same VF voltage
drop.
The VF value is 0.5 V typically.
The regulated output voltage Vbulk uses an internal
reference voltage VREF = 2.5 V.
The regulated Vbulk voltage (its average value in case of
important ripple) will be equal to VREF multiplied by the
dividing factor given by the resistor bridge placed between
Vbulk and FB pin, resulting for example in Vbulk = 395 V.
Given the low bandwidth of the regulation loop, abrupt
variations of the load, may result in excessive over or
under−shoot. Over−shoot is limited by the Over−Voltage
Protection (OVP) connected to FB pin (Feedback).
Optionally, NCL2801 embeds a “Dynamic Response
Enhancer” circuitry (DRE) that limits under−shoots. The
DRE works during startup phase by injecting current into the
VCTRL pin which rises VCTRL pin voltage and allows
more current to charge the bulk capacitor. After the startup
phase, when internal PFCOK flag goes high, the DRE is
disabled on some options, but is enabled in other product
95.5%.Vbulk,nom
• Output Soft OVP Level:
Vbulk,sovp =
• Output Fast OVP level:
Vbulk,fovp =
X%.Vbulk,nom
Y%.Vbulk,nom
NOTE:
Note: X% and Y% are product option dependent
Current Sense and Current Control
The power MOSFET current Iind is sensed during the
on−time phase by the resistor Rsense inserted between the
MOSFET source and ground (see Figure 10). The voltage
Rsense .Iind after a proper leading edge blanking (tLEB,OCP
and tLEB,OVS) starting from the power MOSFET rising
edge drive signal (DRV) is compared to internal
over−current protection (OCP) and overstress protection
(OVS) internal references (namely VCS(th) and
VCS,OVS(th) ) which when triggered ends the on−time for
OCP or stops the switching during 800 us for OVS. The
voltage Rsense .Iind is also low−pass filtered (R=20 kW,
C=20 pF see Figure 10), leading edge blanked and
compared to the multiplier output voltage to generate the
end of the on−time which is typical of a current mode control
(see Figure 10).
In order to improve the THD of the mains current, a Vton
dependent offset at the output of the multiplier and a
TONMAX processing block have been added (see Figure
10).
Vton is one of the inputs of the multiplier for helping
improve THD in DCM mode (Frequency Foldback).
Vton is equal to Vregul which is proportional to the
VCTRL pin voltage when in CrM mode.
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NCL2801
OCP
OVS
R CS – VCRTL,th,ij,Rcs
Lookup−Table
Iind
20kOhms
VCTRL ,th,12,Rcs controls
the Frequency Foldback
threshold
BLK
Rsense
RCS
10pF
PWM
Vin
Rmult1
Vm
End of on−time
when high
Rmult2
Vton
Vton
Koffset.Vton
Vregul
Figure 10. PWM Circuit Showing Current Control Mode With a New MULT Pin
Zero Current Detection (ZCD)
The ZCD pin features a classical and robust ZCD
detection based on sensing the auxiliary winding voltage as
shown in Figure 11. The ZCD pin voltage is clamped high
at VCC plus a diode Vf (0.7 V) and clamped low at minus
a diode Vf (−0.7 V) and then compared to ZCD thresholds
voltages VZCD,th,H and VZCD,th,L (see Table 6).
When no signal is received that triggers the ZCD
comparator to indicate the end of inductor demagnetization,
an internal 200−ms watchdog timer initiates the next drive
pulse.
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NCL2801
VCC
Vaux
RZCD
ZCD
ZCD
VZCD,th,H
VZCD ,th,L
Figure 11. Zero Current Detection (ZCD) Circuitry
Brown−Out Detection) – (Options [**A], [**B])
The line voltage (Vline,BO,L) at which the controller starts
reducing on−time until it stops switching which can be
called brown−out and is given by:
Thanks to the line voltage scaled−down by Km and
rectified available on MULT−pin (Vm) a Brown−Out feature
is available on options [**A], [**B].
V m(t) + K m @ V in(t)
V line,BO,L + V line,Brown*in +
(eq. 10)
With
Km +
R mult2
The VMULT voltage is sensed and when eventually VMULT
falls under Brown−out internal reference voltage VBOL for
50 ms, BONOK flag will be set to 1. After BONOK flag is
set to 1, drive is not disabled, instead, a 30−mA current
source (IVCTRL(BO)) is applied to VCTRL pin to gradually
reduce VCTRL . As a result, the circuit only stops pulsing
when the STATICOVP function is activated. At that
moment, the circuit stops switching. This method limits any
risk of false triggering.
The input of the PFC stage has some impedance that leads
to some sag of the input voltage when the input current is
large. If the PFC stage suddenly stops while a high current
is drawn from the mains, the abrupt decay of the current may
make the input voltage rise and the circuit detect a correct
line level. Instead, the gradual decrease of VCTRL avoids a
line current discontinuity and limits the risk of false
triggering.
The line voltage (Vline,BO,H) at which the controller starts
switching which can be called brown−in and is given by the
following equation:
V line,BO,H + V line,Brown*in +
V BOH
K m Ǹ2
K m Ǹ2
(eq. 13)
It has to be reminded that while changing Km by changing
the Rmult resistors dividing ratio can help to shift up or
down the line brown−in and brown−out levels, Km
determines also the internal gain of the controller, together
with Rsense and Kmult (multiplier gain), so care must be
taken at adjusting Rsense accordingly to the Km adjustment.
(eq. 11)
R mult1 ) R mult2
V BOL
Line Level Detection and 2−Level Line Feed−Forward–
(Options [**A], [**C])
For product options [**A], [**C], the line level detection
(High Line or Low Line) feature together with a two−level
line feed forward is activated and operates as described here
after.
MULT pin voltage VMULT is used to sense the line voltage
and apply a two−level line feed−forward.
The VMULT voltage is compared to a VHL internal voltage
reference. If VMULT exceeds VHL, the circuit detects
a High−Line state (LLINE flag is set to 0) and the multiplier
gain is set to value corresponding to High Line which is
Kmult,HL. Once this occurs, if VMULT remains below VLL
for 25 ms, the circuit detects a Low−Line state (VHL(hyst)
hysteresis) and the multiplier gain is set to Kmult,LL.
At startup, the circuit is in High−Line state (LLINE flag
is set to 0) and then VMULT will be used to determine the
High−Line or Low−Line state.
(eq. 12)
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NCL2801
The line range detection circuit allows more optimal loop
gain control for universal (wide input mains) applications by
adjusting the multiplier gain value versus line voltage status
(High Line or Low Line).
For the options [**B], [**D], no line feedforward action
is taken based on the line level and the multiplier gain
remains set at Kmult whatevever line level.
The High Line and Low Line thresholds, respectively
Vline,HL and Vline,LL are given by the following equations:
V line,HL,rms +
V line,LL,rms +
V HL
K m Ǹ2
V LL
K m Ǹ2
(eq. 14)
(eq. 15)
Vin
VREF,LLINE
VHL if LLINE=1
VLL otherwise
VREF,BONOK
VBOH if BONOK=1
VBOL otherwise
Figure 12. Input Line Sense and Brown−out Monitoring
Thermal Shut−Down (TSD)
More specifically, when the circuit is in OFF state:
− The drive output is kept low
− All the blocks are off except:
♦ The UVLO circuitry that keeps monitoring the
VCC voltage and controlling the start−up current
source accordingly.
♦ The TSD (thermal shutdown)
− Vctrl is grounded so that when the fault is removed, the
device starts−up under the soft start mode.
− The internal “PFCOK” signal is grounded.
− The output of the “Vton processing block” is grounded
An internal circuitry sensing the silicon temperature
disables the circuit gate drive and keeps the power switch off
when the junction temperature exceeds 150_C. The output
stage is then enabled once the temperature drops below
about 100_C (50_C hysteresis).
The temperature shutdown remains active as long as the
circuit is not reset, that is, as long as VCC is higher than a reset
threshold.
Output Drive Section
The output stage contains a totem pole optimized to
minimize the cross conduction current during high
frequency operation. Its high current capability
(−500 mA/+800 mA) allows it to effectively drive high gate
charge power MOSFET.
Failure detection
When manufacturing a power supply, elements can be
accidently shorted or improperly soldered. Such failures can
also happen to occur later on because of the components
fatigue or excessive stress, soldering defaults or external
interactions. In particular, adjacent pins of controllers can be
shorted; a pin can be grounded or badly connected. Such
open/short situations are generally required not to cause fire,
smoke or hazardous conditions. NCL2801 integrate
functions that ease meeting this requirement. Among them,
we can list:
♦ Fault of the GND connection
If the GND pin is not connected, internal circuitry
detects it and if such a fault is detected for 200 ms,
the circuit stops operating.
♦ Fault of the FB connection
If the FB pin is left open because for example of bad
OFF Mode
As previously mentioned, the circuit turns off when one
of the following faults is detected:
• Incorrect feeding of the circuit (“UVLO” high when
VCC
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