NCL30060B3DR2G

NCL30060 High PF Offline Single Stage LED Driver with High Voltage Startup The NCL30060 is a switch mode power supply controller intended for low to medium power single stage power factor (PF) corrected LED Drivers. It employs a constant on−time control method to ensure near unity power factor across a wide range of input voltages and output power. It can be used for isolated flyback as well as buck topologies. The device offers a suite of robust protection features to ensure safe operation under a range of fault conditions. Version NCL30060B2 is intended for constant voltage (CV) regulated output drivers where a DC−DC converter or linear regulator in the second stage controls the current to the LEDs so the output short circuit protection detector function has been disabled. Version NCL30060B3 is intended for applications not requiring Brown Out protection or output short circuit protection as typical with low standby operation. The NCL30060B4 removes on−time modulation for solutions not needing this feature. Features • • • • • • • • • • • • • • • • • • Built−In High Voltage Start−up Circuit Direct Opto−coupler Feedback Connection Constant On−Time PWM Control Quasi−Resonant Switching Low Operating Current (1.6 mA typical) Source 250 mA / Sink 400 mA Totem Pole Gate Driver Integrated 12 V (typ) Gate Drive Clamp Frequency Dithering for Reduced EMI Profile Enable/Disable Function Dynamic Self−Supply (DSS) Operation Operating TJ from −40°C to 105°C Maximum On Time Protection Integrated Brown−out Overvoltage Protection Cycle−by−Cycle Overcurrent Protection Output Winding Short−Circuit Protection Thermal Shutdown These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant www.onsemi.com MARKING DIAGRAM 8 SOIC−7 CASE 751U 1 L0060xx ALYWG G L0060xx = Specific Device Code xx = A, B, B1, B2, B3, B4 A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) PIN CONNECTIONS FB 1 8 HV 6 VCC 5 DRV CS/ZCD 2 RT 3 GND 4 (Top View) ORDERING INFORMATION See detailed ordering and shipping information on page 14 of this data sheet. Typical Applications • LED Lighting © Semiconductor Components Industries, LLC, 2016 April, 2018 − Rev. 8 1 Publication Order Number: NCL30060/D Neutral Line Figure 1. NCL30060 Typical Application Diagram CFB RZCD DZCD EMI FILTER RT DRV GND RCS Vcc HV RT CS FB U1 NCL30060 CVcc DHV Cin DVcc Dclamp Rsense M1 Rclamp U2 CY 4 3 2 1 www.onsemi.com 2 Cclamp Cout + Dout Ro RVcc1 DVcc1 CVcc1 RIS GND Vcc FBC RIS1 ISNS VSNS U3 NCP4328A Rcomp2 Ccomp1 Ccomp2 LED Cathode RVout2 RVout1 LED Anode NCL30060 NCL30060 ACTIVE Ő TSHDN tint Central Logic UVLO VCC blanking (Fault_OVP) Counter Count Reset − + − VDD ACTIVE + VDD2 DRV OVP Comparator VOVP Peak Current DRV Comparator LEB tCS(LEB1) VCC Management Internal Reference DRV VCC(on)/ VCC(off)/ VCC(reset)/ VCC(rUVLO)/ VCC(OVP) toff1,2 Timer Counter Count Short Winding Comparator DRV Reset Disable Selector Reset Re−start ILIM2 CS/ZCD LEB tCS(LEB2) VILIM2 UVLO ILIM2, OVP DRV Edge Detector VCC VILIM1 ZCD Comparator VCC HV(high) − VCC_OK HV Startup Control Maximum Off−Time Detector toff(MAX) + Delay tSHDN(delay) Integration Pulse − Open RT Pin Short Circuit Detector + Thermal Shutdown BO_NOK − Brown−out Detection Auto−Restart Fault Control ‘HV Tran + Istart Selector VZCD Edge Detector TSHDN ZCD Blanking Time VCC DRV Clamp S Q Reset Dominant Latch Q R VDD2 Vton(MAX) FB PWM DRV Comparator FB Offset Von−time DRV RT Disable Comparator + IRT(disable) * RCS ACTIVE IRT Ramp Modulation fMOD ton(mod) Current Mirror + VPRT − RCS RT Enable Comparator − − ACTIVE UVLO Max On−Time Clamp On Time Ramp Delay tdisable(blank)/ tenable(blank) GND + Max On Time Comparator DRV ACTIVE Figure 2. NCL30060 Internal Functional Block Diagram www.onsemi.com 3 VRT(enable) RT NCL30060 Table 1. NCL30060 PIN FUNCTION DESCRIPTION Pin No Pin Name Pin Description 1 FB Feedback Input. The FB pin is the control input to the PWM comparator. A voltage level controlled by the feedback loop on this pin is compared to the internal ramp establishing power switch on time. 2 CS/ZCD Current sense and zero current detection. The CS input is used to sense the instantaneous switch current in the external power switch during switch on time. A fast−responding high threshold level for short circuit detection is provided along with a longer blanking time at lower level for overload conditions. During switch off time, this pin monitors the bias winding to detect transformer demagnetization. When stored energy is depleted the gate drive turns on the power switch initiating the next cycle. This pin also detects overvoltage conditions through the bias winding. A blanking time prevents false overvoltage triggering due to noise. 3 RT Maximum on−time adjust. The RT pin establishes the ramp charging current. The PWM comparator establishes the switch on time from the ramp and FB signal. Pulling the RT pin below the disable threshold forces the controller in the Armed mode where all switching functions cease. 4 GND Ground. This is the ground reference for the controller. All bypassing and control components should be connected to the GND pin with a short trace length to minimize noise. 5 DRV Drive. The high current capability of the totem pole gate drive makes it suitable to directly control high gate charge power MOSFETs. The driver stage provides both passive and active pull−down circuits which force the MOSFET gate off when VCC is below normal operating levels. 6 VCC IC Supply. This is the positive supply of the controller and source for powering external circuits. Internal bias will be disabled when external power is sufficient to maintain operation. 7 NC No−connect. This missing pin provides creepage distance. 8 HV High−voltage input. Monitors input voltage for brown−out detection and power to operate controller. www.onsemi.com 4 NCL30060 Table 2. MAXIMUM RATINGS (Notes 1, 2, 3 and 4) Rating Symbol Value Unit FB Voltage VFB −0.3 to 10 V FB Current IFB ±10 mA CS/ZCD Voltage VCS/ZCD −0.9 to 12.4 V CS/ZCD Current ICS/ZCD −2 / +5 mA VRT −0.3 to 5 V RT Voltage RT Current DRV Voltage (Note 2) DRV Sink Current DRV Source Current Supply Voltage Supply Voltage Rate of Change IRT ±10 mA VDRV −0.3 to VDRV(high) V IDRV(sink) 400 mA IDRV(source) 250 mA VCC −0.3 to 30 V dVCC/dt 1 V/ms Supply Current ICC 20 mA HV Voltage VHV −0.3 to 700 V HV Current IHV 20 mA RqJA 125 _C/W Thermal Resistance, Junction to Ambient 1 Oz Cu Printed Circuit Copper Clad) ESD Capability Human Body Model per JEDEC Standard JESD22−A114E. (Note 5) Machine Model per JEDEC Standard JESD22−A114E. Charge Device Model per JEDEC Standard JESD22−C101E. Operating Temperature Range While Biased 5000 200 1500 V TJ −40 to 105 °C Maximum Junction Temperature TJMax 150 °C Storage Temperature Range TSTG −60 to 150 °C TL 300 °C Lead Temperature (Soldering, 10 s) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. VCS/ZCD(MAX) is the maximum voltage of the pin shown in the electrical table. When the voltage on this pin exceeds 7.4 V, the pin sinks a current equal to [(VCS/ZCD − 7.4 V) / 1 kW]. A VCS/ZCD of 9 V generates a sink current of approximately 1.6 mA. 2. Maximum driver voltage is limited by the driver clamp voltage, VDRV(high), when VCC exceeds the driver clamp voltage. Otherwise, the maximum driver voltage is VCC. 3. This device contains Latch−Up protection and has been tested per JEDEC Standard JESD78D, Class I and exceeds ±100 mA. 4. Low Conductivity Board. As mounted on 80 x 100 x 1.5 mm FR4 substrate with a single layer of 50 mm2 of 2 oz copper trances and heat spreading area. As specified for a JEDEC51−1 conductivity test PCB. Test conditions were under natural convection of zero air flow. 5. Pin 8 HV pin is ESD rated to 1200 V. www.onsemi.com 5 NCL30060 ELECTRICAL CHARACTERISTICS (VCC = 14 V, VHV = 120 V, VFB = 4 V, VCS/ZCD = 0 V, CDRV = 1 nF, RT = 20 kW, for typical values TJ = 25_C, for min/max values, TJ is – 40_C to 105_C, unless otherwise noted) Characteristic Test Conditions Symbol Min Typ Max Unit 1 V/ms, VCC increasing 1 V/ms, VCC decreasing VCC(on) − VCC(MIN) VCC decreasing 1 V/ms, VCC(min) − VCC(UVLO) VCC decreasing VCC increasing VCC(on) VCC(MIN) VCC(HYS1) VCC(UVLO) VCC(HYS2) VCC(reset) VCC(inhibit) 11.75 10.7 0.9 8.2 2.0 4.5 0.35 12.5 11.5 – 8.8 – 5.5 0.7 13.75 12.8 – 9.4 – 7.5 0.95 VRT = 0 V CDRV = open CDRV = 1nF ICC1 ICC2 ICC4 ICC5 140 300 800 1490 190 335 870 1600 240 450 975 1700 Istart1 Istart2 Istart3 0.31 9 3.5 0.77 14 5.25 1.23 19 7.00 mA VCC(OVP) 27 28 29 V tdelay(VCC_OVP) 15 30 50 ms V HV = 400 V, VCC = VCC(on) to VCC(MAX) IHV(off) – 24 30 mA Istart2 = 1 mA VHV(MIN) – – 40 V Istart3 = 5.25 mA VHV(tran) 160 175 190 V VDRV from 10 to 90% of VDRV tPDRV(rise) − 80 180 − 40 80 STARTUP AND SUPPLY CIRCUITS Supply Voltage Startup Threshold Minimum Operating Voltage Operating Hysteresis Undervoltage Lockout Hysteresis Between VCC(MIN) and VCC(UVLO) Internal Latch/Logic Reset Level Transition from Istart1 to Istart2 Supply Current In Fault Mode In Disable Modes Active Mode Without CDRV, fSW = 60 kHz Active Mode With CDRV, fSW = 60 kHz Startup Current VCC = 0 V to Vinhibit VHV = 400V VCC Overvoltage Protection Threshold VCC Overvoltage Protection Delay Startup Circuit Off−State Leakage Current Minimum Startup Voltage Startup Current Transition Voltage Threshold V mA GATE DRIVE Rise Time (10−90%) Fall Time (90−10%) Current Capability Source Sink High State Voltage Low State Voltage ns VDRV from 90 to 10% of VDRV tPDRV(fall) ns VDRV = 2 V VDRV = 10 V IDRV(SRC) IDRV(SNK) – – 250 400 – – VCC = VCC(UVLO) + 0.2 V, RDRV = 10 kW VDRV(highuvlo) − − 0.25 V VCC = VCC(OVP) − 0.5 V , RDRV = 10 kW VDRV(high) 10 12 14 V IDRV = 100mA VDRV(low) – – 0.25 V VFB = open VFB(open) 6.0 6.3 6.6 V VFB decreasing VFB(offset) 0.60 0.70 0.80 V RFB(bias) 20 25.8 29.6 kW mA FEEDBACK Feedback Open Voltage Minimum FB Voltage to Generate Drive Pulses Feedback Bias Resistor CONSTANT ON TIME GENERATOR On Time RT = 20 kW, VFB = VFB(open) RT = 10 kW, VFB = VFB(open) RT = 80 kW, VFB = VFB(open) RT = 80 kW, VFB = 4.45 V RT = 80 kW, VFB = 3.2 V ton1 ton2 ton3 ton4 ton5 4.75 2.37 18.4 13.6 9.0 5.0 2.50 19.5 14.5 9.56 5.25 2.63 20.7 15.5 10.1 ms Maximum On Time RT = 110 kW to open, VFB = VFB(open) ton(MAX) 22.0 27.5 33.0 ms Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 6 NCL30060 ELECTRICAL CHARACTERISTICS (VCC = 14 V, VHV = 120 V, VFB = 4 V, VCS/ZCD = 0 V, CDRV = 1 nF, RT = 20 kW, for typical values TJ = 25_C, for min/max values, TJ is – 40_C to 105_C, unless otherwise noted) Characteristic Test Conditions Symbol Min Typ Max Unit VFB increasing VFB(tonMAX) 5.415 5.70 5.985 V VRT(REG) – 2.0 – V CONSTANT ON TIME GENERATOR Maximum On−Time Feedback Voltage RT Pin Regulation Voltage On−Time Modulation Frequency (Note 6) On Time Modulation (Note 6) fMOD 254 292 325 Hz ton(MOD) ±4 ±6 ±8 % DISABLE FUNCTION RT Disable Current Threshold IRT Decreasing IRT(disable) 250 325 400 mA RT Enable Threshold VRT increasing VRT(enable) 380 400 420 mV IRT(dis) 45 50 55 mA tdisable(blank) 6.8 8 9.8 ms RT Pull−Up Current In Disable Mode Disable Blanking IRT increasing or VDisable decreasing ZERO CURRENT DETECTION ZCD Arming Threshold VCS/ZCD Increasing VZCD(ARM) 225 250 275 mV ZCD Trigger Threshold VCS/ZCD Decreasing VZCD(TRIG) 35 55 90 mV tARM(blank) 1.7 2.05 2.35 ms tZCD(PROP) – 150 170 ns − −0.9 12.4 −0.7 − 0 ZCD Arming Blanking Duration ZCD Propagation Delay Input Voltage Excursion Upper Clamp Negative Clamp VCS/ZCD stepping from 2.0 V to 0 V, dV/dt = 20 V/ms, VCS/ZCD = VZCD(TRIG) to VDRV = 10% VCC = 14V, ICS/ZCD = 5 mA VCS/ZCD(MAX) VCC = 14V, ICS/ZCD = −2 mA VCS/ZCD(MIN) V CS/ZCD Open Voltage VZCD(open) 6.5 – – V Pull−up Current Source ICS/ZCD 0.7 1.0 1.3 mA toff1 toff2 100 1000 200 1250 300 1700 ms Between VZCD(rising) and VZCD(falling) to DRV tSYNC – 70 200 ns TJ = 25_C TJ = −40_C to 125_C VILIM1 242.5 238 250 250 257.5 262 mV Propagation Delay Step VCS/ZCD 0 V to VILIM1 + 0.1 V to DRV falling edge, tILIM1 − 100 200 ns Leading Edge Blanking Duration Step VCS/ZCD 0 V to VILIM1 + 0.1 V to DRV falling edge, tCS(LEB1) 250 325 400 ns VILIM2 475 500 525 mV Timeout After Last Demagnetization Detection Minimum ZCD Pulse Width VCS/ZCD > VILIM2 CURRENT SENSE Current Sense Voltage Threshold Abnormal Overcurrent Fault Threshold Fault Propagation Delay Step VCS/ZCD 0 V to VILIM2 + 0.1 V to DRV falling edge, tILIM2 – 125 175 ns Fault Leading Edge Blanking Duration Step VCS/ZCD 0 V to VILIM2 + 0.1 V to DRV falling edge, tCS(LEB2) 90 120 150 ns Leading Edge Blanking Duration Ratio tLEB(LEB2)/tLEB1 tLEB(ratio) – 0.37 – − nILIM2 – 4 – Number of Consecutive Abnormal Current Events to Enter Fault Mode (Latch mode available on customer request) Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 7 NCL30060 ELECTRICAL CHARACTERISTICS (VCC = 14 V, VHV = 120 V, VFB = 4 V, VCS/ZCD = 0 V, CDRV = 1 nF, RT = 20 kW, for typical values TJ = 25_C, for min/max values, TJ is – 40_C to 105_C, unless otherwise noted) Characteristic Test Conditions Symbol Min Typ Max Unit 43 50 55 ms ms OUTPUT SHORT CIRCUIT AND OVERVOLTAGE PROTECTION Output Short Off−Time Detector Threshold (Note 7) Detected during DRV low toff(OS) Output Short Detection Integration Weighting Ratio (Note 7) NINTratio(OS)= Charging speed(Output Short detected) / Discharging speed (normal operation) NINTratio(OS) Output Short Detection Integration Time for Continuous Integration pulses (Note 7) 20 tINTCON(OS) 36.7 40 45.7 DRV is low VOVP 5.8 6.0 6.2 V VCS/ZCD = 0 V to 7 V ramp, dV/dt = 1 V/ms, VCS/ZCD = VOVP to DRV low tOVP(PROP) – – 2.5 ms tOVP(blank) 1.5 2.0 2.5 ms nOVP – 4 – tautorecovery 0.8 1.0 1.2 s System Startup Threshold VBO(start) 102 111 120 V System Shutdown Threshold VBO(stop) 88 96 104 V tBO(stop) 43 54 65 ms Overvoltage Threshold Overvoltage Propagation Delay Overvoltage Blanking Number of Consecutive Overvoltage Events to Enter Fault Mode Mode (Latch mode available on customer request) Auto−recovery Timer Duration BROWN−OUT PROTECTION (does not apply to B1 and B3 options) Brown−out Detection Blanking Time VHV decreasing, delay from VBO(stop) to drive disable THERMAL PROTECTION Thermal Shutdown Temperature increasing TSHDN − 160 − _C Thermal Shutdown Hysteresis Temperature decreasing TSHDN(HYS) − 50 − _C Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 6. Parameter does not apply to B4 option. 7. Parameter does not apply to B2, B3 and B4 options. www.onsemi.com 8 NCL30060 DETAILED OPERATING DESCRIPTION HIGH VOLTAGE STARTUP CIRCUIT I CC(gate charge) + f @ Q G The NCL30060 integrates a 700 V startup regulator eliminating the need of external startup components. The startup regulator consists of a constant current source that supplies current from the high voltage input terminal (HV) to the supply capacitor on the VCC pin (CCC). The startup circuit current (Istart2) and (Istart3) are disabled if the VCC pin is below VCC(inhibit). In this condition, the startup current is reduced to Istart1, typically 0.77 mA. In addition, this regulator reduces no load power and increases the system efficiency as it uses negligible power in the normal operation mode. After VCC pin is higher than VCC(inhibit) threshold, the startup circuit uses Istart3 to charge the VCC capacitor during the initial charging. Istart3 has a typical value of 5.25 mA. Once CCC is charged to the startup threshold, VCC(on), typically 12.5 V, the startup regulator is disabled and the controller is enabled. The initial charging on VCC capacitor is done. The controller is then biased by the VCC capacitor. (eq. 1) where f is the operating frequency and QG is the gate charge of the external MOSFETs. The additional gate charge current should not exceed the startup circuit. Otherwise, VCC will not charge to VCC(on) and may stay at an undetermined voltage while dissipating excessive power. The controller and the startup circuit are disabled if the junction temperature of the device exceeds the thermal shutdown threshold, TSHDN, typically 160_C. The controller is disabled if VCC falls below the undervoltage lockout (UVLO) threshold, VCC(UVLO), typically 8.8 V. A noise filter, tUVLO, 25 ms maximum, blanks the UVLO fault before disabling the controller. FEEDBACK INPUT A signal proportional to the output error is applied to the FB pin by means of an optocoupler or other means such as an Op Amp. The PWM Comparator compares the feedback or error signal to a level shifted voltage ramp to control the power switch on−time. The feedback voltage is directly proportional to the output power. An internal pull up resistor, RFB, drives this pin to provide more linear response from the optocoupler transistor. The voltage reference biasing RFB is typically 6.3 V . The minimum on−time, ton(MIN), is determined by the propagation delay of the PWM Comparator and control logic. It is limited below 200 ns. The minimum on−time is achieved when VFB is right on the voltage offset of the On−time Ramp, VFB(offset). A VFB below VFB(offset) results in no drive pulses or “zero” on−time. The maximum on−time is limited by the Maximum On−time comparator. The comparator is enabled once the feedback voltage, VFB, exceeds VFB(tonMAX). This establishes the point where the LED driver transitions from constant current feedback (if so configured) to primary power control. Figure 3. Initial Charging of VCC and Normal DSS The startup regulator is enabled once VCC falls below its minimum operating threshold, VCC(MIN), typically 11.5 V. The driver continues operation while VCC is charged by the startup circuit. This operating mode is known as dynamic self supply or DSS. During normal DSS operation, the startup circuit uses Istart2 to charge the VCC capacitor when the line voltage is below VHV(tran), and the startup circuit uses Istart3 when the line voltage is higher than VHV(tran). VHV(tran) has a typical value of 175 V. Figure 3 shows the initial charging of VCC capacitor and normal DSS. The startup circuit continues to charge VCC until the convertor bias winding is able to provide power to the VCC capacitor. As long as the bias winding can maintain the VCC voltage higher than VCC(MIN), the startup circuit will not be enabled. The startup circuit enters DSS mode if the VCC voltage is lower than VCC(MIN). The increase in current consumption due to external gate charge is calculated using Equation 1. MAXIMUM ON−TIME The PWM Comparator controls the on−time by comparing an internal voltage ramp, Von−time, to the feedback voltage. The internal ramp is generated by charging an internal capacitor with a fixed current source. The slope of the ramp is adjusted by the user using an external timing resistor, RT, between the RT and GND pins. The architecture of the on−time control circuitry is shown in Figure 4. www.onsemi.com 9 NCL30060 VCC Clamp S Q Reset Dominant Latch Q R PWM Max On Time Comparator DRV FB Offset Vton(MAX) Clamp Von−time ACTIVE IRT Ramp Modulation On Time DRV Ramp ton(mod) RCS IRT(disable) * RCS RT Disable Comparator RT Mirror + VPRT − + Delay tdisable(blank)/ tenable(blank) Current fMOD RT Enable Comparator + FB − ACTIVE GND UVLO Max On−Time Comparator VDD2 DRV ACTIVE VRT(enable) − Figure 4. On−Time Control Architecture The on−time is internally modulated to reduce the EMI signature of the controller. The modulation is accomplished by modulating the charge current using an internal triangle wave oscillator. The charge current is adjusted ±6% from the nominal value. The EMI signature of the controller is spread over a wide range of frequencies eliminating high peaks during an average reading. Version NCL30060B4 can be selected for some applications not requiring modulation of the control loop or output short circuit protection. The absolute maximum on−time determines the maximum power of the system. The NCL30060 accurately controls the maximum on−time of the system by the Max On−time Clamp circuits. It ensures that On−time can’t exceed ton(MAX), typically 27.5 ms, when the RT resister value is above 110 kW. There is also a fixed voltage reference, Vton(MAX), which defines the maximum effective VFB voltage. Given a certain RT value between 10 kW and 110 kW, the Maximum On−time Comparator controls the on−time when primary side regulation is required. This could occur during an overload condition or during startup when the feedback signal is not present. The relationship between RT and ton(MAX) is given by Equation 2 and Figure 5. t on(MAX) + 0.25 @ R T Figure 5. Maximum On−Time vs RT The RT pin has a threshold output current of IRT(disable) which has a maximum value of 400 mA. The maximum on−time is limited to 27.5 ms if the pin is left open or the Rt is higher than 110 kW. If the resistance between RT pin and GND is small enough to make the RT pin current higher than IRT(disable), the device is disabled after the blanking delay tdisable(blank) and the RT pin output current is switched to IRT(dis) which has 50 mA typical value. After the device is disabled, the integrated HV source maintains VCC above (eq. 2) Where ton(MAX) is in ms and RT is in kW. www.onsemi.com 10 NCL30060 CURRENT SENSE, ZERO CURRENT AND OVERVOLTAGE DETECTION VCC(min). The IC is activated when the voltage of the RT pin is higher than the VRT(enable), which has typical value of 400 mV. And the RT pin output current is switched back to normal operation, and the RT voltage is regulated to VRT(REG),which has a typical value of 2 V. The timing resistor should be placed as close as possible to the RT and GND pins with short trace lengths. Care should be taken to keep switching nodes (high dv/dt) away from RT to reduce noise pickup. The NCL30060 uses a novel architecture combining the current sense, the zero current detector (ZCD), output overvoltage and shorted output detector functions in a single terminal. Figure 6 shows the circuit schematic of the current sense and ZCD detectors. Peak Current DRV Comparator LEB tCS(LEB1) + Short Winding Comparator − Counter VCC VILIM1 Count VILIM2 ILIM2 − toff1,2 Timer UVLO Disable Reset Re−start ILIM2, OVP DRV Edge + Selector VCC ZCD Comparator VZCD HV(high) Detector − DRV + Reset CS/ZCD LEB tCS(LEB2) Edge Detector TSHDN ZCD Blanking Time DRV VCC Clamp S Q Reset Dominant Latch Q R DRV ACTIVE UVLO GND Figure 6. Current Sense and ZCD Detectors Schematic CURRENT SENSE The NCL30060 protects against this fault by adding an additional comparator, Short Circuit Comparator. The current sense signal is blanked with a shorter LEB duration, tCS(LEB2), typically 125 ns, before applying it to the Short Circuit Comparator. The voltage threshold of the comparator, VILIM2, typically 0.5 V, is set twice the level of VILIM1, to avoid interference with normal operation. Four consecutive faults detected by the Short Circuit Comparator causes the controller to enter a fault mode. The NCL30060B will auto−recover from the fault state if the short is removed. The count to 4 provides noise immunity during surge testing. The counter is reset each time a DRV pulse occurs without activating the Short Circuit Comparator. The watchdog timer duration (toff2) is increased to 1.25 ms independent of the PFC ZCD state. The Switch current is sensed across a sense resistor, Rsense, and the resulting voltage ramp is applied to the CS/ZCD pin. The current signal is blanked by a leading edge blanking (LEB) circuit. The blanking period eliminates the leading edge spike and high frequency noise during the switch turn−on event. The LEB period, tCS(LEB1), is typically 325 ns. The Current Limit Comparator disables the driver once the current sense signal exceeds the current sense reference, VILIM1, typically 0.25 V. The next switching cycle is initiated by the ZCD or watchdog timer. A severe overload fault like a secondary side winding short circuit causes the switch current to increase very rapidly during the on−time. The current sense signal significantly exceeds VILIM1. But, because the current sense signal is blanked by the LEB circuit during the switch turn on, the current could damage the system. www.onsemi.com 11 NCL30060 Figure 7. Secondary Side Winding Short−Circuit Waveforms Figure 7 shows simulation results for an output winding short. The simulation waveforms are described below: ♦ DRV/V is gate drive signal for the PFC switch. ♦ VCS/V is the signal on the CS/ZCD pin. ♦ ZCDW/V is the voltage across the ZCD winding. ♦ VHV1/V is the voltage on the HV pin. The converter is operating normally and a momentary fault is applied at 24 ms. Once the fault is applied, the watchdog timer duration increases to toff2. The fault is removed after two faults overcurrent events are detected. The fault is re−applied at 35 ms. After four consecutive overcurrent conditions are detected, the fault signal goes high. Rzcd Dzcd Switch DRV CS/ZCD Rcs Rsense Figure 8. ZCD Winding Implementation ZERO CURRENT DETECTION The off−time in a CrM topology varies with the instantaneous line voltage and it is adjusted every cycle to allow the inductor current to reach zero before the next switch cycle begins. The inductor is demagnetized once its current reaches zero. Once the inductor is demagnetized the drain voltage of the switch begins to fall. The inductor demagnetization is detected by sensing the voltage across the inductor using an auxiliary winding. This winding is commonly known as a zero crossing detector (ZCD) winding. This winding provides a scaled version of the drain voltage. Figure 8 shows the ZCD winding arrangement. The ZCD voltage, VCS/ZCD, is positive while the Switch is off and current flows on the secondary side. VCS/ZCD drops to and rings around zero volts once the transformer is demagnetized. The next switch cycle commences once a negative going transition is detected in the CS/ZCD pin. A positive transition (corresponding to the switch turn off) arms the ZCD detector to prevent false triggering. The arming of the ZCD detector, VZCD(ARM), is typically 250 mV (VCS/ZCD increasing). The trigger threshold, VZCD(TRIG), is typically 55 mV (VCS/ZCD decreasing). www.onsemi.com 12 NCL30060 controller shutting down after an overvoltage condition is detected. The NCL30060 incorporates a minimum off−time delay, tARM(blank).,typically 2.0 ms . This delay blanks the ringing which may be present on the bias winding during start up or if the output of the converter is shorted. The next DRV pulse is initiated once tARM(blank) expires if a ZCD transition is detected prior to the delay expiring. Otherwise, it will initiate on the ZCD transition after tARM(blank) expires. In the absence of a ZCD transition, the watchdog timer initiates the next drive pulse. The CS/ZCD pin is internally clamped to VCC thru an internal diode. A 7.4 V Zener diode with a 1 kW resistor to GND also clamp the pin. A resistor in series with the CS/ZCD pin is required to limit the current into pin. The Zener diode also prevents the voltage from going below ground. Figure 9 shows typical ZCD waveforms. Figure 10. Overvoltage Detection Operating Waveforms OUTPUT SHORT CIRCUIT DETECTION When the converter is operating with low output voltage, the off−time is extended in CrM operation. In Figure 11 of the output short detection function block, the maximum off−time detector signals when the off time is longer than 50 ms. This 50 ms off time detection triggers a 150 ms pulse to feed the integrator. The integrator has a weighted integration feature, which makes the charging 20 times faster than the discharging. A continuous stream of 150 ms pulses will reach the integrator threshold in 40ms. Periods of time without triggering the 150 ms timer will extend the time to reach the threshold. The integrator discharges as the relative number of 150 ms pulses over time decreases. Figure 9. ZCD Winding Waveforms During startup there are no ZCD transitions to set the PWM Latch and generate a DRV pulse. A watchdog timer, toff1, starts the drive pulses in the absence of ZCD transitions. Its duration is typically 200 ms. The timer is also useful during startup and while operating at light load because the amplitude of the ZCD signal may be very small to cross the ZCD thresholds. The watchdog timer is reset at the beginning of a drive pulse. It is disabled if the CS/ZCD pin is above the ZCD arming threshold. The watchdog timer duration increases to toff2, typically 1.25 ms, when a VILIM2 fault is detected. OVERVOLTAGE PROTECTION Figure 11. Output Short−Circuit Detector Output overvoltage protection (OVP) is provided by monitoring the CS/ZCD pin during the off−time. A dedicated comparator compares the voltage on CS/ZCD pin to an internal reference, VOVP, typically 6 V. If 4 consecutive OVP events are detected the controller enters a fault mode. A 2 ms blanking delay, tOVP(blank), blanks the signal CS/ZCD signal after the drive turns off to blank ringing generated by system parasitics. The blanking provides protection during power up and steady state operation. Figure 10 shows the When the threshold is reached, the system will determine there is an output short event. The system enters into fault mode. The NCL30060B will try to auto−recover after a 1 sec typical delay. This minimizes system power consumption due to the output short event. Figure 12 shows auto−restart operating waveforms. www.onsemi.com 13 NCL30060 sensed voltage to cross the startup threshold if switching is abruptly terminated. A false startup level would be followed by crossing the shutdown threshold again. Such cycling on and off near the brown out threshold would result in LED flicker. Allowing the energy to discharge naturally near the zero crossing provides a clean brown out shutdown. MOSFET DRIVER The NCL30060 maximum supply voltage, VCC(OVP), is 28 V. Typical high voltage MOSFETs have a maximum gate voltage rating of 20 V. The driver incorporates an active voltage clamp to limit the gate voltage on the external MOSFET. The voltage clamp, VDRV(high), is typically 12 V with a maximum limit of 14 V. Figure 12. Output Short Detection and Protection Waveform Versions NCL30060B2 and NCL30060B4 are intended for constant voltage (CV) regulated output drivers where a DC−DC converter or linear regulator in the second stage controls the current to the LEDs so the output short circuit protection detector function has been disabled. Version NCL30060B3 is useful in applications where the Brown Out function is not required and light load operation may trigger the output short circuit protection function. Ensure proper operation in fault modes. AUTO−RECOVERY The controller is disabled and enters a fault mode if VCC drops below VCC(UVLO) or a non−latching fault is detected. The controller auto−restarts after the auto−recovery timer tautorecovery, expires, typically 1 s. THERMAL SHUTDOWN An internal thermal shutdown circuit monitors the junction temperature of the IC. The controller including the startup circuit is disabled if the junction temperature exceeds the thermal shutdown threshold, TSHDN, typically 150 _C. Once a thermal shutdown condition is validated, the startup circuit is disabled. The startup circuit is enabled once VCC falls below VCC(reset), charging VCC up to VCC(on). The controller remains disabled if the thermal shutdown is present upon reaching VCC(on). The controller restarts at the next VCC(on) once the IC temperature drops below TSHDN by the thermal shutdown hysteresis, TSHDN(HYS), typically 40_C. BROWN OUT DETECTION The NCL30060 includes brown out protection providing a defined shutdown for low input voltage. This feature is enabled after a VCC reset event and does not allow the controller to enter Active mode until the input voltage is above the startup threshold, typically 111 V. If the input voltage remains below the system shutdown threshold, typically 96 V, longer than the brown out detection blanking time, typically 54 ms, a shutdown flag is set. Gate drive pulses will continue to be issued until the input voltage is near the ac line voltage zero crossing. When a zero crossing is detected and the flag is set, gate drive pulses cease thereby stopping power delivery to the LED load. The brown out flag remains set and switching is suspended until the input voltage rises above the startup threshold. Delaying termination of gate drive pulses until the zero crossing ensures the system is at a low power state before shutting down. This approach avoids a situation where energy stored in the input filter may artificially force the LAYOUT CONSIDERATIONS The GND pin is the reference point for the controller. Unless specified otherwise, all measurements are made relative to this pin. Both power and control circuits use this reference. It is recommended to have short traces between this pin and control components to reduce parasitic inductance. ORDERING INFORMATION OCP Brown Out Output Short Detection On−Time Modulation NCL30060ADR2G* Latched Enabled Enabled Enabled NCL30060BDR2G Auto−recoverable Enabled Enabled Enabled NCL30060B1DR2G* Auto−recoverable Disabled Enabled Enabled NCL30060B2DR2G Auto−recoverable Enabled Disabled Enabled NCL30060B3DR2G Auto−recoverable Disabled Disabled Enabled NCL30060B4DR2G Auto−recoverable Enabled Disabled Disabled Ordering Part No. Package Shipping† SOIC−7 (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *Version available only by customer request. www.onsemi.com 14 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−7 CASE 751U−01 ISSUE E DATE 20 OCT 2009 SCALE 1:1 −A− 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B ARE DATUMS AND T IS A DATUM SURFACE. 4. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 5. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5 −B− S 0.25 (0.010) B M M 1 4 G C R X 45 _ J −T− SEATING PLANE H 0.25 (0.010) K M D 7 PL M T B S A DIM A B C D G H J K M N S INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 S GENERIC MARKING DIAGRAM SOLDERING FOOTPRINT* 8 1.52 0.060 7.0 0.275 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 1 XXX A L Y W G 4.0 0.155 0.6 0.024 = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. 1.270 0.050 SCALE 6:1 XXXXX ALYWX G mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: 98AON12199D DESCRIPTION: 7−LEAD SOIC Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−7 CASE 751U−01 ISSUE E STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. 7. NOT USED 8. EMITTER DATE 20 OCT 2009 STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. NOT USED 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. NOT USED 8. SOURCE, #1 STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. 6. 7. NOT USED 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. 7. NOT USED 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. NOT USED 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR (DIE 1) 2. BASE (DIE 1) 3. BASE (DIE 2) 4. COLLECTOR (DIE 2) 5. COLLECTOR (DIE 2) 6. EMITTER (DIE 2) 7. NOT USED 8. COLLECTOR (DIE 1) STYLE 9: PIN 1. EMITTER (COMMON) 2. COLLECTOR (DIE 1) 3. COLLECTOR (DIE 2) 4. EMITTER (COMMON) 5. EMITTER (COMMON) 6. BASE (DIE 2) 7. NOT USED 8. EMITTER (COMMON) STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. NOT USED 8. GROUND STYLE 11: PIN 1. SOURCE (DIE 1) 2. GATE (DIE 1) 3. SOURCE (DIE 2) 4. GATE (DIE 2) 5. DRAIN (DIE 2) 6. DRAIN (DIE 2) 7. NOT USED 8. DRAIN (DIE 1) STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. NOT USED 8. COMMON CATHODE DOCUMENT NUMBER: 98AON12199D DESCRIPTION: 7−LEAD SOIC Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. 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