NCL30080
Quasi-Resonant Primary
Side Current-Mode
Controller for LED Lighting
The NCL30080 is a PWM current mode controller targeting isolated
flyback and non−isolated constant current topologies. The controller
operates in a quasi−resonant mode to provide high efficiency. Thanks
to a novel control method, the device is able to precisely regulate a
constant LED current from the primary side. This removes the need
for secondary side feedback circuitry, biasing and an optocoupler.
The device is highly integrated with a minimum number of external
components. A wide VCC range simplifies the design process and
allows a single design to support a wide LED forward voltage range. A
robust suite of safety protection is built in to simplify the design. This
device is specifically intended for very compact space efficient
designs.
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1
TSOP−6
SN SUFFIX
CASE 318G
MARKING DIAGRAM
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
AAxAYWG
Quasi−resonant Peak Current−mode Control Operation
G
Primary Side Sensing (no optocoupler needed)
1
Wide VCC Range
AAx = Specific Device Code
Precise LED Constant Current Regulation ±1% Typical
x
= E or Z
Line Feed−forward for Enhanced Regulation Accuracy
A
= Assembly Location
Y
= Year
Low LED Current Ripple
W
= Work Week
250 mV ±2% Guaranteed Voltage Reference for Current Regulation
G
= Pb−Free Package
~ 0.9 Power Factor with Valley Fill Input Stage
(Note: Microdot may be in either location)
Low LED Current Ripple
Source 300 mA / Sink 500 mA Totem Pole Driver with 12 V Gate
PIN CONNECTIONS
Clamp
1
Low Start−up Current (13 mA typ.)
ZCD
VIN
Small Space Saving Low Profile Package
GND
VCC
Wide Temperature Range of −40 to +125°C
DRV
CS
Pb−free, Halide−free MSL1 Product
(Top View)
Robust Protection Features
♦ Over Voltage / LED Open Circuit Protection
♦ Secondary Diode Short Protection
♦ Output Short Circuit Protection
Typical Applications
♦ Shorted Current Sense Pin Fault Detection
• Integral LED Bulbs
♦ Latched and Auto−recoverable Versions
• LED Power Driver Supplies
♦ Brown−out
♦ VCC Under Voltage Lockout
• LED Light Engines
♦ Thermal Shutdown
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 25 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
January, 2015 − Rev. 3
1
Publication Order Number:
NCL30080/D
NCL30080
.
.
Aux
.
1
6
2
5
3
4
Figure 1. Typical Application Schematic for NCL30080
Table 1. PIN FUNCTION DESCRIPTION
Pin No
Pin Name
Function
Pin Description
1
ZCD
Zero Crossing Detection
2
GND
−
3
CS
Current sense
This pin monitors the primary peak current
4
DRV
Driver output
The current capability of the totem pole gate drive (+0.3/−0.5 A) makes it suitable to effectively drive a broad range of power MOSFETs.
5
VCC
Supplies the controller
This pin is connected to an external auxiliary voltage.
6
VIN
Input voltage sensing
Brown−Out
This pin observes the HV rail and is used in valley selection. This pin also
monitors and protects for low mains conditions.
Connected to the auxiliary winding; this pin detects the core reset event.
The controller ground
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2
NCL30080
VDD
STOP
Aux_SCP
GND
OFF
UVLO
Latch
Fault
Management
CS_shorted
Internal
Thermal
Shutdown
VCC_max
Ipkmax
VREF
VCC
VCC Management
VCC Over Voltage
Protection
WOD_SCP
BO_NOK
Qdrv
ZCD
VVIN
Clamp
Circuit
Zero Crossing Detection
Valley Selection
Aux. Winding
Short Circuit Protection
S
Aux_SCP
Q
VVIN
DRV
Qdrv
VVLY
R
Line
Feedforward
CS
VCC
STOP VREF
Leading
Edge
Blanking
CS_reset
Constant−Current
Control
VVIN
Ipkmax
VVIN
Max. Peak
Current
Limit
Ipkmax
CS Short
Protection
CS_shorted
Winding and
Output diode
Short Circuit
Protection
STOP
VIN
BO_NOK
WOD_SCP
Figure 2. Internal Circuit Architecture
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Brown−Out
NCL30080
Table 2. MAXIMUM RATINGS TABLE
Symbol
Rating
Value
Unit
VCC(MAX)
ICC(MAX)
Maximum Power Supply voltage, VCC pin, continuous voltage
Maximum current for VCC pin
−0.3, +35
Internally limited
V
mA
VDRV(MAX)
IDRV(MAX)
Maximum driver pin voltage, DRV pin, continuous voltage
Maximum current for DRV pin
−0.3, VDRV (Note 1)
−500, +800
V
mA
VMAX
IMAX
Maximum voltage on low power pins (except pins DRV and VCC)
Current range for low power pins (except pins ZCD, DRV and VCC)
−0.3, +5.5
−2, +5
V
mA
VZCD(MAX)
IZCD(MAX)
Maximum voltage for ZCD pin
Maximum current for ZCD pin
−0.3, +10
−2, +5
V
mA
RθJ−A
Thermal Resistance, Junction−to−Air
360
°C/W
TJ(MAX)
Maximum Junction Temperature
150
°C
Operating Temperature Range
−40 to +125
°C
Storage Temperature Range
−60 to +150
°C
ESD Capability, HBM model (Note 2)
4
kV
ESD Capability, MM model (Note 2)
200
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. VDRV is the DRV clamp voltage VDRV(high) when VCC is higher than VDRV(high). VDRV is VCC unless otherwise noted.
2. This device series contains ESD protection and exceeds the following tests: Human Body Model 4000 V per JEDEC JESD22−A114−F and
Machine Model Method 200 V per JEDEC JESD22−A115−A.
3. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78 except for VIN pin which passes 60 mA.
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NCL30080
Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V;
For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V)
Description
Test Condition
Symbol
Min
Typ
Max
Unit
VCC increasing
VCC decreasing
VCC decreasing
VCC(on)
VCC(off)
VCC(HYS)
VCC(reset)
16
8.2
8
3.5
18
8.8
–
4.5
20
9.4
–
5.5
Over Voltage Protection
VCC OVP threshold
VCC(OVP)
26
28
30
V
VCC(off) noise filter
VCC(reset) noise filter−
tVCC(off)
tVCC(reset)
–
–
5
20
–
–
ms
ICC(start)
–
13
30
mA
ICC(sFault)
–
46
60
mA
ICC1
ICC2
ICC3
0.8
–
–
1.0
2.15
2.6
1.4
4.0
5.0
Maximum Internal current limit
VILIM
0.95
1
1.05
V
Leading Edge Blanking Duration for VILIM
(Tj = −25°C to 125°C)
tLEB
250
300
350
ns
Leading Edge Blanking Duration for VILIM
(Tj = −40°C to 125°C)
tLEB
240
300
350
ns
Ibias
–
0.02
–
mA
tILIM
–
50
150
ns
VCS(stop)
1.35
1.5
1.65
V
tBCS
–
120
–
ns
Blanking time for CS to GND short detection VpinVIN = 1 V
tCS(blank1)
8.0
–
14
ms
Blanking time for CS to GND short detection VpinVIN = 3.3 V
tCS(blank2)
2.6
–
4.6
ms
Drive Resistance
DRV Sink
DRV Source
RSNK
RSRC
–
–
13
30
–
–
Drive current capability
DRV Sink (Note 4)
DRV Source (Note 4)
ISNK
ISRC
–
–
500
300
–
–
STARTUP AND SUPPLY CIRCUITS
Supply Voltage
Startup Threshold
Minimum Operating Voltage
Hysteresis VCC(on) – VCC(off)
Internal logic reset
V
Startup current
Startup current in fault mode
Supply Current
Device Disabled/Fault
Device Enabled/No output load on pin 4
Device Switching (Fsw = 65 kHz)
mA
VCC > VCC(off)
Fsw = 65 kHz
CDRV = 470 pF,
Fsw = 65 kHz
CURRENT SENSE
Input Bias Current
DRV high
Propagation delay from current detection to gate off−state
Threshold for immediate fault protection activation
Leading Edge Blanking Duration for VCS(stop)
GATE DRIVE
W
mA
Rise Time (10% to 90%)
CDRV = 470 pF
tr
–
40
–
ns
Fall Time (90% to 10%)
CDRV = 470 pF
tf
–
30
–
ns
DRV minimum high level
VCC = VCC(off)+0.2 V
CDRV = 470 pF,
RDRV = 33 kW
VDRV(low)
8
–
–
V
VCC = 30 V
CDRV = 470 pF,
RDRV = 33 kW
VDRV(high)
10
12
14
V
DRV high clamp level
4. Guaranteed by design
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NCL30080
Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V;
For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V)
Description
Test Condition
Symbol
Min
Typ
Max
Unit
ZCD threshold voltage
VZCD increasing
VZCD(THI)
25
45
65
mV
ZCD threshold voltage (Note 4)
VZCD decreasing
VZCD(THD)
5
25
45
mV
ZCD hysteresis (Note 4)
VZCD(HYS)
10
–
–
mV
Threshold voltage for output short circuit or aux. winding
short circuit detection
VZCD(short)
0.8
1
1.2
V
tOVLD
70
90
110
ms
trecovery
3
4
5
s
Ipin1 = 3.0 mA
Ipin1 = −2.0 mA
VCH
VCL
–
−0.9
9.5
−0.6
–
−0.3
VZCD decreasing
tDEM
–
–
150
ns
tPAR
–
20
–
ns
tBLANK
2.25
3
3.75
ms
tTIMO
5
6.5
8
ms
Reference Voltage at Tj = 25°C
VREF
245
250
255
mV
Reference Voltage Tj = −40°C to 125°C
VREF
242.5
250
257.5
mV
VCS(low)
30
55
80
mV
KLFF
15
17
19
mA/V
VpinVIN = 4.5 V
Ioffset(MAX)
67.5
76.5
85.5
mA
Threshold for line range detection Vin increasing
(1st to 2nd valley transition for VREF > 0.75 V)
VVIN increasing
VHL
2.28
2.4
2.52
V
Threshold for line range detection Vin decreasing
(2nd to 1st valley transition for VREF > 0.75 V)
VVIN decreasing
VLL
2.18
2.3
2.42
V
tHL(blank)
15
25
35
ms
TSHDN
130
155
170
°C
TSHDN(HYS)
–
55
–
°C
ZERO VOLTAGE DETECTION CIRCUIT
Short circuit detection Timer
VZCD < VZCD(short)
Auto−recovery timer duration
Input clamp voltage
High state
Low state
Propagation Delay from valley detection to DRV high
V
Equivalent time constant for ZCD input (Note 4)
Blanking delay after on−time
Timeout after last demag transition
CONSTANT CURRENT CONTROL
Current sense lower threshold for detection of the
leakage inductance reset time
LINE FEED−FORWARD
VVIN to ICS(offset) conversion ratio
Offset current maximum value
VALLEY SELECTION
Blanking time for line range detection
THERMAL SHUTDOWN
Thermal Shutdown (Note 4)
Device switching
(FSW around 65 kHz)
Thermal Shutdown Hysteresis (Note 4)
BROWN−OUT
Brown−Out ON level (IC start pulsing)
VSD increasing
VBO(on)
0.90
1
1.10
V
Brown−Out OFF level (IC shuts down)
VSD decreasing
VBO(off)
0.85
0.9
0.95
V
BO comparators delay
tBO(delay)
–
30
–
ms
Brown−Out blanking time
tBO(blank)
35
50
65
ms
Brown−Out pin bias current
IBO(bias)
−250
–
250
nA
4. Guaranteed by design
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NCL30080
TYPICAL CHARACTERISTICS
18.15
8.85
18.10
VCC(off) (V)
VCC(on) (V)
8.80
18.05
18.00
8.75
8.70
17.95
17.90
−40
−20
0
20
40
60
80
8.65
−40
120
100
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 3. VCC(on) vs. Junction Temperature
Figure 4. VCC(off) vs. Junction Temperature
27.80
1.09
27.75
1.07
1.05
27.65
ICC1 (mA)
VCC(OVP) (V)
27.70
27.60
27.55
1.03
1.01
27.50
0.99
27.45
0.97
27.40
−40
−20
0
20
40
60
80
100
0.95
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. VCC(OVP) vs. Junction Temperature
Figure 6. ICC1 vs. Junction Temperature
2.20
120
2.70
2.65
2.60
ICC3 (mA)
ICC2 (mA)
2.15
2.10
2.55
2.50
2.45
2.05
2.40
2.00
−40
−20
0
20
40
60
80
100
2.35
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 7. ICC2 vs. Junction Temperature
Figure 8. ICC3 vs. Junction Temperature
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120
NCL30080
TYPICAL CHARACTERISTICS
54
19
52
50
ICC(sFault) (mA)
ICC(start) (mA)
17
15
13
48
46
44
42
11
40
9
−40
−20
0
20
40
60
80
38
−40
120
100
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 9. ICC(start) vs. Junction Temperature
Figure 10. ICC(sFault) vs. Junction Temperature
1.51
1.002
1.000
1.50
0.998
1.49
VILIM (V)
VCS(stop) (V)
−20
1.48
0.996
0.994
1.47
0.992
1.46
−40
−20
0
20
40
60
80
100
0.990
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 11. VCS(stop) vs. Junction Temperature
Figure 12. VILIM vs. Junction Temperature
305
120
3.00
303
301
2.98
tBLANK (ms)
tLEB (ns)
299
297
295
293
2.96
2.94
291
2.92
289
287
285
−40
−20
0
20
40
60
80
100
2.90
−40
120
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 13. tLEB vs. Junction Temperature
Figure 14. tBLANK vs. Junction Temperature
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NCL30080
TYPICAL CHARACTERISTICS
6.80
254
253
6.70
252
VREF (mV)
tTIMO (ms)
6.60
6.50
6.40
251
250
249
248
6.30
247
6.20
−40
−20
0
20
40
60
80
100
246
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 15. tTIMO vs. Junction Temperature
Figure 16. VREF vs. Junction Temperature
55.8
120
17.65
55.6
17.60
55.2
KLFF (mA/V)
VCS(low) (mV)
55.4
55.0
54.8
54.6
17.55
17.50
17.45
54.4
54.2
−40
−20
0
20
40
60
80
100
17.40
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 17. VCS(low) vs. Junction Temperature
Figure 18. KLFF vs. Junction Temperature
2.42
120
2.30
2.41
2.29
VLL (V)
VHL (V)
2.40
2.39
2.28
2.38
2.27
2.37
2.36
−40
−20
0
20
40
60
80
100
2.26
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 19. VHL vs. Junction Temperature
Figure 20. VLL vs. Junction Temperature
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120
NCL30080
25.5
1.000
25.0
0.995
VBO(on) (V)
tHL(BLANK) (ms)
TYPICAL CHARACTERISTICS
24.5
24.0
0.990
0.985
0.980
23.5
23.0
−40
−20
0
20
40
60
80
100
0.975
−40
120
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 21. tHL(BLANK) vs. Junction Temperature
Figure 22. VBO(on) vs. Junction Temperature
0.910
53.5
53.0
tBO(BLANK) (ms)
VBO(off) (V)
0.905
0.900
0.895
52.5
52.0
51.5
51.0
50.5
0.890
−40
−20
0
20
40
60
80
100
50.0
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 23. VBO(off) vs. Junction Temperature
Figure 24. tBO(BLANK) vs. Junction
Temperature
120
4.40
85.0
84.5
4.35
84.0
4.30
trecovery (s)
tOVLD (ms)
83.5
83.0
82.5
82.0
4.25
4.20
4.15
81.5
4.10
81.0
80.5
−40
−20
0
20
40
60
80
100
4.05
−40
120
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 25. tOVLD vs. Junction Temperature
Figure 26. trecovery vs. Junction Temperature
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NCL30080
Application Information
• Brown−Out: the controller includes a brown−out
The NCL30080 implements a current−mode architecture
operating in quasi−resonant mode. Thanks to proprietary
circuitry, the controller is able to accurately regulate the
secondary side current of the flyback converter without
using any opto−coupler or measuring directly the secondary
side current.
• Quasi−Resonance Current−Mode Operation:
implementing quasi−resonance operation in peak
current−mode control, the NCL30080 optimizes the
efficiency by switching in the valley of the MOSFET
drain−source voltage. Thanks to a smart control
algorithm, the controller locks−out in a selected valley
and remains locked until the input voltage or the output
current set point significantly changes.
• Primary Side Constant Current Control: thanks to a
proprietary circuit, the controller is able to compensate
for the leakage inductance of the transformer and allow
accurate control of the secondary side current.
• Line Feed−forward: compensation for possible
variation of the output current caused by system slew
rate variation.
• Open LED protection: if the voltage on the VCC pin
exceeds an internal limit, the controller shuts down and
waits 4 seconds before restarting switching.
•
•
•
circuit with a validation timer which safely stops the
controller in the event that the input voltage is too low.
The device will automatically restart if the line recovers.
Cycle−by−cycle peak current limit: when the current
sense voltage exceeds the internal threshold VILIM, the
MOSFET is turned off for the rest of the switching cycle.
Winding Short−Circuit Protection: an additional
comparator with a short LEB filter (tBCS) senses the CS
signal and stops the controller if VCS reaches 1.5 x
VILIM. For noise immunity reasons, this comparator is
enabled only during the main LEB duration tLEB.
Output Short−circuit protection: If a very low
voltage is applied on ZCD pin for 90 ms (nominal), the
controllers assume that the output or the ZCD pin is
shorted to ground and enters shutdown. The auto−
restart version (B suffix) waits 4 seconds, then the
controller restarts switching. In the latched version (A
suffix), the controller is latched as long as VCC stays
above the VCC(reset) threshold.
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NCL30080
Constant Current Control
Figure 27 shows the basic circuit of a flyback converter.
Figure 28 portrays the primary and secondary current of a
flyback converter operating in discontinuous conduction
mode (DCM).
Transformer
Vbulk
Lleak
Cclp
Nsp
Rclp
.
Lp
.
Clamping
network
DRV
Clump
Rsense
Figure 27. Basic Flyback Converter Schematic
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12
Vout
NCL30080
turned off, the drain voltage begins to oscillate because of
the resonating network formed by the inductors (Lp+Lleak)
and the lump capacitor. This voltage is reflected on the
auxiliary winding wired in flyback mode. Thus, by
monitoring the auxiliary winding voltage, we can detect the
end of the conduction time of secondary diode. The constant
current control block picks up the leakage inductor current,
the end of conduction of the output rectifier and controls the
drain current to maintain the output current constant.
We have:
During the on−time of the MOSFET, the bulk voltage
Vbulk is applied to the magnetizing and leakage inductors Lp
and Lleak and the current ramps up.
When the MOSFET is turned−off, the inductor current
first charges Clump. The output diode is off until the voltage
across Lp reverses and reaches:
N spǒV out ) V fǓ
(eq. 1)
The output diode current increase is limited by the leakage
inductor. As a result, the secondary peak current is reduced:
I D,pk t
I L,pk
I out +
(eq. 2)
N sp
V REF
2N spR sense
(eq. 3)
The output current value is set by choosing the sense
resistor:
The diode current reaches its peak when the leakage inductor
is reset. Thus, in order to accurately regulate the output
current, we need to take into account the leakage inductor
current. This is accomplished by sensing the clamping
network current. Practically, a node of the clamp capacitor
is connected to Rsense instead of the bulk voltage Vbulk.
Then, by monitoring the voltage on the CS pin, we have an
image of the primary current (red curve in Figure 28).
When the diode conducts, the secondary current decreases
linearly from ID,pk to zero. When the diode current has
R sense +
V ref
2N spI out
(eq. 4)
From Equation 3, the first key point is that the output
current is independent of the inductor value. Moreover, the
leakage inductance does not influence the output current
value as the reset time is processed by the controller.
IL,pk
NspID,pk
Ipri(t)
Isec(t)
time
t1
t2
ton
tdemag
Vaux(t)
time
Figure 28. Flyback Currents and Auxiliary Winding Voltage in DCM
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13
NCL30080
Internal Soft−Start
At startup or after recovering from a fault, there is a small
internal soft−start of 40 ms.
In addition, during startup, as the output voltage is zero
volts, the demagnetization time is long and the constant
current control block will slowly increase the peak current
towards its nominal value as the output voltage grows.
Figure 29 shows a soft−start simulation example for a 9 W
LED driver illustrating a natural soft startup.
16.0
(V)
12.0
1
Vout
2
I out
4
VControl
3
VCS
8.00
4.00
0
800m
(A)
600m
400m
200m
0
800m
(V)
600m
400m
200m
0
604u
1.47m
2.34m
time in seconds
3.21m
4.07m
Figure 29. Startup Simulation Showing the Natural Soft−start
Cycle−by−Cycle Current Limit
Winding and Output Diode Short−Circuit Protection
When the current sense voltage exceeds the internal
threshold VILIM, the MOSFET is turned off for the rest of the
switching cycle (Figure 30).
In parallel with the cycle−by−cycle sensing of the CS pin,
another comparator with a reduced LEB (tBCS) and a higher
threshold (1.5 V typical) is integrated to sense a winding
short−circuit and immediately stops the DRV pulses. The
controller goes into auto−recovery mode in version B.
In version A, the controller is latched. In latch mode, the
DRV pulses stop and VCC ramps up and down. The circuit
un−latches when VCC pin voltage drops below VCC(reset)
threshold.
www.onsemi.com
14
NCL30080
S
DRV
Q
Q
aux
Vdd
latch
CS
R
LEB1
Rsense
+
Vcontrol
Vcc
management
PWMreset
−
+
VCCstop
UVLO
grand
8_HICC
reset
Ipkmax
−
VILIMIT
OVP
LEB2
+
STOP
OVP
WOD_SCP
latch
−
S
VCS(stop)
Q
Q
OFF WOD_SCP
S
Q
Q
R
8_HICC
R
grand
reset
from Fault Management Block
Figure 30. Winding Short Circuit Protection, Max. Peak Current Limit Circuits
www.onsemi.com
15
VCC
NCL30080
VCC Over Voltage Protection (Open LED Protection)
In the NCL30080, when the VCC voltage reaches the
VCC(OVP) threshold, the controller stops the DRV pulses and
the 4−s timer starts counting. The IC re−start switching after
the 4−s timer has elapsed as long as VCC ≥ VCC(on). This is
illustrated in Figure 31.
If no output load is connected to the LED string fails open
circuited, the controller must be able to safely limit the
output voltage excursion.
40.0
V CC(OVP)
(V)
30.0
1 V CC
V CC(on)
20.0
10.0
VCC(off)
0
40.0
(V)
30.0
2 Vout
20.0
10.0
0
800m
(A)
600m
400m
200m
3 I out
0
8.00
(V)
6.00
4 OVP
4.00
2.00
0
1.38
3.96
6.54
time in seconds
9.11
Figure 31. Open LED Protection Chronograms
www.onsemi.com
16
11.7
NCL30080
Valley Lockout
valley until the input voltage varies significantly. This
avoids valley jumping and the inherent noise caused by this
phenomenon.
The input voltage is sensed by the VIN pin. The internal
logic selects the operating valley according to VIN pin
voltage (line range detection in Figure 32). For a universal
mains design, the controller operates in the first valley at low
line and in the second valley at high line.
Quasi−square wave resonant systems have a wide
switching frequency excursion. The switching frequency
increases when the output load decreases or when the input
voltage increases. The switching frequency of such systems
must be limited.
The NCL30080 changes the valley as the input voltage
increases. This limits the switching frequency excursion.
Once a valley is selected, the controller stays locked in the
Vbulk
VIN
+
LLine
25−ms blanking time
−
2.4 V if LLine low
2.3 V if LLine high
Figure 32. Line Range Detection
Table 4. VALLEY SELECTION
VIN pin voltage for valley change
VVIN decreases
0
−LL−
2.3 V
1st
Valley number
0
−LL−
−HL−
5V
2nd
2.4 V
−HL−
VVIN increases
VIN pin voltage for valley change
www.onsemi.com
17
5V
HLine
NCL30080
Zero Crossing Detection Block
the valleys. To avoid such a situation, the NCL30080
features a time-out circuit that generates pulses if the voltage
on ZCD pin stays below the VZCD(THD) threshold for 6.5 ms
(nominal).
The time-out also acts as a substitute clock for the valley
detection and simulates a missing valley in case of very
damped free oscillations.
The ZCD pin detects when the drain-source voltage of the
power MOSFET reaches a valley.
A valley is detected when the voltage on pin 1 crosses
below the VZCD(THD) internal threshold.
At startup or in case of extremely damped free
oscillations, the ZCD comparator may not be able to detect
V ZCD
3
4
V ZCD(THD)
The 3rd valley
is validated
high
14
2nd, 3rd
low
12
The 3rd valley is not detected
by the ZCD comp
The 2nd valley is detected
By the ZCD comparator
high
15 ZCD comp
low
high
low
16 TimeOut
Time−out circuit adds a pulse to
account for the missing 3rd valley
high
low
17
Clk
Figure 33. Time−out Chronograms
To avoid these scenarios, a protection circuit consisting of
a comparator and secondary timer starts counting when the
ZCD voltage is below the VZCD(short) threshold. If this timer
reaches 90 ms, the controller detects a fault and shutdown.
The auto−restart version (B suffix) waits 4 seconds, then the
controller restarts switching. In the latched version
(A suffix), the controller is latched as long as VCC stays
above the VCC(reset) threshold.
Normally with this type of time−out function, in the event
the ZCD pin or the auxiliary winding is shorted, the
controller could continue switching leading to improper
regulation of the LED current. Moreover during an output
short circuit, the controller will strive to maintain constant
current operation.
www.onsemi.com
18
NCL30080
Line Feed−forward
Because of internal and external propagation delays, the
MOSFET is not turned−off immediately when the current
set−point is reached. As a result, the primary peak current is
slightly higher than expected resulting in a small output
current error which can be compensated for during
component selection.
Normally this error would increase if the input line
voltage increased because the slew rate through the primary
inductance would increase. To compensate for the peak
current increase brought by the variation, a positive voltage
proportional to the line voltage is added to the current sense
signal. The amount of offset voltage can be adjusted using
the RLFF resistor as shown in Figure 34.
V CS(offset) + K LFFV pinVINR CS
(eq. 5)
The offset voltage is applied only during the MOSFET
on−time.
Bulk rail
VDD
VIN
CS
ICS(offset)
RCS
Rsense
Q_drv
Figure 34. Line Feed−forward Schematic
Brown−out
condition overrides the hiccup on VCC (VCC does not wait
to reach VCC(off)) and the IC immediately goes into startup
mode (ICC = ICC(start)). Note for most compact LED driver
applications, if a true line dropout occurs, the energy in the
input bulk capacitor will be discharged and the LED load
will turn off before the 50 ms timer expires.
In order to protect the supply against a very low input
voltage, the NCL30080 features a brown−out circuit with a
fixed ON/OFF threshold. The controller is allowed to start
if a voltage higher than 1 V is applied to the VIN pin and
shuts−down if the VIN pin voltage decreases and stays
below 0.9 V for 50 ms nominal. Exiting a brown−out
Vbulk
VIN
+
50−ms blanking time
−
1 V if BONOK high
0.9 V if BONOK low
Figure 35. Brown−out Circuit
www.onsemi.com
19
BO_NOK
NCL30080
160
(V)
120
VBulk
80.0
1
40.0
0
18.0
(V)
2
VCC(on)
16.0
14.0
VCC
12.0
VCC(off)
10.0
1.10
V BO(on)
(V)
900m
V BO(off)
700m
V pinVIN
500m
3
300m
8.00
50−ms Timer
(V)
6.00
BO_NOK low
=> Startup mode
4.00
2.00
BO_NOK
4
0
46.1m
138m
231m
time in seconds
323m
Figure 36. Brown−Out Chronograms (Valley Fill circuit is used)
www.onsemi.com
20
415m
NCL30080
CS Pin Short Circuit Protection
With a traditional controller, if the CS pin or the sense
resistor is shorted to ground, the driver will not be able to
turn off, leading to potential damage of the power supply. To
avoid this, the NCL30080 features a circuit to protect the
power supply against a short circuit of the CS pin. When the
MOSFET is on, if the CS voltage stays below VCS(low) after
the adaptive blanking timer has elapsed, the controller shuts
down and will attempt to restart on the next VCC hiccup.
Adaptative
Blanking Time
VVIN
Q_drv
CS
−
+
S
VCS(low)
Q
CS_short
Q
R
UVLO
BO_NOK
Figure 37. CS Pin Short Circuit Protection Schematic
Fault Management
In this mode, the DRV pulses are stopped. VCC voltage
decrease through the controller own consumption (ICC1).
For the output diode short circuit protection, the output /
aux. winding short circuit protection and the VCC OVP, the
controller waits 4 seconds (auto−recovery timer) and then
initiates a startup sequence (VCC ≥ VCC(on)) before
re−starting switching.
Latch Mode
This mode is activated by the output diode short−circuit
protection (WOD_SCP) and the Aux_SCP in version A
only.
In this mode, the DRV pulses are stopped and the
controller is latched. There are hiccups on VCC.
The circuit un−latches when VCC < VCC(reset).
OFF Mode
The circuit turns off whenever a major condition prevents
it from operating:
• Incorrect feeding of the circuit: “UVLO high”. The
UVLO signal becomes high when VCC drops below
VCC(off) and remains high until VCC exceeds VCC(on).
• VCC OVP
• Output diode short circuit protection: “WOD_SCP
high”
• Output / Auxiliary winding Short circuit protection:
“Aux_SCP high”
• Die over temperature (TSD)
• Brown−Out: “BO_NOK” high
• Pin CS short circuited to GND: “CS_short high”
www.onsemi.com
21
NCL30080
Reset
Timer has
finished
counting
VCC > VCC(on)
VCC < VCC(off)
or
BO_NOK ↓
VCC_OVP
BO_NOK high
or TSD
or CS_Short
Stop
4−s
Timer
VCC
Disch.
BO_NOK high
or TSD
or CS_Short
WOD_SCP
or Aux_SCP
or VCC_OVP
Run
With states: Reset
Stop
Run
VCC Disch.
4−s Timer
→
→
→
→
→
VCC < VCC(off)
Controller is reset, ICC = ICC(start)
Controller is ON, DRV is not switching
Normal switching
No switching, ICC = ICC1, waiting for VCC to decrease to VCC(off)
the auto−recovery timer is counting, VCC is ramping up and down between VCC(on) and VCC(off)
Figure 38. State Diagram for B Version Faults
www.onsemi.com
22
NCL30080
Reset
Timer has
finished
counting
VCC > VCC(on)
VCC < VCC(off)
or
BO_NOK ↓
VCC < VCC(reset)
4−s
Timer
VCC_OVP
BO_NOK high
or TSD
or CS_Short
Stop
VCC
Disch.
VCC_OVP
BO_NOK high
or TSD
or CS_Short
Latch
Run
WOD_SCP or
Aux_SCP
With states: Reset
Stop
Run
VCC Disch.
4−s Timer
Latch
→
→
→
→
→
→
VCC < VCC(off)
Controller is reset, ICC = ICC(start)
Controller is ON, DRV is not switching
Normal switching
No switching, ICC = ICC1, waiting for VCC to decrease to VCC(off)
the auto−recovery timer is counting, VCC is ramping up and down between VCC(on) and VCC(off)
Controller is latched off, VCC is ramping up and down between VCC(on) and VCC(off),
only VCC(reset) can release the latch.
Figure 39. State Diagram for A Version Faults
www.onsemi.com
23
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSOP−6
CASE 318G−02
ISSUE V
1
SCALE 2:1
D
H
ÉÉ
ÉÉ
6
E1
1
NOTE 5
5
2
L2
4
GAUGE
PLANE
E
3
L
b
SEATING
PLANE
C
DETAIL Z
e
DIM
A
A1
b
c
D
E
E1
e
L
L2
M
c
A
0.05
M
DATE 12 JUN 2012
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM
LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D
AND E1 ARE DETERMINED AT DATUM H.
5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.
A1
DETAIL Z
MIN
0.90
0.01
0.25
0.10
2.90
2.50
1.30
0.85
0.20
0°
MILLIMETERS
NOM
MAX
1.00
1.10
0.06
0.10
0.38
0.50
0.18
0.26
3.00
3.10
2.75
3.00
1.50
1.70
0.95
1.05
0.40
0.60
0.25 BSC
10°
−
STYLE 1:
PIN 1. DRAIN
2. DRAIN
3. GATE
4. SOURCE
5. DRAIN
6. DRAIN
STYLE 2:
PIN 1. EMITTER 2
2. BASE 1
3. COLLECTOR 1
4. EMITTER 1
5. BASE 2
6. COLLECTOR 2
STYLE 3:
PIN 1. ENABLE
2. N/C
3. R BOOST
4. Vz
5. V in
6. V out
STYLE 4:
PIN 1. N/C
2. V in
3. NOT USED
4. GROUND
5. ENABLE
6. LOAD
STYLE 5:
PIN 1. EMITTER 2
2. BASE 2
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
6. COLLECTOR 2
STYLE 6:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. EMITTER
5. COLLECTOR
6. COLLECTOR
STYLE 7:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. N/C
5. COLLECTOR
6. EMITTER
STYLE 8:
PIN 1. Vbus
2. D(in)
3. D(in)+
4. D(out)+
5. D(out)
6. GND
STYLE 9:
PIN 1. LOW VOLTAGE GATE
2. DRAIN
3. SOURCE
4. DRAIN
5. DRAIN
6. HIGH VOLTAGE GATE
STYLE 10:
PIN 1. D(OUT)+
2. GND
3. D(OUT)−
4. D(IN)−
5. VBUS
6. D(IN)+
STYLE 11:
PIN 1. SOURCE 1
2. DRAIN 2
3. DRAIN 2
4. SOURCE 2
5. GATE 1
6. DRAIN 1/GATE 2
STYLE 12:
PIN 1. I/O
2. GROUND
3. I/O
4. I/O
5. VCC
6. I/O
STYLE 13:
PIN 1. GATE 1
2. SOURCE 2
3. GATE 2
4. DRAIN 2
5. SOURCE 1
6. DRAIN 1
STYLE 14:
PIN 1. ANODE
2. SOURCE
3. GATE
4. CATHODE/DRAIN
5. CATHODE/DRAIN
6. CATHODE/DRAIN
STYLE 15:
PIN 1. ANODE
2. SOURCE
3. GATE
4. DRAIN
5. N/C
6. CATHODE
STYLE 16:
PIN 1. ANODE/CATHODE
2. BASE
3. EMITTER
4. COLLECTOR
5. ANODE
6. CATHODE
STYLE 17:
PIN 1. EMITTER
2. BASE
3. ANODE/CATHODE
4. ANODE
5. CATHODE
6. COLLECTOR
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
6X
0.60
XXXAYWG
G
1
6X
3.20
XXX
A
Y
W
G
0.95
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB14888C
TSOP−6
1
IC
0.95
XXX MG
G
= Specific Device Code
=Assembly Location
= Year
= Work Week
= Pb−Free Package
STANDARD
XXX = Specific Device Code
M
= Date Code
G
= Pb−Free Package
*This information is generic. Please refer to device data sheet
for actual part marking. Pb−Free indicator, “G” or microdot “
G”, may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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