NCL30081
Dimmable Quasi-Resonant
Primary Side Current-Mode
Controller for LED Lighting
The NCL30081 is a PWM current mode controller targeting isolated
flyback and non−isolated constant current topologies. The controller
operates in a quasi−resonant mode to provide high efficiency. Thanks
to a novel control method, the device is able to precisely regulate a
constant LED current from the primary side. This removes the need
for secondary side feedback circuitry, biasing and an optocoupler.
The device is highly integrated with a minimum number of external
components. A robust suite of safety protection is built in to simplify
the design. This device is specifically intended for very compact space
efficient designs. It supports step dimming by monitoring the AC line
and detecting when the line has been toggled on−off−on by the user to
reduce the light intensity in 5 steps down to 5% dimming.
www.onsemi.com
1
TSOP−6
SN SUFFIX
CASE 318G
MARKING DIAGRAM
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
AAxAYWG
Quasi−resonant Peak Current−mode Control Operation
G
Primary Side Sensing (no optocoupler needed)
1
Wide VCC Range
AAx = Specific Device Code
Precise LED Constant Current Regulation ±1% Typical
x
= G or H
Line Feed−forward for Enhanced Regulation Accuracy
A
= Assembly Location
Y
= Year
Low LED Current Ripple
W
= Work Week
250 mV ±2% Guaranteed Voltage Reference for Current Regulation
G
= Pb−Free Package
~ 0.9 Power Factor with Valley Fill Input Stage
(Note: Microdot may be in either location)
Low Start−up Current (10 mA typ.)
Small Space Saving Low Profile Package
PIN CONNECTIONS
5 State Quasi−log Dimmable
1
Wide Temperature Range of −40 to +125°C
ZCD
VIN
Pb−free, Halide−free MSL1 Product
GND
VCC
Robust Protection Features
DRV
CS
♦ Over Voltage / LED Open Circuit Protection
(Top View)
♦ Secondary Diode Short Protection
♦ Output Short Circuit Protection
♦ Shorted Current Sense Pin Fault Detection
Typical Applications
♦ Latched and Auto−recoverable Versions
• Integral LED Bulbs
♦ Brown−out
• LED Power Driver Supplies
♦ VCC Under Voltage Lockout
• LED Light Engines
♦ Thermal Shutdown
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 30 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
January, 2015 − Rev. 1
1
Publication Order Number:
NCL30081/D
NCL30081
.
.
Aux
.
1
6
2
5
3
4
Figure 1. Typical Application Schematic for NCL30081
Table 1. PIN FUNCTION DESCRIPTION
Pin No
Pin Name
Function
Pin Description
1
ZCD
Zero Crossing Detection
2
GND
−
3
CS
Current sense
This pin monitors the primary peak current
4
DRV
Driver output
The current capability of the totem pole gate drive (+0.3/−0.5 A) makes it suitable to effectively drive a broad range of power MOSFETs.
5
VCC
Supplies the controller
This pin is connected to an external auxiliary voltage.
6
VIN
Input voltage sensing
Brown−Out
This pin observes the HV rail and is used in valley selection. This pin also
monitors and protects for low mains conditions.
Connected to the auxiliary winding, this pin detects the core reset event.
The controller ground
www.onsemi.com
2
NCL30081
OFF
UVLO
Aux_SCP
GND
Fault
Management
CS_shorted
Internal
Thermal
Shutdown
VREF
VDD
STOP
VCC
VCC Management
Latch
VCC_max
Ipkmax
WOD_SCP
VCC Over Voltage
Protection
BO_NOK
Qdrv
ZCD
VCC
VVIN
Valley Selection
S
Aux_SCP
offset_OK
Line
Feedforward
Leading
Edge
Blanking
Q
DRV
Qdrv
VVLY
R
VREF
STEP_DIM
STOP
CS_reset
Constant−Current
Control
Ipkmax
Max. Peak
Current
Limit
VVIN
Clamp
Circuit
offset_OK
Zero Crossing Detection
Aux. Winding
Short Circuit Protection
CS
VREF
VVIN
CS Short
Protection
Winding and
Output diode
Short Circuit
Protection
STOP
Ipkmax
VVIN
STEP_DIM
CS_shorted
Step
Dimming
VIN
Brown−Out
BO_NOK
WOD_SCP
Figure 2. Internal Circuit Architecture
www.onsemi.com
3
NCL30081
Table 2. MAXIMUM RATINGS TABLE
Symbol
Rating
Value
Unit
VCC(MAX)
ICC(MAX)
Maximum Power Supply voltage, VCC pin, continuous voltage
Maximum current for VCC pin
−0.3, +35
Internally limited
V
mA
VDRV(MAX)
IDRV(MAX)
Maximum driver pin voltage, DRV pin, continuous voltage
Maximum current for DRV pin
−0.3, VDRV (Note 1)
−500, +800
V
mA
VMAX
IMAX
Maximum voltage on low power pins (except pins DRV and VCC)
Current range for low power pins (except pins ZCD, DRV and VCC)
−0.3, +5.5
−2, +5
V
mA
VZCD(MAX)
IZCD(MAX)
Maximum voltage for ZCD pin
Maximum current for ZCD pin
−0.3, +10
−2, +5
V
mA
RθJ−A
Thermal Resistance, Junction−to−Air
360
°C/W
TJ(MAX)
Maximum Junction Temperature
150
°C
Operating Temperature Range
−40 to +125
°C
Storage Temperature Range
−60 to +150
°C
ESD Capability, HBM model (Note 2)
4
kV
ESD Capability, MM model (Note 2)
200
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. VDRV is the DRV clamp voltage VDRV(high) when VCC is higher than VDRV(high). VDRV is VCC unless otherwise noted.
2. This device series contains ESD protection and exceeds the following tests: Human Body Model 4000 V per JEDEC JESD22−A114−F and
Machine Model Method 200 V per JEDEC JESD22−A115−A.
3. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78 except for VIN pin which passes 60 mA.
www.onsemi.com
4
NCL30081
Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V;
For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V)
Description
Test Condition
Symbol
Min
Typ
Max
Unit
VCC increasing
VCC decreasing
VCC decreasing
VCC(on)
VCC(off)
VCC(HYS)
VCC(reset)
16
8.2
8
3.5
18
8.8
–
4.5
20
9.4
–
5.5
Over Voltage Protection
VCC OVP threshold
VCC(OVP)
26
28
30
V
VCC(off) noise filter
VCC(reset) noise filter−
tVCC(off)
tVCC(reset)
–
–
5
20
–
–
ms
ICC(start)
–
13
30
mA
ICC(sFault)
–
46
60
mA
ICC1
ICC2
ICC3
0.8
–
–
1.0
2.15
2.6
1.4
4.0
5.0
Maximum Internal current limit
VILIM
0.95
1
1.05
V
Leading Edge Blanking Duration for VILIM
(Tj = −25°C to 125°C)
tLEB
250
300
350
ns
Leading Edge Blanking Duration for VILIM
(Tj = −40°C to 125°C)
tLEB
240
300
350
ns
Ibias
–
0.02
–
mA
tILIM
–
50
150
ns
VCS(stop)
1.35
1.5
1.65
V
tBCS
–
120
–
ns
Blanking time for CS to GND short detection VpinVIN = 1 V
tCS(blank1)
8.0
–
14.0
ms
Blanking time for CS to GND short detection VpinVIN = 3.3 V
tCS(blank2)
2.6
–
4.6
ms
Drive Resistance
DRV Sink
DRV Source
RSNK
RSRC
–
–
13
30
–
–
Drive current capability
DRV Sink (Note 4)
DRV Source (Note 4)
ISNK
ISRC
–
–
500
300
–
–
STARTUP AND SUPPLY CIRCUITS
Supply Voltage
Startup Threshold
Minimum Operating Voltage
Hysteresis VCC(on) – VCC(off)
Internal logic reset
V
Startup current
Startup current in fault mode
Supply Current
Device Disabled/Fault
Device Enabled/No output load on pin 5
Device Switching (Fsw = 65 kHz)
mA
VCC > VCC(off)
Fsw = 65 kHz
CDRV = 470 pF,
Fsw = 65 kHz
CURRENT SENSE
Input Bias Current
DRV high
Propagation delay from current detection to gate off−state
Threshold for immediate fault protection activation
Leading Edge Blanking Duration for VCS(stop)
GATE DRIVE
W
mA
Rise Time (10% to 90%)
CDRV = 470 pF
tr
–
40
–
ns
Fall Time (90% to 10%)
CDRV = 470 pF
tf
–
30
–
ns
DRV Low Voltage
VCC = VCC(off)+0.2 V
CDRV = 470 pF,
RDRV = 33 kW
VDRV(low)
8
–
–
V
DRV High Voltage
VCC = 30 V
CDRV = 470 pF,
RDRV = 33 kW
VDRV(high)
10
12
14
V
4. Guaranteed by design
www.onsemi.com
5
NCL30081
Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V;
For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V)
Description
Test Condition
Symbol
Min
Typ
Max
Unit
ZCD threshold voltage
VZCD increasing
VZCD(THI)
25
45
65
mV
ZCD threshold voltage (Note 4)
VZCD decreasing
VZCD(THD)
5
25
45
mV
ZCD hysteresis (Note 4)
VZCD increasing
VZCD(HYS)
10
–
–
mV
VZCD(short)
0.8
1
1.2
V
tOVLD
70
90
110
ms
trecovery
3
4
5
s
Ipin1 = 3.0 mA
Ipin1 = −2.0 mA
VCH
VCL
–
−0.9
9.5
−0.6
–
−0.3
VZCD decreasing
tDEM
–
–
150
ns
tPAR
–
20
–
ns
tBLANK
2.25
3
3.75
ms
tTIMO
5
6.5
8
ms
Reference Voltage at Tj = 25°C
VREF
245
250
255
mV
Reference Voltage Tj = −40°C to 125°C
VREF
242.5
250
257.5
mV
70% reference voltage
VREF50
–
175
–
mV
40% reference voltage
VREF50
–
100
–
mV
25% reference voltage
VREF50
–
62.5
–
mV
10% reference voltage
VREF50
–
25
–
mV
5% reference voltage
VREF50
–
12.5
–
mV
Current sense lower threshold for detection of the
leakage inductance reset time
VCS(low)
30
55
80
mV
KLFF
15
17
19
mA/V
VpinVIN = 4.5 V
Ioffset(MAX)
67.5
76.5
85.5
mA
VREF value below which the offset current source is turned off
VREF decreases
VREF(off)
–
15
–
mV
VREF value above which the offset current source is turned on
VREF increases
VREF(on)
–
20
–
mV
Threshold for line range detection Vin increasing
(1st to 2nd valley transition for VREF > 0.75 V)
VVIN increases
VHL
2.28
2.4
2.52
V
Threshold for line range detection Vin decreasing
(2nd to 1st valley transition for VREF > 0.75 V)
VVIN decreases
VLL
2.18
2.3
2.42
V
tHL(blank)
15
25
35
ms
ZERO VOLTAGE DETECTION CIRCUIT
Threshold voltage for output short circuit or aux. winding
short circuit detection
Short circuit detection Timer
VZCD < VZCD(short)
Auto−recovery timer duration
Input clamp voltage
High state
Low state
V
Propagation Delay from valley detection to DRV high
Equivalent time constant for ZCD input (Note 4)
Blanking delay after on−time
Timeout after last demag transition
CONSTANT CURRENT CONTROL
LINE FEED−FORWARD
VVIN to ICS(offset) conversion ratio
Offset current maximum value
VALLEY SELECTION
Blanking time for line range detection
4. Guaranteed by design
www.onsemi.com
6
NCL30081
Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V;
For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V)
Description
Test Condition
Symbol
Min
Typ
Max
Unit
Valley thresholds
1st to 2nd valley transition at LL and 2nd to 3rd valley HL
2nd to 1st valley transition at LL and 3rd to 2nd valley HL
2nd to 4th valley transition at LL and 3rd to 5th valley HL
4th to 2nd valley transition at LL and 5th to 3rd valley HL
4th to 7th valley transition at LL and 5th to 8th valley HL
7th to 4th valley transition at LL and 8th to 5th valley HL
7th to 11th valley transition at LL and 8th to 12th valley HL
11th to 7th valley transition at LL and 12th to 8th valley HL
11th to 13th valley transition at LL and 12th to 15th valley HL
13th to 11th valley transition at LL and 15th to 12th valley HL
VREF decreases
VREF increases
VREF decreases
VREF increases
VREF decreases
VREF increases
VREF decreases
VREF increases
VREF decreases
VREF increases
VVLY1−2/2−3
VVLY2−1/3−2
VVLY2−4/3−5
VVLY4−2/5−3
VVLY4−7/5−8
VVLY7−4/8−5
VVLY7−11/8−12
VVLY11−7/12−8
VVLY11−13/12−15
VVLY13−11/15−12
177.5
185.0
117.5
125.0
–
–
–
–
–
–
187.5
195.0
125.0
132.5
75.0
82.5
37.5
50.0
15.0
20.0
197.5
205.0
132.5
140.0
–
–
–
–
–
–
Device switching
(FSW around 65 kHz)
TSHDN
130
155
170
°C
TSHDN(HYS)
–
55
–
°C
VALLEY SELECTION
mV
THERMAL SHUTDOWN
Thermal Shutdown (Note 4)
Thermal Shutdown Hysteresis (Note 4)
BROWN−OUT
Brown−Out ON level (IC start pulsing)
VSD increasing
VBO(on)
0.90
1
1.10
V
Brown−Out OFF level (IC shuts down)
VSD decreasing
VBO(off)
0.85
0.9
0.95
V
BO comparators delay
tBO(delay)
–
30
–
ms
Brown−Out blanking time
tBO(blank)
35
50
65
ms
Brown−out pin bias current
IBO(bias)
−250
–
250
nA
4. Guaranteed by design
www.onsemi.com
7
NCL30081
TYPICAL CHARACTERISTICS
18.15
8.85
18.10
VCC(off) (V)
VCC(on) (V)
8.80
18.05
18.00
8.75
8.70
17.95
17.90
−40
−20
0
20
40
60
80
8.65
−40
120
100
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 3. VCC(on) vs. Junction Temperature
Figure 4. VCC(off) vs. Junction Temperature
27.80
1.09
27.75
1.07
1.05
27.65
ICC1 (mA)
VCC(OVP) (V)
27.70
27.60
27.55
1.03
1.01
27.50
0.99
27.45
0.97
27.40
−40
−20
0
20
40
60
80
100
0.95
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. VCC(OVP) vs. Junction Temperature
Figure 6. ICC1 vs. Junction Temperature
2.20
120
2.70
2.65
2.60
ICC3 (mA)
ICC2 (mA)
2.15
2.10
2.55
2.50
2.45
2.05
2.40
2.00
−40
−20
0
20
40
60
80
100
2.35
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 7. ICC2 vs. Junction Temperature
Figure 8. ICC3 vs. Junction Temperature
www.onsemi.com
8
120
NCL30081
TYPICAL CHARACTERISTICS
54
19
52
50
ICC(sFault) (mA)
ICC(start) (mA)
17
15
13
48
46
44
42
11
40
9
−40
−20
0
20
40
60
80
38
−40
120
100
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 9. ICC(start) vs. Junction Temperature
Figure 10. ICC(sFault) vs. Junction Temperature
1.51
1.002
1.000
1.50
0.998
1.49
VILIM (V)
VCS(stop) (V)
−20
1.48
0.996
0.994
1.47
0.992
1.46
−40
−20
0
20
40
60
80
100
0.990
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 11. VCS(stop) vs. Junction Temperature
Figure 12. VILIM vs. Junction Temperature
305
120
3.00
303
301
2.98
tBLANK (ms)
tLEB (ns)
299
297
295
293
2.96
2.94
291
2.92
289
287
285
−40
−20
0
20
40
60
80
100
2.90
−40
120
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 13. tLEB vs. Junction Temperature
Figure 14. tBLANK vs. Junction Temperature
www.onsemi.com
9
NCL30081
TYPICAL CHARACTERISTICS
6.80
254
253
6.70
252
VREF (mV)
tTIMO (ms)
6.60
6.50
6.40
251
250
249
248
6.30
247
−20
0
20
40
60
80
100
246
−40
120
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 15. tTIMO vs. Junction Temperature
Figure 16. VREF vs. Junction Temperature
178
102
177
101
176
100
175
174
173
120
99
98
97
172
−40
−20
0
20
40
60
80
100
96
−40
120
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 17. VREF70 vs. Junction Temperature
Figure 18. VREF40 vs. Junction Temperature
66
26.0
65
25.5
64
25.0
VREF10 (mV)
VREF25 (mV)
−20
TJ, JUNCTION TEMPERATURE (°C)
VREF40 (mV)
VREF70 (mV)
6.20
−40
63
62
61
24.5
24.0
23.5
60
−40
−20
0
20
40
60
80
100
23.0
−40
120
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 19. VREF25 vs. Junction Temperature
Figure 20. VREF10 vs. Junction Temperature
www.onsemi.com
10
NCL30081
TYPICAL CHARACTERISTICS
14.5
55.8
14.0
55.6
55.4
13.0
VCS(low) (mV)
VREF05 (mV)
13.5
12.5
12.0
11.5
54.8
54.4
10.5
10.0
−40
−20
0
20
40
60
80
100
54.2
−40
120
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 21. VREF05 vs. Junction Temperature
Figure 22. VCS(low) vs. Junction Temperature
17.65
2.42
2.41
17.60
2.40
17.55
VHL (V)
KLFF (mA/V)
55.0
54.6
11.0
17.50
2.39
2.38
17.45
17.40
−40
2.37
−20
0
20
40
60
80
100
2.36
−40
120
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 23. KLFF vs. Junction Temperature
Figure 24. VHL vs. Junction Temperature
120
25.5
25.0
tHL(BLANK) (ms)
2.29
2.28
2.27
2.26
−40
−20
TJ, JUNCTION TEMPERATURE (°C)
2.30
VLL (V)
55.2
24.5
24.0
23.5
−20
0
20
40
60
80
100
23.0
−40
120
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 25. VLL vs. Junction Temperature
Figure 26. tHL(BLANK) vs. Junction Temperature
www.onsemi.com
11
NCL30081
TYPICAL CHARACTERISTICS
186.8
200
186.6
199
186.4
VVLY2−1/3−2 (mV)
VVLY1−2/2−3 (mV)
198
186.2
186.0
185.8
185.6
195
193
185.2
−20
0
20
40
60
80
100
192
−40
120
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 27. VVLY1−2/2−3 vs. Junction
Temperature
Figure 28. VVLY2−1/3−2 vs. Junction
Temperature
124.6
137
124.4
136
124.2
124.0
123.8
123.6
123.4
−40
−20
TJ, JUNCTION TEMPERATURE (°C)
VVLY4−2/5−3 (mV)
VVLY2−4/3−5 (mV)
196
194
185.4
185.0
−40
197
120
135
134
133
132
131
−20
0
20
40
60
80
100
130
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 29. VVLY2−4/3−5 vs. Junction
Temperature
Figure 30. VVLY4−2/5−3 vs. Junction
Temperature
75.0
120
88
87
86
VVLY7−4/8−5 (mV)
VVLY4−7/5−8 (mV)
74.8
74.6
74.4
85
84
83
82
74.2
81
74.0
−40
−20
0
20
40
60
80
100
80
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 31. VVLY4−7/5−8 vs. Junction
Temperature
Figure 32. VVLY7−4/8−5 vs. Junction
Temperature
www.onsemi.com
12
120
NCL30081
37.3
50
37.2
49
VVLY11−7/12−8 (mV)
VVLY7−11/8−12 (mV)
TYPICAL CHARACTERISTICS
37.1
37.0
36.9
36.8
−20
0
20
40
60
80
100
46
45
43
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 33. VVLY7−11/8−12 vs. Junction
Temperature
Figure 34. VVLY11−7/12−8 vs. Junction
Temperature
15.6
21.0
15.1
20.5
VVLY13−11/15−12 (mV)
VVLY11−13/12−15 (mV)
47
44
36.7
−40
14.6
14.1
13.6
13.1
120
20.0
19.5
19.0
18.5
18.0
12.6
−40
−20
0
20
40
60
80
100
17.5
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 35. VVLY11−13/12−15 vs. Junction
Temperature
Figure 36. VVLY13−11/15−12 vs. Junction
Temperature
1.000
120
0.910
0.995
0.905
VBO(off) (V)
VBO(on) (V)
48
0.990
0.985
0.900
0.895
0.980
0.975
−40
−20
0
20
40
60
80
100
0.890
−40
120
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 37. VBO(on) vs. Junction Temperature
Figure 38. VBO(off) vs. Junction Temperature
www.onsemi.com
13
NCL30081
TYPICAL CHARACTERISTICS
53.5
85.0
84.5
53.0
tOVLD (ms)
83.5
52.0
51.5
83.0
82.5
82.0
51.0
81.5
50.5
50.0
−40
81.0
−20
0
20
40
60
80
100
80.5
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 39. tBO(BLANK) vs. Junction
Temperature
Figure 40. tOVLD vs. Junction Temperature
4.40
4.35
4.30
trecovery (s)
tBO(BLANK) (ms)
84.0
52.5
4.25
4.20
4.15
4.10
4.05
−40
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
Figure 41. trecovery vs. Junction Temperature
www.onsemi.com
14
120
NCL30081
Application Information
• Brown−Out: the controller includes a brown−out
The NCL30081 implements a current−mode architecture
operating in quasi−resonant mode. Thanks to proprietary
circuitry, the controller is able to accurately regulate the
secondary side current of the flyback converter without
using any opto−coupler or measuring directly the secondary
side current.
• Quasi−Resonance Current−Mode Operation:
implementing quasi−resonance operation in peak
current−mode control, the NCL30081 optimizes the
efficiency by switching in the valley of the MOSFET
drain−source voltage. Thanks to a smart control
algorithm, the controller locks−out in a selected valley
and remains locked until the input voltage or the output
current set point significantly changes.
• Primary Side Constant Current Control: thanks to a
proprietary circuit, the controller is able to compensate
for the leakage inductance of the transformer and allow
accurate control of the secondary side current.
• Line Feed−forward: compensation for possible
variation of the output current caused by system slew
rate variation.
• Open LED protection: if the voltage on the VCC pin
exceeds an internal limit, the controller shuts down and
waits 4 seconds before restarting switching.
•
•
•
•
circuit with a validation timer which safely stops the
controller in the event that the input voltage is too low.
The device will automatically restart if the line recovers.
Cycle−by−cycle peak current limit: when the current
sense voltage exceeds the internal threshold VILIM, the
MOSFET is turned off for the rest of the switching cycle.
Winding Short−Circuit Protection: an additional
comparator with a short LEB filter (tBCS) senses the CS
signal and stops the controller if VCS reaches 1.5 x
VILIM. For noise immunity reasons, this comparator is
enabled only during the main LEB duration tLEB.
Output Short−circuit protection: If a very low
voltage is applied on ZCD pin for 90 ms (nominal), the
controllers assume that the output or the ZCD pin is
shorted to ground and enters shutdown. The auto−
restart version (B suffix) waits 4 seconds, then the
controller restarts switching. In the latched version (A
suffix), the controller is latched as long as VCC stays
above the VCC(reset) threshold.
Step dimming: Each time the IC detects a brown−out
condition, the output current is decreased by discrete steps.
www.onsemi.com
15
NCL30081
Constant Current Control
(DCM). Figure 42 shows the basic circuit of a flyback
converter.
Figure 43 portrays the primary and secondary current of
a flyback converter in discontinuous conduction mode
Transformer
Vbulk
Lleak
Cclp
Nsp
Rclp
.
Lp
.
Clamping
network
DRV
Clump
Rsense
Figure 42. Basic Flyback Converter Schematic
www.onsemi.com
16
Vout
NCL30081
During the on−time of the MOSFET, the bulk voltage
Vbulk is applied to the magnetizing and leakage inductors Lp
and Lleak and the current ramps up.
When the MOSFET is turned−off, the inductor current
first charges Clump. The output diode is off until the voltage
across Lp reverses and reaches:
N spǒV out ) V fǓ
turned off, the drain voltage begins to oscillate because of
the resonating network formed by the inductors (Lp+Lleak)
and the lump capacitor. This voltage is reflected on the
auxiliary winding wired in flyback mode. Thus, by looking
at the auxiliary winding voltage, we can detect the end of the
conduction time of secondary diode. The constant current
control block picks up the leakage inductor current, the end
of conduction of the output rectifier and controls the drain
current to maintain the output current constant.
We have:
(eq. 1)
The output diode current increase is limited by the leakage
inductor. As a consequence, the secondary peak current is
reduced:
I D,pk t
I L,pk
I out +
V REF
2N spR sense
(eq. 3)
(eq. 2)
N sp
The output current value is set by choosing the sense
resistor:
The diode current reaches its peak when the leakage inductor
is reset. Thus, in order to accurately regulate the output
current, we need to take into account the leakage inductor
current. This is accomplished by sensing the clamping
network current. Practically, a node of the clamp capacitor
is connected to Rsense instead of the bulk voltage Vbulk.
Then, by reading the voltage on the CS pin, we have an
image of the primary current (red curve in Figure 43).
When the diode conducts, the secondary current decreases
linearly from ID,pk to zero. When the diode current has
R sense +
V ref
2N spI out
(eq. 4)
From Equation 3, the first key point is that the output
current is independent of the inductor value. Moreover, the
leakage inductance does not influence the output current
value as the reset time is taken into account by the controller.
IL,pk
NspID,pk
Ipri(t)
Isec(t)
time
t1
t2
ton
tdemag
Vaux(t)
time
Figure 43. Flyback Currents and Auxiliary Winding Voltage in DCM
www.onsemi.com
17
NCL30081
Internal Soft−Start
At startup or after recovering from a fault, there is a small
internal soft−start of 40 ms.
In addition, during startup, as the output voltage is zero
volts, the demagnetization time is long and the constant
current control block will slowly increase the peak current
towards its nominal value as the output voltage grows.
Figure 44 shows a soft−start simulation example for a 9 W
LED power supply.
16.0
(V)
12.0
1
Vout
2
I out
4
VControl
3
VCS
8.00
4.00
0
800m
(A)
600m
400m
200m
0
800m
(V)
600m
400m
200m
0
604u
1.47m
2.34m
time in seconds
3.21m
4.07m
Figure 44. Startup Simulation Showing the Natural Soft−start
Cycle−by−Cycle Current Limit
Winding and Output Diode Short−Circuit Protection
When the current sense voltage exceeds the internal
threshold VILIM, the MOSFET is turned off for the rest of the
switching cycle (Figure 45).
In parallel with the cycle−by−cycle sensing of the CS pin,
another comparator with a reduced LEB (tBCS) and a higher
threshold (1.5 V typical) is able to sense winding
short−circuit and immediately stops the DRV pulses. The
controller goes into auto−recovery mode in version B.
In version A, the controller is latched. In latch mode, the
DRV pulses stop and VCC ramps up and down. The circuit
un−latches when VCC pin voltage drops below VCC(reset)
threshold.
www.onsemi.com
18
NCL30081
S
DRV
Q
Q
aux
Vdd
latch
CS
R
LEB1
Rsense
+
Vcontrol
Vcc
management
PWMreset
VCC
−
+
VCCstop
UVLO
grand
8_HICC
reset
Ipkmax
−
VILIMIT
OVP
LEB2
+
STOP
OVP
WOD_SCP
latch
−
S
VCS(stop)
Q
Q
OFF WOD_SCP
S
Q
Q
R
8_HICC
R
grand
reset
from Fault Management Block
Figure 45. Winding Short Circuit Protection, Max. Peak Current Limit Circuits
Step Dimming
Note:
The power supply designer must ensure that VCC stays
high enough when the light is turned−off to let the controller
memorize the dimming step state.
The power supply designer should use a split VCC circuit
for step dimming with a capacitor allowing providing
enough VCC for 1 s (47 mF to 100 mF capacitor).
The step dimming state is memorized by the controller
until VCC crosses VCC(reset).
The step dimming function decreases the output current
from 100% to 5% of its nominal value in discrete steps.
There are 5 steps in total. Table 4 shows the different steps
value and the corresponding output current set−point. Each
time a brown−out is detected, the output current is decreased
by decreasing the reference voltage VREF setting the output
current value.
When the 5% dimming step is reached, if a brown−out
event occurs, the controller restarts at 100% of the output
current.
Table 4. DIMMING STEPS
Dimming Step
Iout
Perceived Light
ON
100%
100%
1
70%
84%
2
40%
63%
3
25%
50%
4
10%
32%
5
5%
17%
VCC
4.7 mF
47 − 100 mF
Figure 46. Split VCC Supply
www.onsemi.com
19
NCL30081
Vbulk
Vbulk(on)
Vbulk(off)
VCC
VCC(on)
VCC(off)
VCC(reset)
BO
comp
Iout
100%
70%
40%
25%
10%
Figure 47. Step Dimming Chronograms
www.onsemi.com
20
5%
NCL30081
VCC Over Voltage Protection (Open LED Protection)
In the NCL30081, when the VCC voltage reaches the
VCC(OVP) threshold, the controller stops the DRV pulses and
the 4−s timer starts counting. The IC re−start switching after
the 4−s timer has elapsed as long as VCC ≥ VCC(on). This is
illustrated in Figure 48.
If no output load is connected to the LED power supply,
the controller must be able to safely limit the output voltage
excursion.
40.0
V CC(OVP)
(V)
30.0
1 V CC
V CC(on)
20.0
10.0
VCC(off)
0
40.0
(V)
30.0
2 Vout
20.0
10.0
0
800m
(A)
600m
400m
200m
3 I out
0
8.00
(V)
6.00
4 OVP
4.00
2.00
0
1.38
3.96
6.54
time in seconds
9.11
11.7
Figure 48. Open LED Protection Chronograms
Valley Lockout
voltage or the output current set−point varies significantly.
This avoids valley jumping and the inherent noise caused by
this phenomenon.
The input voltage is sensed by the VIN pin. The internal
logic selects the operating valley according to VIN pin
voltage (Figure 49) and the dimming state imposed by the
Step Dimming feature.
By default, when the output current is not dimmed, the
controller operates in the first valley at low line and in the
second valley at high line.
Quasi−Square wave resonant systems have a wide
switching frequency excursion. The switching frequency
increases when the output load decreases or when the input
voltage increases. The switching frequency of such systems
must be limited.
The NCL30081 changes valley as the input voltage
increases and as the output current set−point is varied
(thermal fold−back and step dimming). This limits the
switching frequency excursion. Once a valley is selected,
the controller stays locked in the valley until the input
www.onsemi.com
21
NCL30081
Vbulk
VIN
+
LLine
HLine
25−ms blanking time
−
2.4 V if LLine low
2.3 V if LLine high
Figure 49. Line Range Detection
Table 5. VALLEY SELECTION
VIN pin voltage for valley change
Iout value at which the
controller changes valley
(Iout decreasing)
0
100%
75%
50%
30%
15%
6%
0%
0
−LL−
2.3 V
−HL−
1st
2nd
2nd
3rd
4th
5th
7th
8th
11th
12th
13th
15th
−LL−
2.4 V
−HL−
VVIN increases
VIN pin voltage for valley change
www.onsemi.com
22
5V
100%
78%
53%
33%
20%
8%
0%
5V
Iout increases
Iout decreases
Iout value at which the
controller changes valley
(Iout increasing)
VVIN decreases
NCL30081
Zero Crossing Detection Block
the valleys. To avoid such a situation, the NCL30081
features a Time−Out circuit that generates pulses if the
voltage on ZCD pin stays below the VZCD(THD) threshold
for 6.5 ms.
The time−out also acts as a substitute clock for the valley
detection and simulates a missing valley in case of too
damped free oscillations.
The ZCD pin allows detecting when the drain−source
voltage of the power MOSFET reaches a valley.
A valley is detected when the voltage on pin 1 crosses
below the VZCD(THD) internal threshold.
At startup or in case of extremely damped free
oscillations, the ZCD comparator may not be able to detect
V ZCD
3
4
V ZCD(THD)
The 3rd valley
is validated
high
14
2nd, 3rd
low
12
The 3rd valley is not detected
by the ZCD comp
The 2nd valley is detected
By the ZCD comparator
high
15 ZCD comp
low
high
low
16
TimeOut
17
Clk
Time−out circuit adds a pulse to
account for the missing 3rd valley
high
low
Figure 50. Time−out Chronograms
To avoid these scenarios, a protection circuit consisting of
a comparator and secondary timer starts counting when the
ZCD voltage is below the VZCD(short) threshold. If this timer
reaches 90 ms, the controller detects a fault and shutdown.
The auto−restart version (B suffix) waits 4 seconds, then the
controller restarts switching. In the latched version
(A suffix), the controller is latched as long as VCC stays
above the VCC(reset) threshold.
Normally with this type of time−out function, in the event
the ZCD pin or the auxiliary winding is shorted, the
controller could continue switching leading to improper
regulation of the LED current. Moreover during an output
short circuit, the controller will strive to maintain constant
current operation.
www.onsemi.com
23
NCL30081
Line Feed−forward
Because of internal and external propagation delays, the
MOSFET is not turned−off immediately when the current
set−point is reached. As a result, the primary peak current is
slightly higher than expected resulting in a small output
current error which can be compensated for during
component selection.
Normally this error would increase if the input line
voltage increased because the slew rate through the primary
inductance would increase. To compensate the peak current
increase brought by the variation, a positive voltage
proportional to the line voltage is added to the current sense
signal. The amount of offset voltage can be adjusted using
the RLFF resistor as shown in Figure 51. The offset voltage
is applied only during the MOSFET on−time and when Iout
is above 6% of the nominal output current.
Bulk rail
VDD
VIN
CS
ICS(offset)
RLFF
Rsense
Q_drv
Offset_OK
Figure 51. Line Feed−forward Schematic
Brown−out
shuts−down if the VIN pin voltage decreases and stays
below 0.9 V for 50 ms nominal. Exiting a brown−out
condition overrides the hiccup on VCC (VCC does not wait
to reach VCC(off)) and the IC immediately goes into startup
mode (ICC = ICC(start)).
In order to protect the supply against a very low input
voltage, the NCL30081 features a brown−out circuit with a
fixed ON/OFF threshold. The controller is allowed to start
if a voltage higher than 1 V is applied to the VIN pin and
Vbulk
VIN
+
50−ms blanking time
−
1 V if BONOK high
0.9 V if BONOK low
Figure 52. Brown−out Circuit
www.onsemi.com
24
BO_NOK
NCL30081
160
(V)
120
VBulk
80.0
1
40.0
0
18.0
(V)
2
VCC(on)
16.0
14.0
VCC
12.0
VCC(off)
10.0
1.10
V BO(on)
(V)
900m
V BO(off)
700m
V pinVIN
500m
3
300m
8.00
50−ms Timer
(V)
6.00
BO_NOK low
=> Startup mode
4.00
2.00
BO_NOK
4
0
46.1m
138m
231m
time in seconds
323m
Figure 53. Brown−Out Chronograms (Valley Fill circuit is used)
www.onsemi.com
25
415m
NCL30081
CS Pin Short Circuit Protection
Normally, if the CS pin or the sense resistor is shorted to
ground, the Driver will not be able to turn off, leading to
potential damage of the power supply. To avoid this, the
NCL30081 features a circuit to protect the power supply
against a short circuit of the CS pin. When the MOSFET is
on, if the CS voltage stays below VCS(low) after the adaptive
blanking timer has elapsed, the controller shuts down and
will attempt to restart on the next VCC hiccup.
Adaptative
Blanking Time
VVIN
Q_drv
CS
−
+
S
VCS(low)
Q
CS_short
Q
R
UVLO
BO_NOK
Figure 54. CS Pin Short Circuit Protection Schematic
Fault Management
In this mode, the DRV pulses are stopped and the
controller turn−off some circuits to decrease the internal
consumption. VCC voltage decrease through the controller
own consumption (ICC1).
For the output diode short circuit protection, the output /
aux. winding short circuit protection and the VCC OVP, the
controller waits 4 seconds (auto−recovery timer) and then
initiates a startup sequence (VCC ≥ VCC(on)) before
re−starting switching.
Latch Mode
This mode is activated by the output diode short−circuit
protection (WOD_SCP) and the Aux_SCP in version A
only.
In this mode, the DRV pulses are stopped and the
controller is latched. There are hiccups on VCC.
The circuit un−latches when VCC < VCC(reset).
OFF Mode
The circuit turns off whenever a major condition prevents
it from operating:
• Incorrect feeding of the circuit: “UVLO high”. The
UVLO signal becomes high when VCC drops below
VCC(off) and remains high until VCC exceeds VCC(on).
• VCC OVP
• Output diode short circuit protection: “WOD_SCP
high”
• Output / Auxiliary winding Short circuit protection:
“Aux_SCP high”
• Die over temperature (TSD)
• Brown−Out: “BO_NOK” high
• Pin CS short circuited to GND: “CS_short high”
www.onsemi.com
26
NCL30081
Reset
Timer has
finished
counting
VCC > VCC(on)
VCC < VCC(off)
or
BO_NOK ↓
VCC_OVP
BO_NOK high
or TSD
or CS_Short
Stop
4−s
Timer
VCC
Disch.
BO_NOK high
or TSD
or CS_Short
WOD_SCP
or Aux_SCP
or VCC_OVP
Run
With states: Reset
Stop
Run
VCC Disch.
4−s Timer
→
→
→
→
→
VCC < VCC(off)
Controller is reset, ICC = ICC(start)
Controller is ON, DRV is not switching
Normal switching
No switching, ICC = ICC1, waiting for VCC to decrease to VCC(off)
the auto−recovery timer is counting, VCC is ramping up and down between VCC(on) and VCC(off)
Figure 55. State Diagram for B Version Faults
www.onsemi.com
27
NCL30081
Reset
Timer has
finished
counting
VCC > VCC(on)
VCC < VCC(off)
or
BO_NOK ↓
VCC < VCC(reset)
4−s
Timer
VCC_OVP
BO_NOK high
or TSD
or CS_Short
Stop
VCC
Disch.
VCC_OVP
BO_NOK high
or TSD
or CS_Short
Latch
Run
WOD_SCP or
Aux_SCP
With states: Reset
Stop
Run
VCC Disch.
4−s Timer
Latch
→
→
→
→
→
→
VCC < VCC(off)
Controller is reset, ICC = ICC(start)
Controller is ON, DRV is not switching
Normal switching
No switching, ICC = ICC1, waiting for VCC to decrease to VCC(off)
the auto−recovery timer is counting, VCC is ramping up and down between VCC(on) and VCC(off)
Controller is latched off, VCC is ramping up and down between VCC(on) and VCC(off),
only VCC(reset) can release the latch.
Figure 56. State Diagram for A Version Faults
www.onsemi.com
28
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSOP−6
CASE 318G−02
ISSUE V
1
SCALE 2:1
D
H
ÉÉ
ÉÉ
6
E1
1
NOTE 5
5
2
L2
4
GAUGE
PLANE
E
3
L
b
SEATING
PLANE
C
DETAIL Z
e
DIM
A
A1
b
c
D
E
E1
e
L
L2
M
c
A
0.05
M
DATE 12 JUN 2012
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM
LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D
AND E1 ARE DETERMINED AT DATUM H.
5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.
A1
DETAIL Z
MIN
0.90
0.01
0.25
0.10
2.90
2.50
1.30
0.85
0.20
0°
MILLIMETERS
NOM
MAX
1.00
1.10
0.06
0.10
0.38
0.50
0.18
0.26
3.00
3.10
2.75
3.00
1.50
1.70
0.95
1.05
0.40
0.60
0.25 BSC
10°
−
STYLE 1:
PIN 1. DRAIN
2. DRAIN
3. GATE
4. SOURCE
5. DRAIN
6. DRAIN
STYLE 2:
PIN 1. EMITTER 2
2. BASE 1
3. COLLECTOR 1
4. EMITTER 1
5. BASE 2
6. COLLECTOR 2
STYLE 3:
PIN 1. ENABLE
2. N/C
3. R BOOST
4. Vz
5. V in
6. V out
STYLE 4:
PIN 1. N/C
2. V in
3. NOT USED
4. GROUND
5. ENABLE
6. LOAD
STYLE 5:
PIN 1. EMITTER 2
2. BASE 2
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
6. COLLECTOR 2
STYLE 6:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. EMITTER
5. COLLECTOR
6. COLLECTOR
STYLE 7:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. N/C
5. COLLECTOR
6. EMITTER
STYLE 8:
PIN 1. Vbus
2. D(in)
3. D(in)+
4. D(out)+
5. D(out)
6. GND
STYLE 9:
PIN 1. LOW VOLTAGE GATE
2. DRAIN
3. SOURCE
4. DRAIN
5. DRAIN
6. HIGH VOLTAGE GATE
STYLE 10:
PIN 1. D(OUT)+
2. GND
3. D(OUT)−
4. D(IN)−
5. VBUS
6. D(IN)+
STYLE 11:
PIN 1. SOURCE 1
2. DRAIN 2
3. DRAIN 2
4. SOURCE 2
5. GATE 1
6. DRAIN 1/GATE 2
STYLE 12:
PIN 1. I/O
2. GROUND
3. I/O
4. I/O
5. VCC
6. I/O
STYLE 13:
PIN 1. GATE 1
2. SOURCE 2
3. GATE 2
4. DRAIN 2
5. SOURCE 1
6. DRAIN 1
STYLE 14:
PIN 1. ANODE
2. SOURCE
3. GATE
4. CATHODE/DRAIN
5. CATHODE/DRAIN
6. CATHODE/DRAIN
STYLE 15:
PIN 1. ANODE
2. SOURCE
3. GATE
4. DRAIN
5. N/C
6. CATHODE
STYLE 16:
PIN 1. ANODE/CATHODE
2. BASE
3. EMITTER
4. COLLECTOR
5. ANODE
6. CATHODE
STYLE 17:
PIN 1. EMITTER
2. BASE
3. ANODE/CATHODE
4. ANODE
5. CATHODE
6. COLLECTOR
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
6X
0.60
XXXAYWG
G
1
6X
3.20
XXX
A
Y
W
G
0.95
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB14888C
TSOP−6
1
IC
0.95
XXX MG
G
= Specific Device Code
=Assembly Location
= Year
= Work Week
= Pb−Free Package
STANDARD
XXX = Specific Device Code
M
= Date Code
G
= Pb−Free Package
*This information is generic. Please refer to device data sheet
for actual part marking. Pb−Free indicator, “G” or microdot “
G”, may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Email Requests to: orderlit@onsemi.com
onsemi Website: www.onsemi.com
◊
TECHNICAL SUPPORT
North American Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada
Phone: 011 421 33 790 2910
Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative
工商网监
湘ICP备2023018690号
