NCL30100
Fixed Off Time Switched
Mode LED Driver Controller
The NCL30100 is a compact switching regulator controller intended
for space constrained constant current high−brightness LED driver
applications where efficiency and small size are important. The
controller is based on a peak current, quasi fixed−off time control
architecture optimized for continuous conduction mode step−down
(buck) operation. This allows the output filter capacitor to be
eliminated. In this configuration, a reverse buck topology is used to
control a cost effective N−type MOSFET. Moreover, this controller
employs negative current sensing thus minimizing power dissipation
in the current sense resistor. The off time is user adjustable through the
selection of a small external capacitor, thus allowing the design to be
optimized for a given switching frequency range. The control loop is
designed to operate up to 700 kHz allowing the designer the flexibility
to use a very small inductor for space constrained applications.
The device has been optimized to provide a flexible inductive
step−down converter to drive one or more high power LED(s). The
controller can also be used to implement non−isolated buck−boost
driver topologies.
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MARKING
DIAGRAM
TSOP−6
(SOT23−6, SC59−6) AAAAYWG
G
SN SUFFIX
CASE 318G
1
1
AAA
A
Y
W
G
(Note: Microdot may be in either location)
PIN CONNECTIONS
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Quasi−Fixed OFF Time, Peak Current Control Method
N−FET Based Controller Architecture
Up to 700 kHz Switching Frequency
Up to >95% Efficiency
No Output Capacitor Needed
VCC Operation from 6.35 − 18 V
Adjustable Current Limit with Negative Sensing
Inherent Open LED Protected
Very Low Current Consumption at Startup
Undervoltage Lockout
Compact Thin TSOP−6 Pb−Free Package
−40 to + 125°C Operating Temperature Range
This is a Pb−Free Device
CS
1
6
Gate
GND
2
5
VCC
CT
3
4
IVC
(Top View)
ORDERING INFORMATION
Device
NCL30100SNT1G
Package
Shipping†
TSOP−6 3000 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Typical Applications
•
•
•
•
•
•
•
•
= Specific Device Code
=Assembly Location
= Year
= Work Week
= Pb−Free Package
Low Voltage Halogen LED Replacement (MR 16)
LED Track Lighting
Landscape Lighting
Solar LED Applications
Transportation Lighting
12 V LED Bulb Replacement
Outdoor Area Lighting
LED Light Bars
© Semiconductor Components Industries, LLC, 2011
January, 2011 − Rev. 3
1
Publication Order Number:
NCL30100/D
NCL30100
6.5 – 24 V
+
C1
R1
LED2
R2
LED1
IC1
NCL30100
R3
CS
−
D1
LEDX
DRV
L1
GND VCC
CT
IVC
C2
D2
C3
Q1
R4
Figure 1. Typical Application Example of the LED Converter
PIN FUNCTION DESCRIPTION
Pin N5
Pin Name
Function
Pin Description
1
CS
Current sense input
2
GND
Ground
3
CT
Timing capacitor
4
IVC
Input voltage compensation
5
VCC
Input supply
Supply input for the controller. The input is rated to 18 V but as illustrated
Figure 1, a simple zener diode and resistor can allow the LED string to be
powered from a higher voltage
6
DRV
Driver output
Output drive for an external power MOSFET
A resistor divider consisting of R3 and R4 is used to set the peak current
sensed through the MOSFET switch
Power ground.
Capacitor to establish the off time duration
The current injected into the input varies the switch off time and IPK allowing for
feedforward compensation.
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2
NCL30100
IVC
Input Voltage
Regulator
VOffset
VDD
Reference
Regulator
Iref
Undervoltage
Lockout
VCC
6.35/5.85 V
OFF Time
Comparator
0−3.9 V
CT
50 mA
CS
Gate Driver
Set
12.5−50 mA
S
Q
R
Q
DRV
SET
CLR
Reset
GND
Current Sense
Comparator
Figure 2. Simplified Circuit Architecture
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Power Supply Voltage
VCC
18
V
IVC Pins Voltage Range
IVC
−0.3 to 18
V
CS and CT Pin Voltage Range
Vin
−0.3 to 10
V
RqJA
178
°C/W
Thermal Resistance, Junction−to−Air
Junction Temperature
TJ
150
°C
Storage Temperature Range
Tstg
−60 to +150
°C
ESD Voltage Protection, Human Body Model (HBM)
VESD−HBM
2
kV
ESD Voltage Protection, Machine Model (MM)
VESD−MM
200
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device(s) contains ESD protection and exceeds the following tests:
Human Body Model 2000 V per JEDEC Standard JESD22−A114E
Machine Model 200 V per JEDEC Standard JESD22−A115−A
2. This device meets latchup tests defined by JEDEC Standard JESD78.
3. Moisture Sensitivity Level (MSL) 1.
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NCL30100
ELECTRICAL CHARACTERISTICS (VCC = 12 V, for typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, unless
otherwise noted)
SUPPLY SECTION
Parameter
Conditions
Symbol
Min
Typ
Max
Unit
V(offset)
1.10
1.30
1.45
V
INPUT VOLTAGE COMPENSATION
Offset Voltage
CT Pin Voltage
IVC Current = 25 mA (Including V(offset))
VCT−25mA
1.69
2.08
2.47
V
CT Pin Voltage
IVC Current = 50 mA (Including V(offset))
VCT−50mA
2.12
2.6
3.05
V
IVC pin internal resistance (Note 4)
RIVC
17
kW
CT PIN – OFF TIME CONTROL
Source Current
CT Pin Grounded, 0 v TJ v 85°C
ICT
47.25
50
52.75
mA
Source Current
CT Pin Grounded, −40 v TJ v 125°C
ICT
45.25
50
52.75
mA
VCT(max)
−
4.3
−
V
VCT(min)
−
−
20
mV
CCT
−
8
−
pF
CT Reach VCT Threshold to Gate Output
CTdelay
−
220
−
ns
Minimum Source Current
IVC = 180 mA, CT Pin Grounded,
0 v TJ v 85°C
ICS(min)
11. 75
12.5
13.25
mA
Minimum Source Current
IVC = 180 mA, CT Pin Grounded,
−40 v TJ v 125°C
ICS(min)
11.35
12.5
13.25
mA
Maximum Source Current
IVC = 0 mA, CT Pin Grounded,
0 v TJ v 85°C
ICS(max)
47.25
50
52.75
mA
Maximum Source Current
IVC = 0 mA, CT Pin Grounded,
−40 v TJ v 125°C
ICS(max)
45.25
50
52.75
mA
Vth
−
38
−
mV
CS Falling Edge to Gate Output
CSdelay
−
215
310
ns
Isink = 30 mA
ROL
5
15
40
W
Isource = 30 mA
ROH
20
60
100
W
Startup Threshold
VCC increasing
VCC(on)
−
6.35
6.65
V
Minimum Operating Voltage
VCC decreasing
VCC(off)
5.45
5.85
−
V
VCC(hyst)
−
0.5
−
V
VCC = 6 V
ICC1
−
22
35
mA
Steady State Current Consumption
(Note 4)
CDRV = 0 nF, fSW = 100 kHz, IVC = open,
VCC = 7 V
ICC2
Steady State Current Consumption
CDRV = 1 nF, fSW = 100 kHz, IVC = open,
VCC = 7 V
ICC2
Source Current Maximum Voltage Capability (Note 4)
Minimum CT Pin Voltage (Note 4)
Pin Unloaded, Discharge Switch Turned
on
Pin to ground capacitance (Note 4)
Propagation Delay (Note 4)
CURRENT SENSE
Comparator Threshold Voltage (Note 4)
Propagation Delay
GATE DRIVER
Sink Resistance
Source Resistance
POWER SUPPLY
Vcc Hysteresis (Note 4)
Startup Current Consumption
4. Guaranteed by design
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4
300
0.5
1
mA
1.15
mA
NCL30100
6.260
30
28
26
6.255
6.250
ICC1 (mA)
VCC(on) (V)
24
6.245
22
20
18
16
14
6.240
12
6.235
−40
−20
0
20
40
60
80
100
10
120
−20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 3. Vstartup Threshold vs. Junction
Temperature
Figure 4. Startup Current Consumption vs.
Junction Temperature
12.6
5.780
12.5
5.775
12.4
120
5.770
12.3
12.2
VCC(off) (V)
ICS(min) (mA)
−40
TEMPERATURE (°C)
12.1
12.0
11.9
5.765
5.760
5.755
5.750
11.8
5.745
11.7
11.6
−40
−20
0
20
40
60
80
TEMPERATURE (°C)
100
5.740
120
−40
Figure 5. Minimum Source Current vs.
Junction Temperature
−20
0
20
40
60
80
TEMPERATURE (°C)
100
120
Figure 6. Minimum Operating Voltage
Threshold vs. Junction temperature
50.0
1.10
49.5
ICS(max) (mA)
ICC2 (mA)
1.05
1.00
49.0
48.5
48.0
0.95
47.5
0.90
−40
−20
0
20
40
60
80
TEMPERATURE (°C)
100
47.0
−40
120
Figure 7. Steady State Current Consumption
vs. Junction Temperature
−20
0
20
40
60
80
TEMPERATURE (°C)
100
Figure 8. Maximum Source Current vs.
Junction Temperature
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5
120
55
1.350
50
1.345
45
1.340
V(offset) (V)
Vth (mV)
NCL30100
40
35
30
1.335
1.330
1.325
25
−40
−20
0
20
40
60
80
100
1.320
−40
120
20
40
60
80
100
TEMPERATURE (°C)
Figure 9. Comparator Threshold Voltage vs.
Junction Temperature
Figure 10. Offset Voltage vs. Junction
Temperature
85
51.0
75
50.5
120
50.0
ROH
55
49.5
ICT (mA)
RESISTANCE (W)
0
TEMPERATURE (°C)
65
45
35
49.0
48.5
48.0
25
ROL
15
5
−40
−20
0
20
47.5
40
60
80
100
47.0
−40
120
−20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. Drive Sink and Source Resistance
vs. Junction Temperature
Figure 12. CT Source Current vs. Junction
Temperature
2.60
120
50
45
2.55
40
35
2.50
ICS (mA)
VCT−50mA (V)
−20
2.45
2.40
30
25
20
15
10
2.35
5
2.30
−40
0
−20
0
20
40
60
80
100
120
0
20
40
60
80 100 120 140
160 180 200
TEMPERATURE (°C)
IVC (mA)
Figure 13. CT Pin Voltage vs. Input Voltage
Compensation Current
Figure 14. ICT Dependence on IVC Current
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NCL30100
APPLICATION INFORMATION
The NCL30100 implements a peak current mode control
scheme with a quasi−fixed OFF time. An optional input
feedforward voltage control is provided to enhance
regulation response with widely varying input voltages.
Only a few external components are necessary to implement
the buck converter. The NCL30100 incorporates the
following features:
• Very Low Startup Current: The patented internal supply
block is specially designed to offer a very low current
consumption during startup.
• Negative Current Sensing: By sensing the total current,
this technique does not impact the MOSFET driving
voltage (VGS) during switching. Furthermore, the
programming resistor together with the pin capacitance
forms a residual noise filter which blanks spurious
spikes. This approach also supports a flexible resistor
selection. Finally unlike a positive sensing approach,
there is virtually no power dissipation in the current
sense resistor thus improving efficiency.
• Controller architecture supports high brightness LED
drive current requirements: Selection of the external
n−channel MOSFET can be easily optimized based on
operation voltage, drive current and size giving the
designer flexibility to easily make design tradeoffs.
• Typical $5.5% Current Regulation: The ICS pin offers
$5.5% from 0 to 85°C (+5.5% −9.5% across −40°C to
125°C) accuracy of the current typically, so the LED
peak current is precisely controlled
• No output capacitor is needed: By operating the
controller in continuous conduction mode, it is possible
to eliminate the bulky output filter capacitor.
the switch and the inductor. This approach offers several
benefits over traditional positive current sensing.
• Maximum peak voltage across the current sense resistor
is user controlled and can be optimized by changing the
value of the shift resistor.
• The gate drive capability is improved because the
current sense resistor is located out of the gate driver
loop and does not deteriorate the switch on and also
switch off gate drive amplitude.
• Natural leading edge blanking is filter switching noise
at FET turn−in
• The CS pin is not exposed to negative voltage, which
could induce a parasitic substrate current within the IC
and distort the surrounding internal circuitry.
The current sensing circuit is shown in Figure 15.
IVC
Input Voltage
Regulator
12.5−50 mA
CS
To Latch
Vshift
Rshift
RCS
The following section describes in detail each of the control
blocks
GND
Iprimary
VCS
Current Sensing Block
Figure 15. Primary Current Sensing
The NCL30100 utilizes a technique called negative
current sensing which is used to set the peak current through
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NCL30100
Once the external MOSFET is switched on, the inductor
current starts to flow through the sense resistor RCS. The
current creates a voltage drop VCS on the resistor RCS, which
is negative with respect to GND. Since the comparator
connected to CS pin requires a positive voltage, a voltage
Vshift is developed across the resistor Rshift by a current
source which level−shifts the negative voltage VCS. The
level−shift current is in the range from 12.5 to 50 mA
depending on the optional input voltage compensation loop
control block signal (see more details in the input voltage
compensation section). The peak inductor current is equal
to:
I pk +
I CS @ R shift * V th
From Input Voltage
Compensation Block
VOffset
VOffset to VDD
CT
CT
50 mA
To Latch’s Output
(eq. 1)
R CS
To achieve the best Ipk precision, higher values of ICS
should be used. The Equation 1 shows the higher drop on
RCS reduces the influence of the Vth tolerance. Vth is the
comparator threshold which is nominally 38 mV.
A typical CS pin voltage waveform for continuous
condition mode is shown in Figure 16.
V
To Latch’s Set Input
GND
Figure 17. OFF Time Control
During the switch−on time, the CT capacitor is kept
discharged by an internal switch. As soon as the latch output
changes to a low state, the Isource is enabled and the voltage
across CT starts to ramp−up until its value reaches the
threshold given by the Voffset. The current injected into IVC
can change this threshold. The IVC operation will be
discussed in the next section.
Ishift = 50 mA
V
Ishift = 12.5 mA
VDD
Switch
Turn on
IVC Goes Up
CT pin
Voltage
0
t
IVC Goes Down
Voffset
Figure 16. CS Pin Voltage
I1
I2
I3
0
Figure 16 also shows the effect of the inductor current
based on the range of control possible via the IVC input.
toff−min
t
Figure 18. CT Pin Voltage
OFF Time Control
The voltage that can be observed on CT pin is shown in
Figure 18. The bold line shows the minimum IVC current
when the off time is at its minimum. The amount of current
injected into the IVC input can increase the off time by
changing the turn off comparator switching threshold. I1, I2,
The internal current source, together with an external
capacitor, controls the switch−off time. In addition, the
optional IVC control signal can modulate the off time based
on input line voltage conditions. This block is illustrated in
Figure 17.
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NCL30100
VCC
and I3 represent different delays depending on the
magnitude of IVC.
Current
Mirror
1:1
Gate Driver
The Gate Driver consists of a CMOS buffer designed to
directly drive a power MOSFET. It features unbalanced
source and sink capabilities to optimize switch on and off
performance without additional external components. The
power MOSFET is switched off at high drain current, to
minimize its switch off losses the sink capability of the gate
driver is increased for a faster switch off. On the other hand,
the source capability of the driver is reduced to slow−down
the power MOSFET at switch on in order to reduce EMI
generation. Whenever the IC supply voltage is lower than
the under voltage threshold, the Gate Driver is low, pulling
down the gate to ground thus eliminating the need for an
external resistor.
VOffset
17 kW
IVC
Current
Mirror
1:1
To OFF
Time
Comparator
25 kW
Figure 19. Input Voltage Compensation, OFF Time
Control
Input Voltage Compensation:
OFF Time Comparator Input
Voltage
The Input Voltage Compensation block gives the user
optional flexibility to sense the input voltage and modify the
current sense threshold and off time. This function provides
a feed forward mechanism that can be used when the input
voltage of the controller is loosely regulated to improve
output current regulation. If the input voltage is well
regulated, the IVC input can also be used to adjust the offset
of the off time comparator and the current sense control to
achieve the best current regulation accuracy.
An external resistor connected between IVC and the input
supply results in a current being injected into this pin which
has an internal 17 kW resistor connected to a current mirror.
This current information is used to modify Voffset and ICS.
By changing Voffset the off time comparator threshold is
modified and the off time is increased. A small capacitor
should be connected between the IVC pin and ground to
filter out noise generated during switching period. Figure 19
shows the simplified internal schematic:
V
VDD
Voffset
0
IVC Pin Sink Current
mA
Figure 20. IVC Loop Transfer Characteristic
The transfer characteristic (output voltage to input
current) of the input voltage compensation loop control
block can be seen in Figure 20. VDD refers to the internal
stabilized supply. If no IVC current is injected, the off time
comparator is set to Voffset.
The value of the current injected into IVC also change Ics.
This is accomplished by changing the voltage drop on Rshift.
The corresponding block diagram of the IVC pin can be seen
in Figure 21.
To Current Sense Comparator
17 kW
CS
IVC
Current
Mirror
4:3
37.5 mA
12.5 mA
Figure 21. Input Voltage Compensation Loop – Current Sense Control
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NCL30100
The current sense characteristic can be seen in Figure 22.
As illustrated, by varied the IVC current between 0 − 50 mA,
the sourcing current can range from 12.5 to 50 mA.
V
CS Pin Source Current
50 mA
12.5 mA
0 mA
50 mA
100 mA
mA
140 mA
IVC Pin Sink Current
Figure 22. Current Sense Regulation Characteristic
Biasing the controller
t on + L @
The NCL30010 Vcc input can range up to 18 V. For
applications that have an input voltage that is greater than
that level, an external resistor should be connected between
Vin and the VCC supply capacitor. The value of the resistor
can be calculated as follows:
R2 +
V in * V CC
I CC2
V in
) CS delay
(eq. 4)
Where:
L − Inductor inductance
Ipk − Peak current
As seen from the above equation, the turn on time depends
on the input voltage. In the case of a low voltage AC input
where there is ripple due to the time varying input voltage
and input rectifier, natural frequency dithering is produced
to improve the EMI signature of the LED driver.
The turn off time is determined by the charging of the
external capacitor connected to the CT pin. The minimum
toff value can be computed as:
(eq. 2)
Where:
VCC − Voltage at which IC operates (see spec.)
ICC2 – Current at steady state operation
Vin − Input voltage
The ICC current is composed of two components: The
quiescent current consumption (300 mA) and the switching
current consumption. The driver consumption depends on
the MOSFET selected and the switching frequency. Total
current consumption can be calculated using following
formula:
I CC + 300 @ 10 −6 ) C MOSFET @ V CC @ f switching
I pk
t off + C T @
V offset
I CT
) CT delay
(eq. 5)
Where:
Voffset − Offset voltage (see parametric table)
ICT − CT pin source current (see parametric table)
Finally, the switching frequency then can be evaluated by:
(eq. 3)
In applications where the input voltage Vin is varying
dramatically, a zener can be used to limit the voltage going
into VCC, thus reducing the switching current contribution.
F SW +
1
+
L@I
t on ) t off
pk
V
Switching Frequency
in
1
)
(eq. 6)
C @V
T
offset
) 435 @ 10 −9
50@10 −6
The sum of the nominal CSdelay and CTdelay is
approximately 435 nsec.
The switching frequency varies with the output load and
input voltage. The highest frequency appears at highest
input voltage. Since the peak inductor current is fixed, the
on−time portion of the switching period can be calculated:
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NCL30100
Reverse Buck Operating Description
Figure 23 illustrates a typical application schematic and
Figure 24 displays simplified waveforms illustrate the
converter in steady state operation for critical circuit nodes.
Imag
D1
Vin
ICS
Rshift
ICT
Idemag
IC1
NCL30100
1
CS
2
GND
3
CT
6
DRV
VCC
5
IVC
4
L1
Q1
VCS
Vsense
CT
VCT
VDRV
Rsense
Figure 23. Simplified Application Schematic
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LED
NCL30100
Vcc
VDRV
0
Ipk
Imag
0
Idemag
Imin
0
I LED
0
50 uA
ICT
0
VCT
0
0
V Sense
I CS
0
VCS
38 mV
0
Figure 24. Voltage and Current Nodes in the Application Circuit
The current follows the red line in Figure 23 when Q1 is
turned on. The converter operates in continuous conduction
mode therefore the current through the inductor never goes
to zero. When the switch is on, the current creates a negative
voltage drop on the Rsense resistor. This negative voltage can
not be measured directly by the IC so an Rshift resistor is
connected to CS pin. Inside the IC there is a current source
connected to this pin. This current source creates constant
voltage drop on resistor Rsense which shifts the negative
voltage drop presented on Rsense positive. The magnetizing
current Imag increases linearly, the negative voltage on
Rsense increased as well. Thus the voltage on CS pin
approaching zero. On the CS pin there is a comparator with
a reference level of 38 mV. Once the voltage on the CS pin
reaches this reference level, the DRV output is turned off and
current path Imag disappears. Energy stored in the inductor
as a magnetic field keeps current flowing in the same
direction. The current path is now closed via diode D1
(green line). Once the DRV is turned off, the internal current
source starts to charge the CT capacitor and the voltage on
this node increases. Once the CT capacitor voltage reaches
the VCT level, Q1 is turned on and an internal switch
discharges the CT capacitor to be ready for the next
switching cycle.
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NCL30100
Application Design Example:
A typical step down application will be used to illustrate the basic design process based on nominal design parameters:
• Input voltage:
Vin − 12 Vac (12 V dc after the bridge)
•
•
•
•
•
Nominal LED current:
700 mA (rms)
LEDripple:
120 mA (peak−to−peak)
VLED:
3.2 V
Freewheel diode Vf:
0.5 V
Target Switching Frequency:
450 kHz
Dimming using PWM signal 1 kHz with duty cycle 0 – 99%
12 V
Vac
A
D4
R2
D5
Vac
D3
NCL30100
IC1
R3
D7
D1
R1
C1
D6
CS
R5
L3
DRV
K
Q1
GND VCC
CT
IVC
C2
Q2
D2
C5
C3
R4
R9
DIMM
0/5 V
R8
Figure 25. Example Design Schematic
Note this simplified step−by−step design process neglects
any parasitic contribution of the PCB.
First, we need to determine the nominal tON/tOFF ratio:
V LED ) V f
3.2 ) 0.5
3.7
t on
+
+
+
t off
12 * 3.2
8.8
V in * V LED
Now all the parameters are defined to calculate inductor
value:
V+
di @ L
(eq. 7)
+
Next the typical duty cycle (DC) will be calculated:
DC +
t ON
t ON ) t OFF
+
3.7
+ 0.296
3.7 ) 8.8
1
f op
+
1
450 @ 10 3
+ 2.222 ms
ǒV IN * V LEDǓ @ t ON
I ripple
(12 * 3.2) @ 658 @ 10 −9
0.12
(eq. 11)
^ 48.3 mH
A standard value 47 mH is chosen.
Next the CT capacitor can be calculated, but we need to
first determine the IVC current which can be simply
calculated.
(eq. 8)
Target switching frequency is set at 450 kHz, now we need
to determine the period:
T+
dt
åL+
I IVC +
(eq. 9)
V
12
+
^ 7.91 mA
6
R ) R IVC
1.5 @ 10 ) 17 @ 10 3
(eq. 12)
The IVC current controls the dependence of the peak
current to the input voltage. If the input voltage is well
regulated, the IVC pin should be grounded. The value for
IVC resistor should be chosen based on graphs below.
Note as well that the IVC can be used to implement analog
dimming since increasing the current into IVC pin will
decrease the Ipeak of the LED).
Combination the previous equation we can calculate the tON
and tOFF durations:
t ON + DC @ T + 0.296 @ 2.222 @ 10 −6 + 658 ns (eq. 10)
t OFF + (1 * DC) @ T + (1 * 0.296) @ 2.222 @ 10 −6
+ 1.564 ms
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13
NCL30100
600
1000
900
500
800
400
ILED (mA)
ILED (mA)
700
600
Rivc = 300k
500
Rivc = 510k
400
Rivc = 1 Meg
Rivc = 300k
200
Rivc = 1 Meg
Rivc = 510k
Rivc = 1.5 Meg
300
Rivc = 1.5 Meg
Rivc = 2.2 Meg
200
100
300
Rivc = 3.7 Meg
Rivc = infinity
7
8
9
10
Rivc = 2.2 Meg
100
11 12 13 14 15
INPUT VOLTAGE (V)
16
17
0
18
Rivc = 3.7 Meg
Rivc = infinity
7
Figure 26. Rivc Impact versus Vin for ILED =
700 mA Nominal
−0.097 @ X 2 ) 24.5 @ X ) 1358.1
[V]
976.8
(eq. 13)
−0.097 @ 7.91 2 ) 24.5 @ 7.91 ) 1358.1
976.8
+
dt
å C CT +
I CS + −0.75 @ IVC ) 50 @ 10 −6
50 @ 10 −6 @ ǒ1.654 @ 10 −6 * 220 @ 10 −9Ǔ
1.58
17
18
(eq. 16)
(eq. 17)
+ −0.75 @ 7.91 @ 10 −6 ) 50 @ 10 −6 ^ 44.07 mA
To calculate Rshift it is necessary to know the Ipk current
through the inductor. From the time that the current sense
comparator detects that the peak current threshold has been
crossed to the time that the external MOSFET switch is
turned off there is a propagation delay. Depending on the
value of the inductor selected (which is based on the target
switching frequency), there is a current error between the
intended peak current and the actual peak current, this is
illustrated in Figure 28.
I CT @ ǒt OFF * CT delayǓ
V CT
16
Therefore:
(eq. 14)
The CT capacitance can be calculated using the equations
above:
I+
11 12 13 14 15
INPUT VOLTAGE (V)
I CS + −0.75 @ IVC ) 50 @ 10 −6 [mA]
^ 1.58 V
dv @ C
10
calculated value is not standard, so the nearest value 33 pF
has been selected.
Now we can calculate the IPK of LED. The average value
is set to 700 mA and the target ripple is set at 120 mA, the
IPK equals 760 mA. Rshift has been chosen to be as small a
voltage drop as possible to minimize power dissipation so an
Rshift of 100 mW has been selected.
Before calculation of Rshift we need to know the ICS
current, which affects the offset on Rshift. The ICS value
dependents on the IVC current and for IVC currents between
0 − 50 mA, it can be described by this formula:
Using the result from Equation 12 and put it to Equation 13
the VCT threshold will be calculated:
V CT +
9
Figure 27. Rivc Impact versus Vin for ILED =
350 mA Nominal
A value 1.5 MW was used since the input voltage has a
sinusoidal component due to the low voltage AC input and
desires to have a small bulk capacitance, thus compensating
for part of this variation.
The dependence of VCT on IVC current is described by the
following equation:
V CT +
8
(eq. 15)
^ 45.8 pF
The intrinsic pin capacitance CT pin (~8 pF) in
conjunction with the dimming transistor (~10 pF) in this
schematic approximately 18 pF so this value must be
subtracted from the calculated value in Equation 15. The
http://onsemi.com
14
NCL30100
Ipeak
Ics
ILED
ΔiL
td
(Vin-VLED)
-VLED - Vdiode
L
L
ton
toff
Figure 28. A Current Error Between the Intended Peak Current and the Actual Peak Current
V+
di @ L
dt
å I delay +
V@t
L
+
Using the PDIE, we can calculate junction temperature:
8.8 @ 215 @ 10 −9
47 @ 10 −6
(eq. 18)
Temp IC + T A ) P DIE @ R qJA + T A ) 0.0399 @ 178
^ 0.0402 A
+ T A ) 7.1° C
V/L is simply the slew rate through the inductor and td is
the internal propagation delay so the current overshoot from
target is approximately 40 mA as calculated in Equation 18.
All values necessary for Rshift calculation are known, the
Rshift value is described by this formula:
R shift +
+
A design spreadsheet to aid in calculating the external
components necessary for a specific set of operating
conditions is available for download at the
ON Semiconductor website.
For a low voltage AC input diode D3 is placed into the Vcc
line. Since Capacitor C3 is charged from a sinusoidal
voltage. If the input voltage approaches zero, the IC is still
supplied from C3. Due to this diode, the IC keeps the LED
driver operating even if the sinusoidal voltage is lower than
VCC(min) until Vin is lower than VLED. The use of this diode
make sense only if a single LED is used and the converter is
supplied by sinusoidal voltage 12 Vac. For two LEDs in
series their forward voltage is almost as high as VCC(min) of
the IC.
Parasitic capacitance and inductance are presented in real
applications which will have an influence on the circuit
operation. They are depending on the PCB design which is
user dependent. The BOM, PCB and some plots are enclosed
for better understanding of the system behavior.
R sense @ ǒI pk * I delayǓ ) V th
I CS
0.1 @ (0.76 * 0.0402) ) 0.038
44.07 @ 10 −6
(eq. 19)
^ 2496 W
This value of resistance can be a parallel combination of
2.7 kW and 30 kW.
To understand the operating junction temperature, we
calculate the die power dissipation:
P DIE + V CC @ ǒ300 @ 10 −6 ) C MOSFET @ V CC @ f switchingǓ
+ 12 @ ǒ300 @ 10 −6 ) 560 @ 10 −12 @ 12 @ 450 @ 10 3Ǔ
+ 39.8 mW
(eq. 21)
(eq. 20)
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15
NCL30100
Figure 29. PCB Design the Circuit Calculated Above.
Only Single Layer PCB is Used for the Application.
Figure 30. The Component Side (Several Transistor
Packages are Possible to Use)
BILL OF MATERIALS FOR THE SINGLE LAYER EVALUATION BOARD (NCL30100ASLDGEVB)
Designator
Qty
Description
Value
Tol
Footprint
Manufacturer
Manufacturer
Part Number
Substitution
Allowed
Pb−Free
C1
1
Capacitor
2.2 mF / 25 V
10%
0805
AVX
08053C225KAT2A
Yes
Yes
C2
1
Capacitor
33 pF
5%
0603
Kemet
C0603C330J5GACTU
Yes
Yes
C3
1
Capacitor
4.7 mF / 25 V
10%
0805
AVX
08053D475KAT2A
Yes
Yes
C5
1
Capacitor
1 nF
10%
0603
Kemet
C0603C104K5RACTU
Yes
Yes
D1
1
Surface
Mount
Schottky
Power
Rectifier
MBR130T3G
−
SOD−123
ON Semiconductor
MBR130T3G
No
Yes
D2
1
Zener
Diode
16 V
5%
SOD−123
ON semiconductors
MMSZ16T1G
No
Yes
D3
1
Schottky
Diode
NSR0520V2T1G
−
SOD−523
ON semiconductors
NSR0520V2T1G
No
Yes
D4,
D5,
D6,
D7
4
Schottky
Diode
NSR0340HT1G
−
SOD−323
ON semiconductors
NSR0340HT1G
No
Yes
IC1
1
LED
Driver
NCL30100
−
TSOP−6
ON semiconductors
NCL30100SNT1G
No
Yes
L3
1
Inductors
47 mH
10%
WE−PD2_M
Wurth Electronik
744774147
No
Yes
Q1
1
Power
MOSFET
NTGS4141NT1G
−
TSOP−6
ON semiconductors
NTGS4141NT1G
No
Yes
Q2
1
Power
MOSFET
NU
−
SOT−223
ON semiconductors
NTF3055−100T1G
No
Yes
Option
Q2
1
Power
MOSFET
NU
−
DPAK
ON semiconductors
NTD23N03RT4G
No
Yes
Option
Q2
1
Power
MOSFET
NU
−
SOT−363
ON semiconductors
NTJS4160NT1G
No
Yes
Option
Q2
1
Power
MOSFET
NU
−
SOT−23
ON semiconductors
NTR4170NT1G
No
Yes
Option
Q3
1
General
Purpose
Transistor
NPN
BC817−16
−
SOT−23
ON semiconductors
BC817−16LT1G
No
Yes
http://onsemi.com
16
Comments
NCL30100
BILL OF MATERIALS FOR THE SINGLE LAYER EVALUATION BOARD (NCL30100ASLDGEVB)
Designator
Qty
Q3
1
R1
Description
Value
Tol
Footprint
Manufacturer
Manufacturer
Part Number
Substitution
Allowed
Pb−Free
Comments
Power
MOSFET
NU
−
SOT−23
ON semiconductors
NTS4001NT1G
No
Yes
Option
1
Resistor
1.5 M
1%
0603
Rohm Semiconductor
MCR03EZPFX1504
Yes
Yes
R2
1
Resistor
300 R
1%
0603
Rohm Semiconductor
MCR03EZPFX3000
Yes
Yes
R3
1
Resistor
30 k
1%
0603
Rohm Semiconductor
MCR03EZPFX3002
Yes
Yes
R4
1
Resistor
0.1 R
1%
0805
Welwyn
LRCS0805−0R1FT5
Yes
Yes
R5
1
Resistor
2.7 k
1%
0603
Rohm Semiconductor
MCR03EZPFX2701
Yes
Yes
R8
1
Resistor
10 k
1%
0603
Rohm Semiconductor
MCR03EZPFX1002
Yes
Yes
R9
1
Resistor
5.6 k
1%
0603
Rohm Semiconductor
MCR03EZPFX5601
Yes
Yes
Figure 31. Completed PCB with Devices
Figure 32. Snapshot of CT Pin Voltage, Driver and
ILED
Figure 33. Voltage Measured on RCS (R4)
http://onsemi.com
17
NCL30100
Figure 34. Current Through LED if 50% Dimming
at 1 kHz is Applied
Figure 35. The Dimming Detail at 95%. No Overshoot
in LED Current is Observed
real world application is dependent on the characteristics of
the actual dimmer and the electronic transformer used to
generated to chopped AC waveform
Figures 36 and 37 illustrate leading edge and trailing edge
waveforms from a chopped AC source. For proper dimming
control, the bulk capacitance must be reduced to a relatively
small value to achieve best dimming range. Performance in
Figure 36. Trailing Edge Dimming
Figure 37. Leading Edge (Triac) Regulation. Small
Overshoot is Seen on the Leading Edge, this is
Based on the Abrupt Chopping of the Low Voltage
AC Waveform
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18
NCL30100
Figure 38. ILED and Vin Waveform if No Dimming is Used
84
83
680
82
CURRENT (mA)
EFFICIENCY (%)
690
DC Voltage Efficiency
(No Bridge Rectifier)
81
80
79
78
77
7
670
660
650
640
630
8
9
10
11
12
13
INPUT VOLTAGE (V)
14
15
620
16
LED Current Variation
7
Figure 39. Efficiency Measurement for the
Demoboard (Vf = 3.2 Nominal)
8
9
10
11
12
13
INPUT VOLTAGE (V)
14
15
16
Figure 40. ILED Current Dependence on Input
DC Voltage (No Bridge Rectifier is Used)
Figure 39 represents the efficiency of the converter
driving a single LED at a nominal current of 690 mA. The
addition of the AC bridge rectifier contributes addition
losses into the circuit and it is recommended to us low
forward voltage schottky rectifiers to minimize power
dissipation in the AC rectification stage.
MR 16 Evaluation Board Information
A specific two sided demo board was designed to fit with
the MR 16 form factor. The schematic is almost the same for
both, but the PWM dimming control circuitry has been
removed. If the same components are used, the operation
frequency will be slightly higher due to the lower pin
capacitance because the dimming transistor contribution is
removed.
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19
NCL30100
12 V
X2
A
D3
D7
D4
D1
R1
C1
D5
X3
D6
R2
R3
NCL30100
R5
GND VCC
CS
CT
DRV
L1
Q1
K
IVC
C2
C4
C3
D2
R4
Figure 41. Schematic MR 16 Application
Figure 42. PCB Top Side MR 16 Application
Figure 43. PCB Top Side Devices Placement
Figure 44. PCB Bottom Side MR 16 Application
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20
NCL30100
Figure 45. PCB Bottom Side Devices Placement
Figure 46. Top Side Photo
Figure 47. Bottom Side Photo
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21
NCL30100
BILL OF MATERIALS FOR THE MR 16 EVALUATION BOARD (NCL30100ADLMGEVB)
Designator
Qty
Description
Value
Tol
Footprint
Manufacturer
Manufacturer
Part Number
Substitution
Allowed
Pb−Free
C1
1
Capacitor
2.2 mF / 25 V
10%
0805
AVX
08053C225KAT2A
Yes
Yes
C2
1
Capacitor
33 pF
5%
0603
Kemet
C0603C330J5GACTU
Yes
Yes
C3
1
Capacitor
4.7 mF / 25 V
10%
0805
AVX
08053D475KAT2A
Yes
Yes
C4
1
Capacitor
1 nF
10%
0603
Kemet
C0603C104K5RACTU
Yes
Yes
D1
1
Surface
Mount
Schottky
Power
Rectifier
MBR130T3G
−
SOD−123
ON Semiconductor
MBR130T3G
No
Yes
D2
1
Zener
Diode
16 V
5%
SOD−523
ON Semiconductor
MM5Z16VT1G
No
Yes
D3,
D4,
D5,
D6
4
Schottky
Diode
NSR0340HT1G
−
SOD−323
ON Semiconductor
NSR0340HT1G
No
Yes
D7
1
Schottky
Diode
NSR0520V2T1G
−
SOD−523
ON Semiconductor
NSR0520V2T1G
No
Yes
IC1
1
LED
Driver
NCL30100
−
TSOP−6
ON Semiconductor
NCL30100SNT1G
No
Yes
L1
1
Inductors
47 mH
10%
WE−PD2_M
Wurth Electronik
744774147
No
Yes
Q1
1
Power
MOSFET
NTGS4141NT1G
−
TSOP−6
ON Semiconductor
NTGS4141NT1G
No
Yes
Q1
1
Power
MOSFET
NU
−
SOT−223
ON Semiconductor
NTF3055−100T1G
No
Yes
Option
Q1
1
Power
MOSFET
NU
−
SOT−363
ON Semiconductor
NTJS4160NT1G
No
Yes
Option
Q1
1
Power
MOSFET
NU
−
SOT−23
ON Semiconductor
NTR4170NT1G
No
Yes
Option
R1
1
Resistor
1.5 M
1%
0603
Rohm Semiconductor
MCR03EZPFX1504
Yes
Yes
R2
1
Resistor
300 R
1%
0603
Rohm Semiconductor
MCR03EZPFX3000
Yes
Yes
R3
1
Resistor
30 k
1%
0603
Rohm Semiconductor
MCR03EZPFX3002
Yes
Yes
R4
1
Resistor
0.1 R
1%
0805
Welwyn
LRCS0805−0R1FT5
Yes
Yes
R5
1
Resistor
2.7 k
1%
0603
Rohm Semiconductor
MCR03EZPFX2701
Yes
Yes
Comments
Application Design Example for an Offline (115 Vac) Buck Application:
In addition to traditional DC−DC applications, the NCL30100 can also be used in offline applications, a schematic and PCB
layout are provided to illustrate a typical circuit configuration.
• Input voltage:
Vin − 115 Vac
•
•
•
•
•
Nominal LED current:
700 mA (rms)
LEDripple:
120 mA (peak−to−peak)
VLED:
3.2 V
Freewheel diode Vf:
0.5 V
Target Switching Frequency:
50 kHz
Dimming using PWM signal 1 kHz with duty cycle 0 – 99%
In this application example, there is schematic and PCB only. The design steps are the same as above mentioned.
http://onsemi.com
22
NCL30100
D1
MRA4003
Vac
L1
A
100u
R1
24k
C1
CX1
D3
MRA4003
C2
47n
2.2u
2.2n
D4
MRA4003
IC1
NCL30100
R3
150k
Vac
CS
D6
MRA4003
D2
MURA130
R2
24k
D5
1N4148
L2
DRV
Q1
1mH
GND VCC
R4
5.6k
C3
10p
CT
C4
560p
MTD6N20ET
IVC
C5
1u
R5
R33
DIMM
0/5 V
R6
5.6k
K
Q2
BC817−16L
D7
16V
GND
R7
10k
Figure 48. Design Example Schematic of 115 Vac Converter
by resistors R3, R4 and R5. In this case Rsense is 0.33 W to
reach higher accuracy. A small capacitor C3 is used to filter
out spikes which are generated during the turn off of diode
D2. It is recommended to use L2 with low series resistance
since current is flowing through the inductor continuously
and D2 should be selected for low forward voltage drop and
fast reverse recovery time.
The input voltage in range 85−140 Vac is rectified by
bridge rectifier D1, D3, D4 and D6. To limit current peaks
generated during on time period, capacitor C1 is used. CX1,
C2 and L1 are an EMI filter to protect mains against current
spikes mainly generated by D2 if Q1 is turned on. The
NCL30100 is powered through resistors R1 and R2. The
Vcc voltage is limited by D7. Maximum LED current is set
Figure 49. Component Side
Figure 50. Single Layer PCB
Design for this Application
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23
NCL30100
Figure 51. ILED and Vin Waveform
Figure 52. ILED at the Peak of Sinusoidal Voltage
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24
NCL30100
Figure 53. Input Voltage and Input Current
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25
NCL30100
BILL OF MATERIALS FOR THE NCL30100 115 Vac
Designator
Qty
Description
Value
Tol
Footprint
Manufacturer
Manufacturer
Part Number
Substitution
Allowed
Pb−Free
C1
1
Capacitor
2.2 mF / 200 V
10%
E3.5−8
Koshin
KR1 2.2u 200V 8X11.5
Yes
Yes
C2
1
Capacitor
47 nF
10%
1206
Yageo
CC1206KKX7RABB473
Yes
Yes
C3
1
Capacitor
10 pF
5%
0603
Kemet
C0603C100J5GACTU
Yes
Yes
C4
1
Capacitor
560 pF
5%
0603
Kemet
C0603C561J5GACTU
Yes
Yes
C5
1
Capacitor
1 mF / 25 V
10%
0805
AVX
08053D105KAT2A
Yes
Yes
D1,
D3,
D4,
D6
4
Standard
Recovery
Power
Rectifier
MRA4003T3G
−
SMA
ON Semiconductor
MRA4003T3G
No
Yes
D2
1
Ultrafast
Power
Rectifier
MURA130T3G
−
SMA
ON Semiconductor
MURA130T3G
No
Yes
D5
1
Standard
Diode
MMSD4148
−
SOD−123
ON Semiconductor
MMSD4148T1G
No
Yes
D7
1
Zener Diode
16 V
5%
SOD−123
ON Semiconductor
MMSZ16VT1G
No
Yes
IC1
1
LED Driver
NCL30100
−
TSOP−6
ON Semiconductor
NCL30100SNT1G
No
Yes
L1
1
Inductors
100 mH
10%
WE−PD4_L
Wurth Electronik
7445620
No
Yes
L2
1
Inductors
1 mH
10%
WE−PD_XXL
Wurth Electronik
7447709102
No
Yes
Q1
1
Power
MOSFET
MTD6N20
−
DPAK
ON Semiconductor
MTD6N20ET4G
No
Yes
Q2
1
General
Purpose
Transistor
NPN
BC817−16
−
SOT−23
ON Semiconductor
BC817−16LT1G
No
Yes
Q2
1
Power
MOSFET
NU
−
SOT−23
ON Semiconductor
NTS4001NT1G
No
Yes
R1,
R2
2
Resistor
24 k
1%
0806
Rohm Semiconductor
MCR06EZPFX2402
Yes
Yes
R3
1
Resistor
150 k
1%
0603
Rohm Semiconductor
MCR03EZPFX1503
Yes
Yes
R4,
R6
2
Resistor
5.6 k
1%
0603
Rohm Semiconductor
MCR03EZPFX5601
Yes
Yes
R5
1
Resistor
0.33 R
1%
0805
Welwyn
LRCS0805−0R33FT5
Yes
Yes
R7
1
Resistor
10 k
1%
0603
Rohm Semiconductor
MCR03EZPFX1002
Yes
Yes
CX1
1
EMI
Suppression
Capacitor
2.2 nF / 300 V
20%
XC10B5
Epcos
B32021A3222M289
Yes
Yes
http://onsemi.com
26
Comments
Option
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSOP−6
CASE 318G−02
ISSUE V
1
SCALE 2:1
D
H
ÉÉ
ÉÉ
6
E1
1
NOTE 5
5
2
L2
4
GAUGE
PLANE
E
3
L
b
SEATING
PLANE
C
DETAIL Z
e
DIM
A
A1
b
c
D
E
E1
e
L
L2
M
c
A
0.05
M
DATE 12 JUN 2012
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM
LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D
AND E1 ARE DETERMINED AT DATUM H.
5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.
A1
DETAIL Z
MIN
0.90
0.01
0.25
0.10
2.90
2.50
1.30
0.85
0.20
0°
MILLIMETERS
NOM
MAX
1.00
1.10
0.06
0.10
0.38
0.50
0.18
0.26
3.00
3.10
2.75
3.00
1.50
1.70
0.95
1.05
0.40
0.60
0.25 BSC
10°
−
STYLE 1:
PIN 1. DRAIN
2. DRAIN
3. GATE
4. SOURCE
5. DRAIN
6. DRAIN
STYLE 2:
PIN 1. EMITTER 2
2. BASE 1
3. COLLECTOR 1
4. EMITTER 1
5. BASE 2
6. COLLECTOR 2
STYLE 3:
PIN 1. ENABLE
2. N/C
3. R BOOST
4. Vz
5. V in
6. V out
STYLE 4:
PIN 1. N/C
2. V in
3. NOT USED
4. GROUND
5. ENABLE
6. LOAD
STYLE 5:
PIN 1. EMITTER 2
2. BASE 2
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
6. COLLECTOR 2
STYLE 6:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. EMITTER
5. COLLECTOR
6. COLLECTOR
STYLE 7:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. N/C
5. COLLECTOR
6. EMITTER
STYLE 8:
PIN 1. Vbus
2. D(in)
3. D(in)+
4. D(out)+
5. D(out)
6. GND
STYLE 9:
PIN 1. LOW VOLTAGE GATE
2. DRAIN
3. SOURCE
4. DRAIN
5. DRAIN
6. HIGH VOLTAGE GATE
STYLE 10:
PIN 1. D(OUT)+
2. GND
3. D(OUT)−
4. D(IN)−
5. VBUS
6. D(IN)+
STYLE 11:
PIN 1. SOURCE 1
2. DRAIN 2
3. DRAIN 2
4. SOURCE 2
5. GATE 1
6. DRAIN 1/GATE 2
STYLE 12:
PIN 1. I/O
2. GROUND
3. I/O
4. I/O
5. VCC
6. I/O
STYLE 13:
PIN 1. GATE 1
2. SOURCE 2
3. GATE 2
4. DRAIN 2
5. SOURCE 1
6. DRAIN 1
STYLE 14:
PIN 1. ANODE
2. SOURCE
3. GATE
4. CATHODE/DRAIN
5. CATHODE/DRAIN
6. CATHODE/DRAIN
STYLE 15:
PIN 1. ANODE
2. SOURCE
3. GATE
4. DRAIN
5. N/C
6. CATHODE
STYLE 16:
PIN 1. ANODE/CATHODE
2. BASE
3. EMITTER
4. COLLECTOR
5. ANODE
6. CATHODE
STYLE 17:
PIN 1. EMITTER
2. BASE
3. ANODE/CATHODE
4. ANODE
5. CATHODE
6. COLLECTOR
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
6X
0.60
XXXAYWG
G
1
6X
3.20
XXX
A
Y
W
G
0.95
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB14888C
TSOP−6
1
IC
0.95
XXX MG
G
= Specific Device Code
=Assembly Location
= Year
= Work Week
= Pb−Free Package
STANDARD
XXX = Specific Device Code
M
= Date Code
G
= Pb−Free Package
*This information is generic. Please refer to device data sheet
for actual part marking. Pb−Free indicator, “G” or microdot “
G”, may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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