Dimmable Power Factor
Corrected LED Driver
Featuring Primary Side CC /
CV Control
NCL30386
The NCL30386 is a power factor corrected controller targeting
isolated and non−isolated “smart−dimmable” constant−current LED
drivers. Designed to support flyback, buck−boost and SEPIC
topologies, the controller operates in a quasi−resonant mode to
provide high efficiency. Thanks to a novel control method, the device
is able to tightly regulate a constant LED current and voltage from the
primary side. This removes the need for secondary−side feedback
circuitry, its biasing and for an optocoupler. The device also provides
near−unity power factor correction.
The device is highly integrated with a minimum number of external
components. A robust suite of safety protection is built in to simplify
the design. This device is specifically intended for very compact space
efficient designs and supports analog and digital dimming with two
dedicated dimming inputs control ideal for Smart LED Lighting
applications.
Features
•
•
•
•
•
•
•
•
•
•
•
High Voltage Startup
Quasi−resonant Peak Current−mode Control Operation
Primary Side Feedback
CC / CV Control
Tight LED Constant Current Regulation of ±2% Typical
Digital Power Factor Correction
Analog and Digital Dimming
Cycle by Cycle Peak Current Limit
Wide Operating VCC Range
−40 to + 125°C
Robust Protection Features
♦ Brown−Out
♦ OVP on VCC
♦ Constant Voltage / LED Open Circuit Protection
♦ Winding Short Circuit Protection
♦ Secondary Diode Short Protection
♦ Output Short Circuit Protection
♦ Thermal Shutdown
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MARKING
DIAGRAM
9
9
L30386x
ALYWX
G
1
SOIC−9
CASE 751BP
L30386
x
A
L
Y
W
G
1
= Specific Device Code
= Version
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
HV
ADIM
1
COMP
2
ZCD
3
8
PDIM
CS
4
7
VCC
GND
5
6
DRV
10
ORDERING INFORMATION
See detailed ordering and shipping information on page 18 of
this data sheet.
Typical Applications
• Integral LED Bulbs
• LED Power Driver Supplies
• LED Light Engines
© Semiconductor Components Industries, LLC, 2018
July, 2020 − Rev. 3
1
Publication Order Number:
NCL30386/D
NCL30386
.
.
Aux
.
VADIM
NCL30386
1
10
2
9
3
8
4
7
5
6
PWM signal
Figure 1. Typical Application Schematic for NCL30386
PIN FUNCTION DESCRIPTION NCL30386
Pin N5
Pin Name
Function
1
ADIM
Analog dimming
Pin Description
2
COMP
OTA output for CV loop
This pin receives a compensation network to stabilize the CV loop
3
ZCD
Zero crossing Detection
Vaux sensing
This pin connects to the auxiliary winding and is used to detect the core reset event.
This pin also senses the auxiliary winding voltage for accurate output voltage control
4
CS
Current sense
5
GND
−
6
DRV
Driver output
7
VCC
Supplies the controller
8
PDIM
PWM dimming
9
NC
creepage
10
HV
High Voltage sensing
This pin is used for analog control of the output current. Applying a voltage varying
between VDIM(EN) and VDIM100 will dim the output current from 0.5% to 100%.
This pin monitors the primary peak current.
The controller ground
The driver’s output to an external MOSFET
This pin is connected to an external auxiliary voltage.
This pin is used PWM dimming control. An optocoupler can be connected directly to
the pin if the PWM control signal is from the secondary side
This pin connects after the diode bridge to provide the startup current and internal
high voltage sensing function.
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2
NCL30386
INTERNAL CIRCUIT ARCHITECTURE
CS_shorted
Enable
V REF
OFF
f_OVP
Internal
Thermal
Shutdown
V DD
STOP
VCC
UVLO
Fault
Management
VCC Management
Latch
UVP
COMP
VCC_max
Ipkmax
Qdrv
BO_NOK
V HVdiv
FF_mode
V HVdiv V REFX
BO_NOK
ZCD
f_OVP
Zero Crossing Detection Logic
(ZCD Blanking, Time−Out, ...)
S
UVP
Q
V HVdiv
VCC
Qdrv
Clamp
Circuit
Q
DRV
R
Line
feed−forward
Leading
Edge
Blanking
STOP
V REF(PFC)
CS_reset
Constant−Current Control
V DIMA
Ipkmax
ADIM
Enable
V DIMA
Max. Peak
Current
Limit
Ipkmax
CS Short
Protection
CS_shorted
Winding and
Output diode
Short Circuit
Protection
Analog
Dimming
STOP
Enable
GND
HV
Brown−Out
FF_mode
Valley Selection
Frequency Foldback
Under Voltage Protection
CS
HV
STUP
WOD_SCP
V CV
Constant Voltage Control
VCC Over Voltage
Protection
V CV
dc_DIM
dc_DIM
PWM
Dimming
VREFX
setpoint
V REFX
V HVdiv
WOD_SCP
Generation of the
Reference Voltage
for Power Factor Corr.
Figure 2. Internal Circuit Architecture NCL30386
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3
V REF(PFC)
PDIM
NCL30386
MAXIMUM RATINGS TABLE
Symbol
VCC(MAX)
ICC(MAX)
Rating
VDRV(MAX) Maximum driver pin voltage, DRV pin, continuous voltage
IDRV(MAX) Maximum current for DRV pin
VHV(MAX)
IHV(MAX)
Value
Unit
−0.3 to 30
Internally limited
V
mA
−0.3, VDRV (Note 1)
−300, +500
V
mA
−0.3, +700
±20
V
mA
−0.3, 5.5 (Note 2)
−2, +5
V
mA
Maximum Power Supply voltage, VCC pin, continuous voltage
Maximum current for VCC pin
Maximum voltage on HV pin
Maximum current for HV pin (dc current self−limited if operated within the allowed range)
VMAX
IMAX
Maximum voltage on low power pins (except pins HV, DRV and VCC)
Current range for low power pins (except pins HV, DRV and VCC)
RθJ−A
Thermal Resistance Junction−to−Air
180
°C/W
Maximum Junction Temperature
150
°C
Operating Temperature Range
−40 to +125
°C
Storage Temperature Range
−65 to +150
°C
TJ(MAX)
ESD Capability, HBM model except HV pin (Note 3)
4
kV
ESD Capability, HBM model HV pin
700
V
ESD Capability, MM model (Note 3)
200
V
1
kV
ESD Capability, CDM model (Note 3)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. VDRV is the DRV clamp voltage VDRV(high) when VCC is higher than VDRV(high). VDRV is VCC otherwise.
2. This level is low enough to guarantee not to exceed the internal ESD diode and 5.5 V ZENER diode. More positive and negative voltages
can be applied if the pin current stays within the −2 mA / 5 mA range.
3. This device series contains ESD protection and exceeds the following tests: Human Body Model 4000 V per Mil−Std−883, Method 3015.
Charged Device Model 2000 V per JEDEC Standard JESD22−C101D.
4. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V, , VCS = 0 V)
For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V)
Test Condition
Symbol
Min
High voltage current source
VCC = VCC(on) – 200 mV
IHV(start2)
3.3
High voltage current source
VCC = 0 V
IHV(start1)
VCC = 0 V
VHV(MIN)
VHV = 450 V
IHV(leak)
Description
Typ
Max
Unit
4.7
6.1
mA
HIGH VOLTAGE SECTION
VCC level for IHV(start1) to IHV(start2) transition
300
VCC(TH)
Minimum startup voltage
HV source leakage current
Maximum rms input voltage for correct constant−current operation
(TJ = −20°C to 125°C)
mA
2
−
V
17
−
V
4.5
10
mA
VHV(OL)
265
Vrms
VCC(on)
VCC(on2)
VCC(off)
VCC(HYS)
VCC(reset)
16
9.77
8.2
7.8
4
18
10.80
8.6
−
5
20
11.24
9.4
−
6
Over Voltage Protection
VCC OVP threshold
VCC(OVP)
25
26.5
28
V
VCC(off) noise filter (Note 6)
VCC(reset) noise filter (Note 6)
tVCC(off)
tVCC(reset)
−
−
5
20
−
−
ms
ICC1
ICC2
ICC3
ICC4
1.2
–
−
−
1.5
3.0
3.3
2.9
1.8
3.5
4.0
3.4
SUPPLY SECTION
Supply Voltage
Startup Threshold
Threshold for turning off DSS (Note 5)
Minimum Operating Voltage
Hysteresis VCC(on) – VCC(off)
Internal logic reset
Supply Current
Device Disabled/Fault
Device Enabled/No output load on pin 5
Device Switching (Fsw = 65 kHz)
Device switching (Fsw = 15 kHz)
VCC increasing
VCC increasing
VCC decreasing
VCC decreasing
VCC > VCC(off)
Fsw = 65 kHz
CDRV = 470 pF, Fsw = 65 kHz
VREFX = 10%of max value
5. Refer to ordering table option at the end of the document.
6. Guaranteed by design.
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4
V
mA
NCL30386
ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V, , VCS = 0 V)
For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V)
Description
Test Condition
Symbol
Min
Typ
Max
Unit
Maximum Internal current limit
VILIM
1.31
1.38
1.45
V
Leading Edge Blanking Duration for VILIM
tLEB
270
330
390
ns
Propagation delay from current detection to gate off−state
tILIM
−
100
150
ns
Maximum on−time (option B)
ton(MAX)
29
39
49
ms
Maximum on−time (option A)
ton(MAX2)
16
20
24
ms
Threshold for immediate fault protection activation (140% of VILIM)
CURRENT SENSE
VCS(stop)
1.91
1.99
2.07
V
Leading Edge Blanking Duration for VCS(stop)
tBCS
−
170
−
ns
Current source for CS to GND short detection
ICS(short)
400
500
600
mA
VCS(low)
20
60
100
mV
Drive Resistance
DRV Sink
DRV Source
RSNK
RSRC
−
−
13
30
−
−
Drive current capability
DRV Sink (Note GBD)
DRV Source (Note GBD)
ISNK
ISRC
−
−
500
300
−
−
Current sense threshold for CS to GND short detection
VCS rising
GATE DRIVE
W
mA
Rise Time (10 % to 90 %)
CDRV = 470 pF
tr
–
30
−
ns
Fall Time (90 % to 10 %)
CDRV = 470 pF
tf
–
20
−
ns
DRV Low Voltage
VCC = VCC(off)+0.2 V
CDRV = 470 pF,
RDRV=33 kW
VDRV(low)
8
–
−
V
DRV High Voltage
VCC = VCC(MAX)
CDRV = 470 pF,
RDRV=33 kW
VDRV(high)
10
12
14
V
Upper ZCD threshold voltage
VZCD rising
VZCD(rising)
−
90
150
mV
Lower ZCD threshold voltage
VZCD falling
VZCD(falling)
35
55
−
mV
VZCD(HYS)
15
−
−
mV
VZCD decreasing
tZCD(DEM)
−
−
150
ns
Blanking delay after on−time (ZCD blank option B)
VREFX > 0.35 V
tZCD(blank1)B
1.1
1.5
1.9
ms
Blanking Delay at light load (ZCD blank option B)
VREFX < 0.25 V
tZCD(blank2)B
0.6
0.8
1.0
ms
Blanking delay after on−time (ZCD blank option A)
VREFX > 0.35 V
tZCD(blank1)A
0.75
1.0
1.25
ms
Blanking Delay at light load (ZCD blank option A)
VREFX < 0.25 V
tZCD(blank2)A
0.45
0.6
0.75
ms
tTIMO
5
6.5
8
ms
ZERO VOLTAGE DETECTION CIRCUIT
ZCD hysteresis
Propagation Delay from valley detection to DRV high
Timeout after last DEMAG transition
Pulling−down resistor
VZCD = VZCD(falling)
RZCD(pd)
200
kW
CONSTANT CURRENT CONTROL
Reference Voltage at TJ = 25°C to 100°C
VREF
Reference Voltage TJ = −40°C to 125°C
10% reference Voltage (TJ = 25°C to 85°C)
10% reference Voltage (TJ = −40°C to 125°C)
Current sense lower threshold for detection of the leakage inductance reset time
VCS falling
Blanking time for leakage inductance reset detection
326
333
340
mV
VREF
323
333
343
mV
VREF10
23.45
33.50
43.55
mV
VREF10
21.77
33.50
45.23
mV
VCS(low)
20
50
100
mV
tCS(low)
−
120
−
ns
VREF(CV)
2.42
2.48
2.54
V
CONSTANT VOLTAGE SECTION
Internal voltage reference for constant voltage regulation
TJ = 25°C
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NCL30386
ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V, , VCS = 0 V)
For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V)
Description
Test Condition
Symbol
Min
Typ
Max
Unit
VREF(CV)
2.38
2.48
2.58
V
GEA
40
50
60
mS
CONSTANT VOLTAGE SECTION
Internal voltage reference for constant voltage regulation
TJ = −40°C to 125°C
CV Error amplifier Gain
Error amplifier current capability
VREFX=VREF
COMP pin lower clamp voltage
COMP pin higher clamp voltage
ZCD pin voltage below which the CV OTA is boosted
IEA
±60
mA
VCV(clampL)
0.6
V
VCV(clampH)
VREF(CV)* 80%
Vboost(CV)
Error amplifier current capability during boost phase
IEAboost
ZCD slow OVP threshold (Vref(CV)*115%)
VOVP1
Switching period during slow OVP
Tsw(OVP1)
ZCD voltage at which slow OVP is exit (Vref(CV)*105%)
VOVP1rst
ZCD fast OVP threshold (Vref(CV)*130%)
4.1
1.88
2
V
2.12
±140
2.69
2.87
V
mA
3.04
1.5
V
ms
2.625
V
VOVP2
3.29
3.43
3.57
V
LINE FEED FORWARD
VVS to ICS(offset) conversion ratio
KLFF
0.153
0.185
0.217
mA/V
Offset current maximum value
VHV > (450 V or 500 V)
Ioffset(MAX)
76
95
114
mA
Line feed−forward current
DRV high, VHV = 200 V
IFF
32
37
42
mA
Threshold for line range detection VHV increasing
VHV increases
VHL
252
264
276
V
Threshold for line range detection VHV decreasing
VHV decreases
VLL
241
253
265
V
tHL(blank)
15
25
35
ms
VALLEY LOCKOUT SECTION
Blanking time for line range detection
Valley thresholds (expressed as a percentage of VREF)
1st to 2nd valley transition at LL and 2nd to 3rd valley HL, VREF decr.
2nd to 1st valley transition at LL and 3rd to 2nd valley HL, VREF incr.
2nd to 3rd valley transition at LL and 3rd to 4th valley HL, VREF decr.
3rd to 2nd valley transition at LL and 4th to 3rd valley HL, VREF incr.
3rd to 4th valley transition at LL and 4th to 5th valley HL, VREF decr.
4th to 3th valley transition at LL and 5th to 4th valley HL, VREF incr.
4th to 5th valley transition at LL and 5th to 6th valley HL, VREF decr.
5th to 4th valley transition at LL and 6th to 5th valley HL, VREF incr.
VREF decreases
VREF increases
VREF decreases
VREF increases
VREF decreases
VREF increases
VREF decreases
VREF increases
VVLY1−2/2−3
VVLY2−1/3−2
VVLY2−3/3−4
VVLY3−2/4−3
VVLY3−4/4−5
VVLY4−3/5−4
VVLY4−5/5−6
VVLY5−4/6−5
80
90
65
75
50
60
35
45
%
VREF value at which the FF mode is activated
VREF decreases
VFFstart
25
%
VREF value at which the FF mode is removed
VREF increases
VFFstop
35
%
Added dead time
VREFX = 25%VREF
tFF1LL
1.4
2.0
2.6
ms
Added dead time
VREFX = 8% VREF
tFFchg
−
40
−
ms
FREQUENCY FOLDBACK
Dead−time clamp (Maximum dead−time option C)
VREFX < 1 mV
tFFend
1.4
−
ms
Dead−time clamp (Maximum dead−time option B)
VREFX < 3 mV
tFFend2
−
687
−
ms
Dead−time clamp (Maximum dead−time option A)
VREFX < 11.2 mV
tFFend3
−
250
−
ms
DIM pin voltage for zero output current (OFF voltage)
VADIM(EN)
0.475
0.5
0.525
V
ADIM pin voltage for 0.5% reference voltage
VADIM(MIN)
0.67
0.7
0.73
Minimum dimming level (dimming lower clamp option Y)
KDIM(MIN)
ADIM pin voltage for maximum output current (VREFX = 1 V)
VADIM100
DIMMING SECTION
0.5
−
3.0
V
%
3.1
V
Dimming range
VADIM(range)
2.3
V
Clamping voltage for DIM pin
VADIM(CLP)
6.8
V
Dimming pin pull−up current source
IADIM(pullup)
8
10
12
mA
Current Comparator threshold for PDIM
IPDIM rising
IPDIM(THR)
60
70
80
mA
Current Comparator threshold for PDIM
IPDIM falling
IPDIM(THD)
86
100
114
mA
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NCL30386
ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V, , VCS = 0 V)
For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V)
Description
Test Condition
Symbol
Min
Typ
Max
Unit
IPDIM(LIM)
510
600
690
mA
VPDIM
−
3
TSHDN
130
150
170
°C
Thermal Shutdown Hysteresis
TSHDN(HYS)
−
50
–
°C
Threshold voltage for output short circuit or aux. winding short
circuit detection
VZCD(short)
0.8
1.0
1.2
V
tOVLD
70
90
110
ms
trecovery
3
4
5
s
V
DIMMING SECTION
Cascode current limit for PDIM
PDIM pin voltage
V
FAULT PROTECTION
Thermal Shutdown
Device switching
(FSW around 65 kHz)
Short circuit detection Timer
VZCD < VZCD(short)
Auto−recovery Timer
BROWN−OUT AND LINE SENSING
Brown−Out ON level (IC start pulsing)
VHV increasing
VHVBO(on)
104
110
116
Brown−Out OFF level (IC stops pulsing)
VHV decreasing
VHVBO(off)
93
99
105
BO comparators delay
tBO(delay)
Brown−Out blanking time
30
tBO(blank)
15
V
ms
25
35
ms
HV pin voltage above which the sampling of ZCD is enabled
VHV decreasing
VsampEN
61
V
Sampling Enable comparator hysteresis
VHV increasing
VsampHYS
4
V
TYPICAL CHARACTERISTICS
18.30
8.90
18.25
8.88
VCC(off) (V)
VCC(on) (V)
18.20
18.15
18.10
8.84
8.82
8.80
18.05
18.00
−50
8.86
8.78
−25
0
25
50
75
100
125
8.76
−50
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 3. VCC(on) vs. Junction Temperature
Figure 4. VCC(off) vs. Junction Temperature
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125
NCL30386
28.0
1.45
27.5
1.43
1.41
27.0
VILIM (V)
VCC(OVP) (V)
TYPICAL CHARACTERISTICS
26.5
26.0
1.37
1.35
25.5
1.33
25.0
−50
−25
0
25
50
75
100
1.31
−50
125
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. VCC(OVP) vs. Junction Temperature
Figure 6. VILIM vs. Junction Temperature
100
2.07
90
2.05
80
2.03
70
2.01
VCS(stop) (V)
VCS(low)F (V)
1.39
60
50
1.99
1.97
40
1.95
30
1.93
20
−50
−25
0
25
50
75
100
1.91
−50
125
125
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 7. VCS(low)F vs. Junction Temperature
Figure 8. VCS(stop) vs. Junction Temperature
144
335.5
134
334.5
114
VREF (V)
tILIM (ns)
124
104
94
84
333.5
332.5
331.5
74
64
−50
−25
0
25
50
75
100
330.5
−50
125
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 9. tILIM vs. Junction Temperature
Figure 10. VREF vs. Junction Temperature
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125
NCL30386
TYPICAL CHARACTERISTICS
60
2.511
58
2.506
56
2.501
54
GEA (mS)
VREF(CV) (V)
2.496
2.491
2.486
52
50
48
2.481
46
2.476
44
2.471
42
2.466
−50
−25
0
25
50
75
100
40
−50
125
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 11. VREF(CV) vs. Junction Temperature
Figure 12. GEA vs. Junction Temperature
3.46
2.883
2.878
3.45
2.873
3.44
VOVP2 (V)
VOVP1 (V)
2.868
2.863
2.858
3.43
3.42
2.853
2.848
2.843
2.838
−50
125
3.41
−25
0
25
50
75
100
3.40
−50
125
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 13. VOVP1 vs. Junction Temperature
Figure 14. VOVP2 vs. Junction Temperature
0.190
125
37.8
37.6
0.188
37.4
KLFF (mA/V)
37.2
IFF (mA)
0.186
0.184
37.0
36.8
36.6
0.182
36.4
0.180
−50
36.0
−50
36.2
−25
0
25
50
75
100
125
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 15. KLFF vs. Junction Temperature
Figure 16. IFF vs. Junction Temperature
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125
NCL30386
TYPICAL CHARACTERISTICS
100.2
VHVbo(off) (V)
VHVBO(on) (V)
111.2
110.7
110.2
99.7
99.2
98.7
109.7
109.2
−50
−25
0
25
50
75
100
98.2
−50
125
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 17. VHVBO(on) vs. Junction Temperature
Figure 18. VHVbo(off) vs. Junction Temperature
75
0.504
74
73
IPDIM(THR) (mA)
VADIM(EN) (V)
0.502
0.500
0.498
72
71
70
69
68
67
0.496
66
0.494
−50
−25
0
25
50
75
100
65
−50
125
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 19. VADIM(EN) vs. Junction Temperature
Figure 20. IPDIM(THR) vs. Junction Temperature
105
104
621
616
102
IPDIM(LIM) (mA)
IPDIM(THD) (mA)
103
101
100
99
98
97
611
606
601
96
95
−50
−25
0
25
50
75
100
125
596
−50
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 21. IPDIM(THD) vs. Junction Temperature
Figure 22. IPDIM(LIM) vs. Junction Temperature
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10
NCL30386
APPLICATION INFORMATION
• Fast Over Voltage Protection: If the voltage of ZCD pin
The NCL30386 implements a current−mode architecture
operating in quasi−resonant mode. Thanks to proprietary
circuitry, the controller is able to accurately regulate the
secondary side current and voltage of the fly−back converter
without using any opto−coupler or measuring directly the
secondary side current or voltage. The controller provides
near unity power factor correction
• Quasi−Resonance Current−Mode Operation:
implementing quasi−resonance operation in peak
current−mode control, the NCL30386 optimizes the
efficiency by switching in the valley of the MOSFET
drain−source voltage. Thanks to an internal algorithm
control, the controller locks−out in a selected valley and
remains locked until the input voltage or the output
current set point significantly changes.
• Primary Side Constant Current Control: thanks to a
proprietary circuit, the controller is able to take into
account the effect of the leakage inductance of the
transformer and allows an accurate control of the
secondary side current regardless of the input voltage
and output load variation
• Primary Side Constant Voltage Regulation: By
monitoring the auxiliary winding voltage, it is possible
to regulate accurately the output voltage. The output
voltage regulation is typically within ±2%.
• Load Transient Compensation: Since PFC has low loop
bandwidth, abrupt changes in the load may cause
excessive over or under−shoot. The slow Over Voltage
Protection contains the output voltage when it tends to
become excessive. In addition, the NCL30386 speeds
up the constant voltage regulation loop when the output
voltage goes below 80% of its regulation level.
• Power Factor Correction: A proprietary concept allows
achieving high power factor correction and low THD
while keeping accurate constant current and constant
voltage control.
• Line Feed−forward: allows compensating the variation
of the output current caused by the propagation delay.
• VCC Over Voltage Protection: if the VCC pin voltage
exceeds an internal limit, the controller shuts down and
waits 4 seconds before restarting pulsing.
•
•
•
•
•
•
•
•
exceeds 130% of its regulation level, the controller
shuts dwon and waits 4 s before trying to restart.
Brown−Out: the controller includes a brown−out circuit
which safely stops the controller in case the input
voltage is too low. The device will automatically restart
if the line recovers.
Cycle−by−cycle peak current limit: when the current
sense voltage exceeds the internal threshold VILIM, the
MOSFET is turned off for the rest of the switching
cycle.
Winding Short−Circuit Protection: an additional
comparator senses the CS signal and stops the
controller if VCS reaches 1.5 x VILIM (after a reduced
LEB of tBCS). This additional comparator is enabled
only during the main LEB duration tLEB, for noise
immunity reason.
Output Under Voltage Protection: If a too low voltage is
applied on ZCD pin for 90−ms time interval, the
controllers assume that the output or the ZCD pin is
shorted to ground and shutdown. After waiting 4
seconds, the IC restarts switching.
Analog Dimming: the ADIM pin is dedicated to analog
dimming. The minimum dimming level is fixed 0.5%
of the maximum output current. If a voltage lower than
VADIM(EN) is applied on the pin, the controller is
disabled.
PWM dimming: the PDIM pin is dedicated to PWM
dimming. The controller measures the duty ratio of a
signal applied to the pin and reduces the output current
accordingly. The PWM dimming signal is transform
into an analog signal internally, and the LED current is
controlled in an analog way.
Thermal Shutdown: an internal circuitry disables the
gate drive when the junction temperature exceeds
150°C (typically). The circuit resumes operation once
the temperature drops below approximately 100°C.
Dynamic Self Supply option: the dynamic self−supply
keeps the controller alive in case of low dimming. If
VCC reaches VCC(off), the HV current source is turned
on to charge VCC capacitor until the voltage reaches
VCC(on2) without interrupting the DRV pulses.
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11
NCL30386
POWER FACTOR AND CONSTANT CURRENT
CONTROL
The NCL30386 embeds an analog/digital block to control
the power factor and regulate the output current by
monitoring the ZCD, CS and HV pin voltages (signals
VZCD, VHV_DIV, VCS). This circuit generates the current
setpoint VCTRL_DIV and compares it to the current sense
signal to turn the MOSFET off. The HV pin provides the
sinusoidal reference necessary for shaping the input current.
The obtained current reference is further modulated so that
when averaged over a half line period, it is equal to the
output current reference (VREFX). The modulation and
averaging process is made internally by a digital circuit. If
the HV pin properly conveys the sinusoidal shape, power
factor will be close to 1. Also, the Total Harmonic Distortion
(THD) will be low especially if the output voltage ripple is
small.
The output current will be well regulated, following the
equation below:
I OUT +
V REFX
2N spR sense
Rsense is the current sense resistor
VREFX is the output current reference: VREFX =
VREF if no dimming
The output current reference (VREFX) is VREF unless the
constant voltage mode is activated or ADIM pin voltage is
below VADIM(100) or a PWM signal with a duty−cycle below
95% is applied on PDIM.
♦
♦
CONSTANT VOLTAGE CONTROL
The auxiliary winding voltage is sampled internally
through the ZCD pin.
A precise internal voltage reference VREF(CV) sets the
voltage target for the CV loop.
The sampled voltage is applied to the negative input of the
CV OTA and compared to VREFCV.
A type 2 compensator is needed at the CV OTA output to
stabilize the loop. The COMP pin voltage modify the the
output current internal reference in order to regulate the
output voltage.
When VCOMP ≥ 4 V, VREFX = VREF.
When VCOMP < 0.6 V, VREFX = 0 V
(eq. 1)
Where:
♦ Nsp is the secondary to primary transformer turns
ratio: Nsp = NS / NP.
RZCDU
ZCD
VZCDsamp
ZCD & signal
sampling
Gm
COMP
.
Aux.
RZCDL
VREF(CV)
OTA
R1
C2
C1
Figure 23. Constant Voltage Feedback Circuit
STARTUP PHASE (HV STARTUP)
It is generally requested that the LED driver starts to emit
light in less than 1 s and possibly within 300 ms. It is
challenging since the start−up consists of the time to charge
the VCC capacitor and that necessary to charge the output
capacitor until sufficient current flows into the LED string.
This second phase can be particularly long in dimming cases
where the secondary current is a portion of the nominal one.
The NCL30386/88 features a high voltage startup circuit
that allows charging VCC capacitor very fast.
When the power supply is first connected to the mains
outlet, the internal current source is biased and charges up
the VCC capacitor. When the voltage on this VCC capacitor
reaches the VCC(on) level, the current source turns off. At this
time, the controller is only supplied by the VCC capacitor,
and the auxiliary supply should take over before VCC
collapses below VCC(off).
The HV startup circuitry is made of two startup current
levels, IHV(start1) and IHV(start1). This helps to protect the
controller against short−circuit between VCC and GND. At
power−up, as long as VCC is below VCC(TH), the source
delivers IHV(start1) (around 300 mA typical). Then, when
VCC reaches VCC(TH), the source smoothly transitions to
IHV(start2) and delivers its nominal value. As a result, in case
of short−circuit between VCC and GND occurring at high
line (Vin = 265 Vrms), the power dissipation will be 375 x
300u = 112 mW instead of 1.5 W if there was only one
startup current level.
To speed−up the output voltage rise, the following is
implemented:
• The digital OTA output is increased until VREF(PFC)
signal reaches VREFX. Again, this is to speed−up the
control signal rise to their steady state value.
• At the beginning of each operating phase of a VCC
cycle, the digital OTA output is set to 0. Actually, the
digital OTA output is set to 0 in the case of a cold
start−up or in the case of a start−up sequence following
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12
NCL30386
•
an operation interruption due to a fault. On the other
hand, if the VCC hiccups just because the system fails to
start−up in one VCC cycle (DSS option not activated),
the digital OTA output is not reset to ease the second
(or more) attempt.
If the load is shorted, the circuit will operate in hiccup
mode with VCC oscillating between VCC(off) and
VCC(on) until the output under voltage protection (UVP)
trips. UVP is triggered if the ZCD pin voltage does not
exceed 1 V within a 90 ms operation of time. This
indicates that the ZCD pin is shorted to ground or that
an excessive load prevents the output voltage from
rising.
threshold of (VCS(stop) = 140% *VILIM) monitors the CS pin
to detect a winding or an output diode short circuit. The
controller shuts down if it detects 4 consecutives pulses
during which the CS pin voltage exceeds VCS(stop).
The controller goes into auto−recovery mode.
PWM DIMMING
The NCL30386 has a dedicated pin for PWM dimming.
The controller directly measures the duty ratio of a PWM
signal applied to PDIM.
Two counters with a high frequency clock are used for this
purpose. A first counter measure the high state duration of
the PWM signal (ton_PDIM) and the second counter measures
its period (Tsw_PDIM). A divider computes (ton_PDIM /
Tsw_PDIM) and the result is directly the output current
setpoint (VREFX set point). A filter is added after the digital
divider to remove the ripple of the signal. A cascode
configuration on PDIM pin allows decreasing the fall time
of the signal.
Due to this circuit, the LED current is controlled in an
analog way, even if a PWM signal is used for dimming. This
allows having a good PF during dimming.
CYCLE−BY−CYCLE CURRENT LIMIT
When the current sense voltage exceeds the internal
threshold VILIM, the MOSFET is turned off for the rest of the
switching cycle.
WINDING AND OUTPUT DIODE SHORT−CIRCUIT
PROTECTION
In parallel to the cycle−by−cycle sensing of the CS pin,
another comparator with a reduced LEB (tBCS ) and a
VDIM_sec
Ton_P
IPDIM
IPDIM(THD)
IPDIM(THR)
VPDIM_int
Tsw_P
Figure 24. PDIM Internal Waveforms
Practically, the controller extracts the duty−cycle by
measuring the current inside PDIM pin which is directly the
opto coupler collector current.
If PDIM pin is left open, the controller delivers 100% of
Iout. If the pin is pulled down for longer than 25 ms, the
controller is disabled.
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13
NCL30386
ANALOG DIMMING
The pin ADIM pin allows dimming the LED light using
an analog signal as the control input.
The DIM pin voltage is sampled by an analog to digital
converter and sets the output current value accordingly.
If the power supply designer applies an analog signal
varying from VDIM(EN) to VDIM100 to the DIM pin, the
output current will increase or decrease proportionally to the
voltage applied. For VDIM = VDIM100, the power supply
delivers the maximum output current (VREFX = VREF).
If a voltage lower than VADIM(MIN) is applied to ADIM
pin, the output current is clamped to 0.5% of the maximum
output current depending on the controller option
If a voltage lower than VADIM(EN) is applied to the DIM
pin, the DRV pulses are disabled.
The DIM pin is pulled up internally by a small current
source or resistor. Thus, if the pin is left open, the controller
is able to start.
Note:
• Interaction between ADIM and PDIM: if ADIM and
PDIM are both used at the same time, the resulting
dimming set point if a multiplication of VADIM and the
duty−ratio of PDIM signal.
• If the dimming curve option S is selected, a square
relationship is implemented between the dimming
signal and the output current setpoint.
VREF
100% VREF
L option
S option
0.5% VREF
VADIM (EN)
VADIM 100
VADIM (MIN)
Figure 25. ADIM Pin Dimming Curves
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14
VADIM
NCL30386
VALLEY LOCKOUT
Quasi−Square wave resonant systems have a wide
switching frequency excursion. The switching frequency
increases when the output load decreases or when the input
voltage increases. The switching frequency of such systems
must be limited.
The NCL30386 changes valley as VREFX decreases and as
the input voltage increases and as the output current setpoint
is varied during dimming. This limits the frequency
excursion.
By default, when the output current is not dimmed, the
controller operates in the first valley at low line and in the
second valley at high line.
HV pin voltage for valley change
value at which the
controller changes valley
(Iout decreasing)
REFX
0
100%
−−LL −− 230 V
−−HL −− 400 V
1st
2nd
2nd
3rd
rd
th
80%
100%
85%
70%
3
50%
35%
4
4th
5th
5th
6th
25%
55%
40%
30%
FF mode
0%
0
FF mode
−−LL −− 240 V
−−HL −− 400 V
HV pin voltage for valley change
Figure 26. TABLE II: Valley Selection
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15
0%
Iout increase
65%
Iout decreases
VREFX value at which the
controller changes valley
(Iout increasing)
NCL30386
ZERO CROSSING DETECTION BLOCK
The ZCD pin allows detecting when the drain−source
voltage of the power MOSFET reaches a valley.
A valley is detected when the ZCD pin voltage crosses
below the 55 mV internal threshold.
At startup or in case of extremely damped free
oscillations, the ZCD comparator may not be able to detect
the valleys. To avoid such a situation, the NCL30386 a
Time−Out circuit that generates pulses if the voltage on ZCD
pin stays below the 55 mV threshold for 6.5 ms.
The Time−out also acts as a substitute clock for the valley
detection and simulates a missing valley in case of too
damped free oscillations.
At startup, the output voltage reflected on the auxiliary
winding is low. Because of the ZCD resistor bridge setting
the constant voltage regulation target, the voltage on the
ZCD pin is very low and the ZCD comparator might be
unable to detect the valleys. In this condition, setting the
DRV Latch with the 6.5−ms time−out leads to a continuous
conduction mode operation (CCM) at the beginning of the
soft−start. This CCM operation only last a few cycles until
the voltage on ZCD pin becomes high enough and trips the
ZCD comparator.
V ZCD
3
4
high
V ZCD(THD)
The 3rd valley is
validated
14
2 nd , 3 rd
low
12
The 2nd valley is detected
By the ZCD comparator
The 3rd valley is not detected by the
ZCD comp
high
low
15
ZCD comp
high
low
16
Time−out circuit adds a pulse to
account for the missing 3rd valley
TimeOut
high
low
17
Clk
Figure 27. ZCD Time−out Chronograms
ZCD PIN OVER VOLTAGE PROTECTION.
Because of the power factor correction, it is necessary to
set the crossover frequency of the CV loop very low (target
10 Hz, depending on power stage phase shift). Because the
loop is slow, the output voltage can reach high value during
startup or during an output load step. It is necessary to limit
the output voltage excursion. For this, the NCL30388
features a slow over voltage protection (slow OVP) and a
fast over voltage protection (fast OVP) on ZCD pin.
If the ZCD pin or the auxiliary winding happen to be
shorted the time−out function would normally make the
controller keep switching and hence lead to improper
regulation of the LED current.
The Under Voltage Protection (UVP) is implemented to
avoid these scenarios: a secondary timer starts counting
when the ZCD voltage is below the VZCD(short) threshold. If
this timer reaches 90 ms, the controller detects a fault and
enters the auto−recovery fault mode.
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16
NCL30386
Slow OVP
Fast OVP
If ZCD voltage exceed VZCD(OVP1) for 4 consecutive
switching cycles, the controller stops switching during
1.4 ms. After 1.4 ms, the controller initiates a new DRV
pulse to refresh ZCD sampling voltage. If VZCD is still too
high (VZCD > 110%VREF(CV)), the controller continues to
switch with a 1.4 ms period. The controller resumes its
normal operation when VZCD < 110%VREF(CV).
If ZCD voltage exceeds VZCD(OVP2) (130% of VREF(CV))
for 4 consecutive switching cycles (slow OVP not triggered)
or for 2 switching cycles if the slow OVP has already been
triggered, the controller detects a fault and starts the
auto−recovery fault mode (cf: Protections Section)
LINE FEEDFORWARD
HV
vDD
vVS
CS
I CS(offset)
KLFF
RLFF
R sense
Q_drv
+
25 ms
Blanking
−
BO_NOK
1 V / 0.9 V
Figure 28. Line Feed−Forward and Brown−out Schematic
PROTECTIONS
The circuit incorporates a large variety of protections to
make the LED driver very rugged.
Among them, we can list:
• Fault of the GND connection
If the GND pin is properly connected, the supply
current drawn from the positive terminal of the VCC
capacitor, flows out of the GND pin to return to the
negative terminal of the VCC capacitor. If the GND pin
is not connected, the circuit ESD diodes offer another
return path. The accidental non connection of the GND
pin can hence be detected by detecting that one of this
ESD diode is conducting. Practically, the ESD diode of
CS pin is monitored. If such a fault is detected for
200 ms, the circuit stops generating DRV pin.
• Output short circuit situation (Output Under Voltage
Protection)
Overload is detected by monitoring the ZCD pin
voltage: if it remains below VZCD(short) for 90 ms, an
output short circuit is detected and the circuit stops
generating pulses for 4 s. When this 4 s delay has
elapsed, the circuit attempts to restart.
• ZCD pin incorrect connection:
The line voltage is sensed by the HV pin and converted
into a current. By adding an external resistor in series
between the sense resistor and the CS pin, a voltage offset
proportional to the line voltage is added to the CS signal. The
offset is applied only during the MOSFET on−time in order
to not influence the detection of the leakage inductance
reset.
The offset is always applied even at light load in order to
improve the current regulation at low output load.
BROWN−OUT
In order to protect the supply against a very low input
voltage, the NCL30386 features a brown−out circuit with a
fixed ON/OFF threshold. The controller is allowed to start
if a voltage higher than 100 V is applied to the HV pin and
shuts−down if the HV pin voltage decreases and stays below
9 0 V for 25 ms typical. Exiting a brown−out condition
overrides the hiccup on VCC (VCC does not wait to reach
VCC(off)) and the IC immediately goes into startup mode.
www.onsemi.com
17
NCL30386
• Die Over Temperature (TSD)
If the ZCD pin grounded, the circuit will detect an
output short circuit situation when 90−ms delay has
elapsed.
♦ A 200 kW resistor pulls down the ZCD pin so that
the output short circuit detection trips if the ZCD pin
is not connected (floating).
Winding or Output Diode Short Circuit protection
The circuit detects this failure when 4 consecutive DRV
pulses occur within which the CS pin voltage exceeds
(VCS(stop)=140% *VILIM). In this case, the controller
enters auto−recovery mode (4−s operation interruption
between active bursts).
VCC Over Voltage Protection
The circuit stops generating pulses if the VCC exceeds
VCC(OVP) and enters auto−recovery mode. This feature
protects the circuit if output LEDs happen to be
disconnected.
ZCD fast OVP
If ZCD voltage exceeds VZCD(OVP2) for 4 consecutive
switching cycles (slow OVP not triggered) or for 2
switching cycles if the slow OVP has already been
triggered, the controller detects a fault and enters
auto−recovery mode (4 s operation interruption
between active bursts).
♦
•
•
•
The circuit stops operating if the junction temperature
(TJ) exceeds 150°C typically. The controller remains
off until TJ goes below nearly 100°C.
• Brown−Out Protection (BO)
The circuit prevents operation when the line voltage is
too low to avoid an excessive stress of the LED driver.
Operation resumes as soon as the line voltage is high
enough and VCC is higher than VCC(on).
• CS pin short to ground
The CS pin is checked at start−up (cold start−up or after
a brown−out event). A current source (Ics(short)) is
applied to the pin and no DRV pulse is generated until
the CS pin exceeds Vcs(low). Ics(short) and Vcs(low) are
500 mA and 60 mV typically (VCS rising). The typical
minimum impedance to be placed on the CS pin for
operation is then 120 W. In practice, it is recommended
to place more than 250 W to take into account possible
parametric deviations
Also, along the circuit operation, the CS pin could happen
to be grounded. If it is grounded, the MOSFET conduction
time is limited by the maximum on−time. If such an event
occurs, a new pin impedance test is made.
ORDERING TABLE OPTION
DSS
Maximum dead−time
Max. On−
time
VREF
ZCD blanking
Dimming Curve
Line Range
Detector
Dimming
Clamp
Y
N
A
B
C
U
V
A
B
A
B
L
S
Y
N
Y
N
OPN #
On
Off
250 ms
687 ms
1.4 ms
250 mV
333 mV
20 ms
33 ms
1 ms
1.5 ms
Linear
Square
On
Off
On
Off
NCL30386A1
x
x
x
x
x
x
x
x
NCL30386A2
x
x
x
x
x
x
NCL30386B1
x
x
x
x
x
NCL30386B2
x
x
x
x
x
x
x
x
x
x
x
x
x
ORDERING INFORMATION2
Marking
Package type
Shipping†
NCL30386A1DR2G
L30386A1
SOIC9 COMP EPX 0.5P PBF
2500 / Tape & Reel
NCL30386A2DR2G
L30386A2
SOIC9 COMP EPX 0.5P PBF
2500 / Tape & Reel
NCL30386B1DR2G
L30386B1
SOIC9 COMP EPX 0.5P PBF
2500 / Tape & Reel
NCL30386B2DR2G
L30386B2
SOIC9 COMP EPX 0.5P PBF
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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18
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−9 NB
CASE 751BP
ISSUE A
9
1
SCALE 1:1
DATE 21 NOV 2011
2X
0.10 C A-B
D
D
A
0.20 C
2X
4 TIPS
F
0.10 C A-B
10
6
H
E
1
5
0.20 C
9X
B
5 TIPS
L2
b
0.25
A3
L
DETAIL A
M
C
SEATING
PLANE
C A-B D
TOP VIEW
9X
h
0.10 C
0.10 C
X 45 _
M
A
e
A1
C
SIDE VIEW
SEATING
PLANE
DETAIL A
END VIEW
1
6.50
9X
1.18
1
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON52301E
SOIC−9 NB
MILLIMETERS
MIN
MAX
1.25
1.75
0.10
0.25
0.17
0.25
0.31
0.51
4.80
5.00
3.80
4.00
1.00 BSC
5.80
6.20
0.37 REF
0.40
1.27
0.25 BSC
0_
8_
9
1.00
PITCH
0.58
DIM
A
A1
A3
b
D
E
e
H
h
L
L2
M
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
9X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.10mm TOTAL IN EXCESS OF ’b’
AT MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15mm
PER SIDE. DIMENSIONS D AND E ARE DETERMINED AT DATUM F.
5. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM F.
6. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
XXXXX
ALYWX
G
XXXXX = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking. Pb−Free indicator, “G”, may
or not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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