NCL30488A2DR2G

Power Factor Corrected LED Driver with Primary Side CC/CV NCL30488 The NCL30488 is a power factor corrected flyback controller targeting isolated constant current LED drivers. The controller operates in a quasi−resonant mode to provide high efficiency. Thanks to a novel control method, the device is able to tightly regulate a constant LED current from the primary side. This removes the need for secondary side feedback circuitry, its biasing and for an optocoupler. The device is highly integrated with a minimum number of external components. A robust suite of safety protection is built in to simplify the design. www.onsemi.com SOIC−7 CASE 751U MARKING DIAGRAM Features • • • • • • • • • • • • 8 High Voltage Startup Quasi−resonant Peak Current−mode Control Operation Primary Side Feedback CC / CV Accurate Control Vin up to 320 V rms Tight LED Constant Current Regulation of ±2% Typical Digital Power Factor Correction Analog and Digital Dimming Cycle by Cycle Peak Current Limit Wide Operating VCC Range −40 to + 125°C Robust Protection Features ♦ Brown−Out ♦ OVP on VCC ♦ Constant Voltage / LED Open Circuit Protection ♦ Winding Short Circuit Protection ♦ Secondary Diode Short Protection ♦ Output Short Circuit Protection ♦ Thermal Shutdown ♦ Line over Voltage Protection This is a Pb−Free Device L30488XX ALYWX G 1 L30488 XX A L YW G = Specific Device Code = Version = Assembly Location = Wafer Lot = Assembly Start Week = Pb−Free Package PIN CONNECTIONS HV COMP 1 ZCD 2 CS 3 6 VCC GND 4 5 DRV 8 Typical Applications • Integral LED Bulbs • LED Power Driver Supplies • LED Light Engines © Semiconductor Components Industries, LLC, 2020 May, 2021 − Rev. 2 ORDERING INFORMATION See detailed ordering and shipping information on page 21 of this data sheet. 1 Publication Order Number: NCL30488/D NCL30488 . . . NCL30488 1 7 2 3 6 4 5 Figure 1. Typical Application Schematic for NCL30488 PIN FUNCTION DESCRIPTION NCL30488 Pin N5 Pin Name Function Pin Description 1 COMP OTA output for CV loop This pin receives a compensation network (capacitors and resistors) to stabilize the CV loop 2 ZCD Zero crossing Detection Vaux sensing This pin connects to the auxiliary winding and is used to detect the core reset event. This pin also senses the auxiliary winding voltage for accurate output voltage control. 3 CS Current sense 4 GND − 5 DRV Driver output 6 VCC Supplies the controller 7 NC creepage 8 HV High Voltage sensing This pin monitors the primary peak current. The controller ground The driver’s output to an external MOSFET This pin is connected to an external auxiliary voltage. This pin connects after the diode bridge to provide the startup current and internal high voltage sensing function. www.onsemi.com 2 NCL30488 INTERNAL CIRCUIT ARCHITECTURE STOP VCV Constant Voltage Control Thermal Shutdown Slow_OVP CS_short Fast_OVP Leading Edge Blanking Q_drv VHVdiv STOP VCC Management OFF VCC OVP VCC_OVP HV Startup HV BO_NOK Zero crossing detection Logic (ZCD blanking, Time−Out, …) Line feed −forward UVLO VREFX VVS Slow_OVP Valley Selection Aux . Winding Short Circuit Prot. CS Fault Management Fast_OVP Standby ZCD VCC L_OVP Aux_SCP COMP VHVdiv Standby Power factor and Constant−current control Max. Peak Current Limit Winding / Output diode SCP CS Short Protection L_OVP VHVdiv Frequency foldback Aux_SCP Brown−out Line OVP S Q R Q Q_drv VREFX CS_reset Ipk_max STOP WOD_SCP CS_short GND Figure 2. Internal Circuit Architecture NCL30488 www.onsemi.com 3 Maximum on−time Driver and Clamp DRV NCL30488 MAXIMUM RATINGS TABLE Symbol VCC(MAX) ICC(MAX) Rating Maximum Power Supply voltage, VCC pin, continuous voltage Maximum current for VCC pin VDRV(MAX) Maximum driver pin voltage, DRV pin, continuous voltage IDRV(MAX) Maximum current for DRV pin VHV(MAX) IHV(MAX) Value Unit −0.3 to 30 Internally limited V mA −0.3, VDRV (Note 1) −300, +500 V mA −0.3, +700 ±20 V mA −0.3, 5.5 (Note 2) −2, +5 V mA Maximum voltage on HV pin Maximum current for HV pin (dc current self−limited if operated within the allowed range) VMAX IMAX Maximum voltage on low power pins (except pins DRV and VCC) Current range for low power pins (except pins DRV and VCC) RθJ−A Thermal Resistance Junction−to−Air 200 °C/W Maximum Junction Temperature 150 °C Operating Temperature Range −40 to +125 °C Storage Temperature Range −60 to +150 °C TJ(MAX) ESD Capability, HBM model except HV pin (Note 3) ESD Capability, HBM model HV pin ESD Capability, CDM model (Note 3) 4 kV 1.5 kV 1 kV Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. VDRV is the DRV clamp voltage VDRV(high) when VCC is higher than VDRV(high). VDRV is VCC otherwise. 2. This level is low enough to guarantee not to exceed the internal ESD diode and 5.5 V ZENER diode. More positive and negative voltages can be applied if the pin current stays within the −2 mA / 5 mA range. 3. This device series contains ESD protection and exceeds the following tests: Human Body Model 4000 V per Mil−Std−883, Method 3015. Charged Device Model 1000 V per JEDEC Standard JESD22−C101D. 4. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V, VCS = 0 V) For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V) Parameter Test Condition Symbol Min Typ Max Unit HIGH VOLTAGE SECTION High voltage current source VCC = VCC(on) – 200 mV IHV(start2) 3.9 5.1 6.2 mA High voltage current source VCC = 0 V IHV(start1) − 300 − mA VCC(TH) − 0.8 − V − 15 − V VCC level for IHV(start1) to IHV(start2) transition Minimum startup voltage VCC = 0 V VHV(MIN) HV source leakage current VHV = 450 V IHV(leak) − 4.5 10 mA VHV(OL) 320 − − V rms VCC(on) VCC(off) VCC(HYS) VCC(reset) 16 9.3 7.6 4 18 10.2 − 5 20 10.7 − 6 Over Voltage Protection VCC OVP threshold VCC(OVP) 25 26.5 28 V VCC(off) noise filter (Note 5) VCC(reset) noise filter (Note 5) tVCC(off) tVCC(reset) − − 5 20 − − ms ICC1 ICC2 ICC3 ICC4 1.2 – − − 1.35 3.0 3.5 1.7 1.6 3.5 4.0 1.88 Maximum input voltage (rms) for correct operation of the PFC loop SUPPLY SECTION Supply Voltage Startup Threshold Minimum Operating Voltage Hysteresis VCC(on) – VCC(off) Internal logic reset Supply Current Device Disabled/Fault Device Enabled/No output load on pin 5 Device Switching (Fsw = 65 kHz) Device switching (Fsw = 700 Hz) VCC increasing VCC decreasing VCC decreasing VCC > VCC(off) Fsw = 65 kHz CDRV = 470 pF, Fsw = 65 kHz VCOMP v 0.9 V www.onsemi.com 4 V mA NCL30488 ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V, VCS = 0 V) For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V) (continued) Parameter Test Condition Symbol Min Typ Max Unit Maximum Internal current limit VILIM 1.33 1.40 1.47 V Leading Edge Blanking Duration for VILIM tLEB 283 345 407 ns Propagation delay from current detection to gate off−state tILIM − 100 150 ns Maximum on−time (option 1) ton(MAX) 29 39 49 ms Maximum on−time (option 2) ton(MAX) 16 20 24 ms Threshold for immediate fault protection activation (140% of VILIM) VCS(stop) 1.9 2.0 2.1 V CURRENT SENSE Leading Edge Blanking Duration for VCS(stop) tBCS − 170 − ns Current source for CS to GND short detection ICS(short) 400 500 600 mA VCS(low) 20 60 90 mV Drive Resistance DRV Sink DRV Source RSNK RSRC − − 13 30 − − Drive current capability DRV Sink (Note GBD) DRV Source (Note GBD) ISNK ISRC − − 500 300 − − Current sense threshold for CS to GND short detection VCS rising GATE DRIVE W mA Rise Time (10% to 90%) CDRV = 470 pF tr – 30 − ns Fall Time (90 %to 10%) CDRV = 470 pF tf – 20 − ns DRV Low Voltage VCC = VCC(off)+0.2 V CDRV = 470 pF, RDRV = 33 kW VDRV(low) 8 – − V DRV High Voltage VCC = VCC(MAX) CDRV = 470 pF, RDRV = 33 kW VDRV(high) 10 12 14 V Upper ZCD threshold voltage VZCD rising VZCD(rising) − 90 150 mV Lower ZCD threshold voltage VZCD falling VZCD(falling) 35 55 − mV Threshold to force VREFX maximum during startup VZCD falling VZCD(start) − 0.7 − V ZERO VOLTAGE DETECTION CIRCUIT ZCD hysteresis VZCD(HYS) 15 − − mV Propagation Delay from valley detection to DRV high (no tLEB4) VZCD decreasing tZCD(DEM) − − 150 ns Additional delay from valley lockout output to DRV latch set (programmable option) VZCD decreasing TLEB4 125 250 375 ns tPAR − 20 − ns Equivalent time constant for ZCD input (GBD) Blanking delay after on−time (option 1) VREFX > 0.35 V tZCD(blank1) 1.1 1.5 1.9 ms Blanking delay after on−time (option 2) VREFX > 0.35 V tZCD(blank1) 0.75 1.0 1.25 ms Blanking Delay at light load (option 1) VREFX < 0.25 V tZCD(blank2) 0.6 0.8 1.0 ms Blanking Delay at light load (option 2) VREFX < 0.25 V tZCD(blank2) 0.45 0.6 0.75 ms tTIMO 5 6.5 8 ms RZCD(pd) − 200 − kW VREF/3 327.9 334.2 341.2 mV Timeout after last DEMAG transition Pulling−down resistor VZCD = VZCD(falling) CONSTANT CURRENT CONTROL Reference Voltage Tj = 25°C − 85°C Reference Voltage Tj = −40°C to 125°C VREF/3 324 334.2 346 mV Current sense lower threshold for detection of the leakage inductance reset time VCS falling VCS(low) 20 50 100 mV tCS(low) − 120 − ns Blanking time for leakage inductance reset detection www.onsemi.com 5 NCL30488 ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V, VCS = 0 V) For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V) (continued) Parameter Test Condition Symbol Min Typ Max Unit POWER FACTOR CORRECTION Clamping value for VREF(PFC) TJ = 0°C to 125°C VREF(PFC)CLP 2.06 2.2 2.34 V Line range detector for PFC loop VHV increases VHL(PFC) − 240 − Vdc Line range detector for PFC loop VHV decreases VLL(PFC) − 230 − Vdc VREF(CV) 3.41 3.52 3.63 V GEA 40 50 60 mS CONSTANT VOLTAGE SECTION Internal voltage reference for constant voltage regulation CV Error amplifier Gain Error amplifier current capability VREFX = VREF (no dimming) COMP pin lower clamp voltage IEA − ±60 − mA VCV(clampL) − 0.6 − V COMP pin higher clamp voltage TJ = 0°C to 125°C VCV(clampH) 4.05 4.12 4.25 V COMP pin higher clamp voltage TJ = −40°C to 125°C VCV(clampH) 4.01 4.12 4.25 V KCOMP − 4 − 2.975 3.154 Internal divider VCOMP to VREFX Internal ZCD voltage below which the CV OTA is boosted VREF(CV) * 85% Vboost(CV) 2.796 Threshold for releasing the CV boost VREF(CV) * 90% Vboost(CV)RST 2.96 3.15 3.34 V IEAboost − ±140 − mA VOVP1 3.783 4.025 4.267 V Error amplifier current capability during boost phase ZCD OVP 1st level (slow OVP) option 1 VREF(CV) * 115% ZCD voltage at which slow OVP is exit (option 1) VREF(CV) * 105% Switching period during slow OVP ZCD fast OVP option 1 Vref(CV) * 125% + 150 mV Number of switching cycles before fast OVP confirmation Duration for disabling DRV pulses during ZCD fast OVP COMP pin internal pullup resistor (SSR option) V VOVP1rst − 3.675 − V Tsw(OVP1) − 1.5 − ms V VOVP2 4.253 4.525 4.797 TOVP2_CNT − 4 − Trecovery − 4 − s Rpullup − 15 − kW LINE FEED FORWARD VHV to ICS(offset) conversion ratio KLFF 0.189 0.21 0.231 mA/V Offset current maximum value VHV > (450 V or 500 V) Ioffset(MAX) 76 95 114 mA Line feed−forward current DRV high, VHV = 200 V IFF 35 40 45 mA Threshold for line range detection VHV increasing (1st to 2nd valley transition for VREFX > 80% VREF) (prog. option: 1st to 3rd valley transition) VHV increases VHL 228 240 252 V Threshold for line range detection VHV decreasing (2nd to 1st valley transition for VREFX > 80% VREF) (prog. option: 3rd to 1st valley transition) VHV decreases VLL 218 230 242 V tHL(blank) 15 25 35 ms VALLEY LOCKOUT SECTION Blanking time for line range detection www.onsemi.com 6 NCL30488 ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V, VCS = 0 V) For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V) (continued) Parameter Test Condition Symbol Min Typ Max Unit VREF decreases VVLY1−2/2−3 − 0.80 − VREF increases VVLY2−1/3−2 − 0.90 − VREF decreases VVLY2−3/3−4 − 0.65 − VREF increases VVLY3−2/4−3 − 0.75 − VREF decreases VVLY3−4/4−5 − 0.50 − VREF increases VVLY4−3/5−4 − 0.60 − VREF decreases VVLY4−5/5−6 − 0.35 − VREF increases VVLY5−4/6−5 − 0.45 − VREF value at which the FF mode is activated VREF decreases VFFstart − 0.25 − V VREF value at which the FF mode is removed VREF increases VFFstop − 0.35 − V Added dead time VREFX = 0.25 V tFF1LL 0.8 1.0 1.2 ms Added dead time VREFX = 0.08 V tFFchg − 40 − ms Dead−time clamp ( option 1) VREFX < 3 mV tFFend1 − 675 − ms Dead−time clamp ( option 2) VREFX < 11.2 mV tFFend2 − 250 − ms Minimum added dead−time in standby VREFX = 0 tDT(min)SBY − 650 − ms Maximum added dead−time in standby (option 2) VREFX = 0, VCOMP < 0.7 V tDT(max)SBY2 − 1.8 − ms TSHDN 130 150 170 °C VALLEY LOCKOUT SECTION Valley thresholds 1st to 2nd valley transition at LL and 2nd to 3rd valley HL, VREF decr. (prog. option: 3rd to 4th valley HL) 2nd to 1st valley transition at LL and 3rd to 2nd valley HL, VREF incr. (prog. option: 4th to 3rd valley HL) 2nd to 3rd valley transition at LL and 3rd to 4th valley HL, VREF decr. (prog. option: 4th to 5th valley HL) 3rd to 2nd valley transition at LL and 4th to 3rd valley HL, VREF incr. (prog. option: 5th to 4th valley HL) 3rd to 4th valley transition at LL and 4th to 5th valley HL, VREF decr. (prog. option: 5th to 6th valley HL) 4th to 3th valley transition at LL and 5th to 4th valley HL, VREF incr. (prog. option: 6th to 5th valley HL) 4th to 5th valley transition at LL and 5th to 6th valley HL, VREF decr. (prog. option: 6th to 7th valley HL) 5th to 4th valley transition at LL and 6th to 5th valley HL, VREF incr. (prog. option: 7th to 6th valley HL) V FREQUENCY FOLDBACK FAULT PROTECTION Thermal Shutdown (Note 5) Device switching (FSW around 65 kHz) Thermal Shutdown Hysteresis TSHDN(HYS) − 20 – °C Threshold voltage for output short circuit or aux. winding short circuit detection VZCD(short) 0.6 0.65 0.7 V tOVLD 70 90 110 ms Short circuit detection Timer VZCD < VZCD(short) Auto−recovery Timer trecovery 3 4 5 s Line OVP threshold VHV increasing VHV(OVP) 457 469 485 Vdc HV pin voltage at which Line OVP is reset VHV decreasing VHV(OVP)RST 430 443 465 Vdc TLOVP(blank) 15 25 35 ms Blanking time for line OVP reset BROWN−OUT AND LINE SENSING Brown−Out ON level (IC start pulsing) VHV increasing VHVBO(on) 101.5 108 114.5 Vdc Brown−Out ON level (IC start pulsing) option 2 VHV increasing VHVBO(on)2 129.7 138 146.3 Vdc Brown−Out OFF level (IC stops pulsing) VHV decreasing VHVBO(off) 92 98 104 Vdc Brown−Out OFF level (IC stops pulsing) option 2 VHV decreasing VHVBO(off)2 121 129 137 Vdc HV pin voltage above which the sampling of ZCD is enabled low line VHV decreasing, low line VsampENLL − 55 − V HV pin voltage above which the sampling of ZCD is enabled highline VHV decreasing, highline VsampENHL − 105 − V ZCD sampling enable comparator hysteresis VHV increasing VsampHYS − 5 − V BO comparators delay tBO(delay) − 30 − ms Brown−Out blanking time tBO(blank) 15 25 35 ms Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 5. Guaranteed by design. www.onsemi.com 7 NCL30488 TYPICAL CHARACTERISTICS 5,4 309 5,3 304 5,1 IHV(start1) (mA) IHV(start2) (mA) 5,2 5 4,9 4,8 4,7 299 294 289 4,6 4,5 284 −50 −25 0 25 50 75 100 −50 125 −25 0 TEMPERATURE (°C) 25 50 75 100 125 100 125 100 125 TEMPERATURE (°C) Figure 3. IHV(start2) vs. Temperature Figure 4. IHV(start1) vs. Temperature 361 18,34 357 VCC(on) (V) VHV(OL) (V rms) 359 355 18,29 18,24 353 18,19 351 349 −50 −25 0 25 50 75 100 18,14 125 −50 −25 0 TEMPERATURE (°C) 25 50 75 TEMPERATURE (°C) Figure 5. VHV(OL) vs. Temperature Figure 6. VCC(on) vs. Temperature 10,25 26,96 10,23 26,91 VCC(OVP) (V) VCC(off) (V) 10,21 10,19 10,17 26,86 26,81 10,15 26,76 10,13 26,71 26,66 10,11 −50 −25 0 25 50 75 100 −50 125 TEMPERATURE (°C) −25 0 25 50 75 TEMPERATURE (°C) Figure 7. VCC(off) vs. Temperature Figure 8. VCC(OVP) vs. Temperature www.onsemi.com 8 NCL30488 TYPICAL CHARACTERISTICS (continued) 1,7 1,41 1,69 1,39 ICC4 (mA) ICC1 (mA) 1,68 1,37 1,35 1,33 1,67 1,66 1,65 1,64 1,31 1,63 1,29 1,62 −50 −25 0 25 50 75 100 −50 125 −25 0 TEMPERATURE (°C) Figure 9. ICC1 vs. Temperature 54 1.402 53,5 VCS(low)F (mV) VILIM (V) 1.400 1.398 1.396 1.394 1.392 100 125 51,5 50,5 50 125 52 1.388 25 100 52,5 51 0 75 53 1.390 −25 50 Figure 10. ICC4 vs. Temperature 1.404 1.386 −50 25 TEMPERATURE (°C) 75 100 50 125 −50 −25 0 TEMPERATURE (°C) 25 50 75 TEMPERATURE (°C) Figure 11. VILIM vs. Temperature Figure 12. VCS(low)F vs. Temperature 2,06 20,24 20,19 2,02 ton(MAX)2 (ms) VCS(stop) (V) 2,04 2 1,98 20,14 20,09 20,04 19,99 19,94 1,96 19,89 19,84 1,94 −50 −25 0 25 50 75 100 −50 125 TEMPERATURE (°C) −25 0 25 50 75 100 TEMPERATURE (°C) Figure 13. VCS(stop) vs. Temperature Figure 14. ton(MAX)2 vs. Temperature www.onsemi.com 9 125 NCL30488 TYPICAL CHARACTERISTICS (continued) 359 180 179 354 tBCS (ns) tLEB (ns) 178 349 344 177 176 175 174 339 173 334 172 −50 −25 0 25 50 75 100 −50 125 −25 0 TEMPERATURE (°C) 25 50 75 100 125 100 125 100 125 TEMPERATURE (°C) Figure 15. tLEB vs. Temperature Figure 16. tBCS vs. Temperature 120 10,5 110 9,5 100 RSNK (W) tILIM (ns) 8,5 90 80 70 7,5 6,5 5,5 60 4,5 50 −50 −25 0 25 50 75 100 3,5 125 −50 −25 0 TEMPERATURE (°C) 25 50 75 TEMPERATURE (°C) Figure 17. tILIM vs. Temperature Figure 18. RSNK vs. Temperature 34 15,5 32 30 tr (ns) RSRC (W) 13,5 11,5 28 26 9,5 24 7,5 22 20 5,5 −50 −25 0 25 50 75 100 −50 125 TEMPERATURE (°C) −25 0 25 50 75 TEMPERATURE (°C) Figure 19. RSRC vs. Temperature Figure 20. tr vs. Temperature www.onsemi.com 10 NCL30488 TYPICAL CHARACTERISTICS (continued) 21,5 83 20,5 82,5 19,5 VZCD(rising) (mV) 82 tF (ns) 18,5 17,5 16,5 15,5 81,5 81 80,5 80 14,5 79,5 13,5 12,5 79 −50 −25 0 25 50 75 100 −50 125 −25 0 TEMPERATURE (°C) 25 50 75 100 125 TEMPERATURE (°C) Figure 21. tf vs. Temperature Figure 22. VZCD(rising) vs. Temperature 0,672 54,5 53,5 VZCD(short) (V) VZCD(falling) (mV) 0,67 52,5 51,5 0,668 0,666 0,664 0,662 50,5 0,66 49,5 −50 −25 0 25 50 75 100 0,658 125 −50 −25 0 TEMPERATURE (°C) 25 50 75 100 125 TEMPERATURE (°C) Figure 23. VZCD(falling) vs. Temperature Figure 24. VZCD(short) vs. Temperature 116 1,605 tZCD(blank1)OPN1 (ms) 111 tZCD(DEM) (ns) 106 101 96 91 86 1,595 1,585 1,575 1,565 81 1,555 76 −50 −25 0 25 50 75 100 −50 125 TEMPERATURE (°C) −25 0 25 50 75 100 TEMPERATURE (°C) Figure 25. tZCD(dem) vs. Temperature Figure 26. tZCD(blank1)OPN1 vs. Temperature www.onsemi.com 11 125 NCL30488 TYPICAL CHARACTERISTICS (continued) 0,861 tZCD(blank2)OPN1 (ms) tZCD(blank1)OPN2 (ms) 1,072 1,067 1,062 1,057 1,052 0,856 0,851 0,846 0,841 1,047 1,042 0,836 −50 −25 0 25 50 75 100 −50 125 −25 0 TEMPERATURE (°C) 50 75 100 125 Figure 28. tZCD(blank2)OPN1 vs. Temperature 0,584 6,92 0,579 6,87 tTIMO (ms) tZCD(blank2)OPN2 (ms) Figure 27. tZCD(blank1)OPN2 vs. Temperature 0,574 0,569 6,82 6,77 0,564 −50 −25 0 25 50 75 100 6,72 125 −50 −25 0 TEMPERATURE (°C) 25 50 75 100 125 100 125 TEMPERATURE (°C) Figure 29. tZCD(blank2)OPN2 vs. Temperature Figure 30. tTIMO vs. Temperature 336,8 3,545 336,3 3,535 335,8 3,525 VREF(CV) (V) 335,3 VREF/3 (mV) 25 TEMPERATURE (°C) 334,8 334,3 333,8 333,3 3,515 3,505 3,495 332,8 3,485 332,3 331,8 3,475 −50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 TEMPERATURE (°C) TEMPERATURE (°C) Figure 31. VREF/3 vs. Temperature Figure 32. VREF(CV) vs. Temperature www.onsemi.com 12 NCL30488 TYPICAL CHARACTERISTICS (continued) 4,15 4,075 4,065 4,13 4,055 VOVP1 (V) VCV(clampH) (V) 4,14 4,12 4,11 4,045 4,035 4,025 4,1 4,015 4,09 4,005 4,08 −50 −25 0 25 50 75 100 3,995 125 −50 −25 0 TEMPERATURE (°C) 25 50 75 100 125 100 125 100 125 TEMPERATURE (°C) Figure 33. VCV(clampH) vs. Temperature Figure 34. VOVP1 vs. Temperature 0,2095 4,54 0,2085 0,2075 KLFF (mA/V) VOVP2 (V) 4,53 4,52 4,51 0,2065 0,2055 0,2045 0,2035 0,2025 4,5 0,2015 0,2005 −50 4,49 −50 −25 0 25 50 75 100 125 −25 0 TEMPERATURE (°C) 25 50 75 TEMPERATURE (°C) Figure 35. VOVP2 vs. Temperature Figure 36. KLFF vs. Temperature 104 41,7 103 41,5 41,3 101 IFF (mA) Ioffset(MAX) (mA) 102 100 99 41,1 40,9 40,7 98 40,5 97 40,3 96 40,1 −50 −25 0 25 50 75 100 −50 125 TEMPERATURE (°C) −25 0 25 50 75 TEMPERATURE (°C) Figure 37. Ioffset(MAX) vs. Temperature Figure 38. IFF vs. Temperature www.onsemi.com 13 NCL30488 TYPICAL CHARACTERISTICS (continued) 1,0395 2,208 1,0375 2,203 VREF(PFC)CLP (V) 1,0385 tFF1LL (ms) 1,0365 1,0355 1,0345 1,0335 2,198 2,193 2,188 2,183 1,0325 2,178 1,0315 2,173 1,0305 −50 −25 0 25 50 75 100 2,168 125 −50 −25 0 TEMPERATURE (°C) Figure 39. tFF1LL vs. Temperature 50 75 100 125 Figure 40. VREF(PFC)CLP vs. Temperature 108,9 99,6 108,7 99,4 108,5 99,2 VHVBO(off)OPN1 (V) VHVBO(on)OPN1 (V) 25 TEMPERATURE (°C) 108,3 108,1 107,9 107,7 107,5 99 98,8 98,6 98,4 107,3 98,2 107,1 98 106,9 −50 −25 0 25 50 75 100 97,8 125 −50 −25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 41. VHVBO(on)ONP1 vs. Temperature Figure 42. VHVBO(off) vs. Temperature 472 446 471 445 VHV(OVP)RST (V dc) VHV(OVP) (V dc) 470 469 468 467 466 444 443 442 441 440 465 464 −50 −25 0 25 50 75 100 439 125 −50 TEMPERATURE (°C) −25 0 25 50 75 100 TEMPERATURE (°C) Figure 43. VHV(OVP) vs. Temperature Figure 44. VHV(OVP)RST vs. Temperature www.onsemi.com 14 125 NCL30488 Application Information The NCL30488 implements a current−mode architecture operating in quasi−resonant mode. Thanks to proprietary circuitry, the controller is able to accurately regulate the secondary side current and voltage of the fly−back converter without using any opto−coupler or measuring directly the secondary side current or voltage. The controller provides near unity power factor correction • Quasi−Resonance Current−Mode Operation: implementing quasi−resonance operation in peak current−mode control, the NCL30488 optimizes the efficiency by switching in the valley of the MOSFET drain−source voltage. Thanks to an internal algorithm control, the controller locks−out in a selected valley and remains locked until the input voltage or the output current set point significantly changes. • Primary Side Constant Current Control: thanks to a proprietary circuit, the controller is able to take into account the effect of the leakage inductance of the transformer and allows an accurate control of the secondary side current regardless of the input voltage and output load variation. • Primary Side Constant Voltage Regulation: By monitoring the auxiliary winding voltage, it is possible to regulate accurately the output voltage. The output voltage regulation is typically within ±2%. • Load Transient Compensation: Since PFC has low loop bandwidth, abrupt changes in the load may cause excessive over or under−shoot. The slow Over Voltage Protection contains the output voltage when it tends to become excessive. In addition, the NCL30488 speeds up the constant voltage regulation loop when the output voltage goes below 85% of its regulation level. • Power Factor Correction: A proprietary concept allows achieving high power factor correction and low THD while keeping accurate constant current and constant voltage control. • Line Feed−forward: allows compensating the variation of the output current caused by the propagation delay. • VCC Over Voltage Protection: if the VCC pin voltage exceeds an internal limit, the controller shuts down and waits 4 seconds before restarting pulsing. • Fast Over Voltage Protection: If the voltage of ZCD pin exceeds 130% of its regulation level, the controller shuts down and waits 4 s before trying to restart. • Brown−Out: the controller includes a brown−out circuit which safely stops the controller in case the input voltage is too low. The device will automatically restart if the line recovers. • Cycle−by−cycle peak current limit: when the current sense voltage exceeds the internal threshold VILIM, the MOSFET is turned off for the rest of the switching cycle. • Winding Short−Circuit Protection: an additional comparator senses the CS signal and stops the controller • • if VCS reaches 1.5 x VILIM (after a reduced LEB of tBCS). This additional comparator is enabled only during the main LEB duration tLEB, for noise immunity reason. Output Under Voltage Protection: If a too low voltage is applied on ZCD pin for 90 ms time interval, the controllers assume that the output or the ZCD pin is shorted to ground and shutdown. After waiting 4 seconds, the IC restarts switching. Thermal Shutdown: an internal circuitry disables the gate drive when the junction temperature exceeds 150°C (typically). The circuit resumes operation once the temperature drops below approximately 140°C. POWER FACTOR AND CONSTANT CURRENT CONTROL The NCL30488 embeds an analog/digital block to control the power factor and regulate the output current by monitoring the ZCD, CS and HV pin voltages (signals VZCD, VHV_DIV, VCS). This circuit generates the current setpoint signal and compares it to the current sense signal to turn the MOSFET off. The HV pin provides the sinusoidal reference necessary for shaping the input current. The obtained current reference is further modulated so that when averaged over a half line period, it is equal to the output current reference (VREFX). The modulation and averaging process is made internally by a digital circuit. If the HV pin properly conveys the sinusoidal shape, power factor will be close to 1. Also, the Total Harmonic Distortion (THD) will be low especially if the output voltage ripple is small. I OUT + V REF 2N spR sense (eq. 1) Where: • Nsp is the secondary to primary transformer turns ratio: Nsp = NS / NP • Rsense is the current sense resistor • VREFX is the output current reference: VREFX = VREF if no dimming The output current reference (VREFX) is VREF unless the controller operates in constant voltage mode. PRIMARY SIDE CONSTANT VOLTAGE CONTROL The auxiliary winding voltage is sampled internally through the ZCD pin. A precise internal voltage reference VREF(CV) sets the voltage target for the CV loop. The sampled voltage is applied to the negative input of the constant voltage (CV) operational transconductance amplifier (OTA) and compared to VREFCV. A type 2 compensator is needed at the CV OTA output to stabilize the loop. The COMP pin voltage modify the the output current internal reference in order to regulate the output voltage. When VCOMP ≥ 4 V, VREFX = VREF. When VCOMP < 0.9 V, VREFX = 0 V. www.onsemi.com 15 NCL30488 RZCDU ZCD VZCDsamp ZCD & signal sampling Gm COMP . RZCDL VREF(CV) Aux. OTA R1 C2 C1 Figure 45. Constant Voltage Feedback Circuit Secondary Side Regulation Compatible The HV startup circuitry is made of two startup current levels, IHV(start1) and IHV(start1). This helps to protect the controller against short−circuit between VCC and GND. At power−up, as long as VCC is below VCC(TH), the source delivers IHV(start1) (around 300 mA typical). Then, when VCC reaches VCC(TH), the source smoothly transitions to IHV(start2) and delivers its nominal value. As a result, in case of short−circuit between VCC and GND occurring at high line (Vin = 305 V rms), the maximum power dissipation will be 431 x 300 m = 130 mW instead of 1.5 W if there was only one startup current level. To speed−up the output voltage rise, the following is implemented: • The digital OTA output is increased until VREF(PFC) signal reaches VREFX. Again, this is to speed−up the control signal rise to their steady state value. • At the beginning of each operating phase of a VCC cycle, the digital OTA output is set to 0. Actually, the digital OTA output is set to 0 in the case of a cold start−up or in the case of a start−up sequence following an operation interruption due to a fault. On the other hand, if the VCC hiccups just because the system fails to start−up in one VCC cycle, the digital OTA output is not reset to ease the second (or more) attempt. • If the load is shorted, the circuit will operate in hiccup mode with VCC oscillating between VCC(off) and VCC(on) until the output under voltage protection (UVP) trips. UVP is triggered if the ZCD pin voltage does not exceed VZCD(short) within a 90 ms operation of time. This indicates that the ZCD pin is shorted to ground or that an excessive load prevents the output voltage from rising. The NCL30488 is able to support secondary−side regulation as well. The controller features an option to provide a pullup resistor Rpullup on COMP pin instead of the CV OTA output. This allows connecting directly an optocoupler collector and properly biases it. The internal voltage biasing Rpullup is around 5 V. In secondary side regulation, the slow and fast OVP on ZCD pin are still active thus providing an additional over voltage protection. In this case, the ZCD pin resistors should be calculated to trigger VOVP2 at the output voltage of interest. VDD CV OTA Boost Rpullup COMP − + VREF(CV) Figure 46. COMP Pin Configuration for Secondary Side Regulation STARTUP PHASE (HV STARTUP) It is generally requested that the LED driver starts to emit light in less than 1 s and possibly within 300 ms. It is challenging since the start−up consists of the time to charge the VCC capacitor and that necessary to charge the output capacitor until sufficient current flows into the LED string. This second phase can be particularly long in dimming cases where the secondary current is a portion of the nominal one. The NCL30488 features a high voltage startup circuit that allows charging VCC pin capacitor very fast. When the power supply is first connected to the mains outlet, the internal current source is biased and charges up the VCC capacitor. When the voltage on this VCC capacitor reaches the VCC(on) level, the current source turns off. At this time, the controller is only supplied by the VCC capacitor, and the auxiliary supply should take over before VCC collapses below VCC(off). HV Startup Power Dissipation At high line (305 V rms and above) the power dissipated by the HV startup in case of fault becomes high. Indeed, in case of fault, the NCL30488 is directly supplied by the HV rail. The current flowing through the HV startup will heat the controller. It is highly recommended adding enough copper around the controller to decrease the RqJA of the controller. Adding a minimum pad area of 215 mm2 of 35 mm copper (1 oz) drops the RqJA to around 120°C/W (no air flow, RqJA measured at ADIM pin) The PCB layout shown in Figure 47 is a layout example to achieve low RqJA. www.onsemi.com 16 NCL30488 Winding and Output Diode Short−Circuit Protection In parallel to the cycle−by−cycle sensing of the CS pin, another comparator with a reduced LEB (tBCS ) and a threshold of (VCS(stop) = 140% x VILIM ) monitors the CS pin to detect a winding or an output diode short circuit. The controller shuts down if it detects 4 consecutives pulses during which the CS pin voltage exceeds VCS(stop). The controller goes into auto−recovery mode. Valley Lockout Quasi−Square wave resonant systems have a wide switching frequency excursion. The switching frequency increases when the output load decreases or when the input voltage increases. The switching frequency of such systems must be limited. The NCL30488 changes valley as VREFX decreases and as the input voltage increases and as the output current setpoint is varied during dimming. This limits the frequency excursion. By default, when the output current is not dimmed, the controller operates in the first valley at low line and in the second valley at high line. (prog. option to have the operating valley incremented by 1 at high line for better Iout control at 305 V rms.) Figure 47. PCD Layout Example The application note ANDXXXX gives more details about strategies to decrease the power dissipation of the HV startup circuit. Cycle−by−Cycle Current Limit When the current sense voltage exceeds the internal threshold VILIM, the MOSFET is turned off for the rest of the switching cycle. Table 1. VALLEY SELECTION VHV_DIV Voltage for Valley Change 0 Iout decreases 100% 80% 65% 50% 35% 25% 0% 0 −−LL−− 2.3 V −−HL−− 1st 2nd (3rd) 2nd 3rd (4th) 3rd 4th (5th) 4th 5th (6th) 5th 6th (7th) FF mode FF mode −−LL−− 2.3 V −−HL−− 5V VREFX Value at Which the Controller Changes Valley(Iout Increasing) 100% 80% 65% 50% 35% Iout decreases VREFX value at which the Controller Changes Valley (Iout Decreasing) 25% 0% 5V Internal VHV_DIV Voltage for Valley Change Zero Crossing Detection Block The Time−out also acts as a substitute clock for the valley detection and simulates a missing valley in case of too damped free oscillations. At startup, the output voltage reflected on the auxiliary winding is low. Because of the ZCD resistor bridge setting the constant voltage regulation target, the voltage on the ZCD pin is very low and the ZCD comparator might be unable to detect the valleys. In this condition, setting the DRV Latch with the 6.5 ms time−out leads to a continuous conduction mode operation (CCM) at the beginning of the soft−start. This CCM operation only last a few cycles until the voltage on ZCD pin becomes high enough and trips the ZCD comparator. The ZCD pin allows detecting when the drain−source voltage of the power MOSFET reaches a valley. A valley is detected when the ZCD pin voltage crosses below the 55 mV internal threshold. At startup or in case of extremely damped free oscillations, the ZCD comparator may not be able to detect the valleys. To avoid such a situation, Optimus Prime features a Time−Out circuit that generates pulses if the voltage on ZCD pin stays below the 55 mV threshold for 6.5 ms. www.onsemi.com 17 NCL30488 VZCD VZCD(th) low 3 4 high 14 Iout decreases or Vin increases high 12 ZCD comp high low 15 TimeOut low 16 2nd , 3 rd high VVIN increases Clock low 17 Figure 48. Valley Detection and Time−out Chronograms If the ZCD pin or the auxiliary winding happen to be shorted the time−out function would normally make the controller keep switching and hence lead to improper regulation of the LED current. The Under Voltage Protection (UVP) is implemented to avoid these scenarios: a secondary timer starts counting when the ZCD voltage is below the VZCD(short) threshold. If this timer reaches 90 ms, the controller detects a fault and enters the auto−recovery fault mode. Slow OVP If ZCD voltage exceeds VOVP1 for 4 consecutive switching cycles, the controller stops switching during 1.4 ms. The PFC loop is not reset. After 1.4 ms, the controller initiates a new DRV pulse to refresh ZCD sampling voltage. If VZCD is still too high (VZCD > 115% VREF(CV)), the controller continues to switch with a 1.4 ms period. The controller resumes its normal operation when VZCD < 115% VREF(CV). During slow OVP, the peak current setpoint is COMP pin voltage scaled down by a fixed ratio. ZCD Over Voltage Protection Because of the power factor correction, it is necessary to set the crossover frequency of the CV loop very low (target 10 Hz, depending on power stage phase shift). Because the loop is slow, the output voltage can reach high value during startup or during an output load step. It is necessary to limit the output voltage excursion. For this, the NCL30488 features a slow OVP and a fast OVP on ZCD pin. Fast OVP If ZCD voltage exceeds VOVP2 (130% of VREF(CV)) for 4 consecutive switching cycles (slow OVP not triggered) or for 2 switching cycles if the slow OVP has already been triggered, the controller detects a fault and starts the auto−recovery fault mode (cf: Fault Management Section) www.onsemi.com 18 NCL30488 Line Feedforward HV v DD v VS CS I CS(offset) R LFF K LFF R sense Q_drv + 25 ms Blanking − BO_NOK 1 V / 0.9 V Figure 49. Line Feed−Forward and Brown−out Schematic The line voltage is sensed by the HV pin and converted into a current. By adding an external resistor in series between the sense resistor and the CS pin, a voltage offset proportional to the line voltage is added to the CS signal. The offset is applied only during the MOSFET on−time in order to not influence the detection of the leakage inductance reset. The offset is always applied even at light load in order to improve the current regulation at low output load. below VHVBO(off) for 25 ms typical. Exiting a brown−out condition overrides the hiccup on VCC (VCC does not wait to reach VCC(off)) and the IC immediately goes into startup mode. An option with higher brown−out levels is also available (see ordering table and electricals parameters) Line OVP In order to protect the power supply in case of too high input voltage, the NCL30488 features a line over voltage protection. When the voltage on HV pin exceeds VHV(OVP) the controller stops switching; VCC hiccups. When VHV becomes lower than VHV(OVP)RST for more than 25 ms, the controller initiates a clean startup sequence and re−starts switching. Brown−out In order to protect the supply against a very low input voltage, the controller features a brown−out circuit with a fixed ON/OFF threshold. The controller is allowed to start if a voltage higher than VHVBO(on) is applied to the HV pin and shuts−down if the HV pin voltage decreases and stays www.onsemi.com 19 NCL30488 V HV V HV(OVP) V HV(OVP)RST t LOVP(blank) V CC V CC(on) V CC(off) V DRV I out ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ Figure 50. Line OVP Chronograms Protections • Winding or Output Diode Short Circuit protection The circuit incorporates a large variety of protections to make the LED driver very rugged. Among them, we can list: • Fault of the GND connection If the GND pin is properly connected, the supply current drawn from the positive terminal of the VCC capacitor, flows out of the GND pin to return to the negative terminal of the VCC capacitor. If the GND pin is not connected, the circuit ESD diodes offer another return path. The accidental non connection of the GND pin can hence be detected by detecting that one of this ESD diode is conducting. Practically, the ESD diode of CS pin is monitored. If such a fault is detected for 200 ms, the circuit stops generating DRV pin. • Output short circuit situation (Output Under Voltage Protection) Overload is detected by monitoring the ZCD pin voltage: if it remains below VZCD(short) for 90 ms, an output short circuit is detected and the circuit stops generating pulses for 4 s. When this 4 s delay has elapsed, the circuit attempts to restart. • ZCD pin incorrect connection: ♦ If the ZCD pin grounded, the circuit will detect an output short circuit situation when 90 ms delay has elapsed. ♦ A 200 kW resistor pulls down the ZCD pin so that the output short circuit detection trips if the ZCD pin is not connected (floating). • • • • The circuit detects this failure when 4 consecutive DRV pulses occur within which the CS pin voltage exceeds (VCS(stop) = 140% x VILIM). In this case, the controller enters auto−recovery mode (4−s operation interruption between active bursts). VCC Over Voltage Protection The circuit stops generating pulses if the VCC exceeds VCC(OVP) and enters auto−recovery mode. This feature protects the circuit if output LEDs happen to be disconnected. ZCD fast OVP If ZCD voltage exceeds VZCD(OVP2) for 4 consecutive switching cycles (slow OVP not triggered) or for 2 switching cycles if the slow OVP has already been triggered, the controller detects a fault and enters auto−recovery mode (4 s operation interruption between active bursts). Die Over Temperature (TSD) The circuit stops operating if the junction temperature (TJ) exceeds 150°C typically. The controller remains off until TJ goes below nearly 130°C. Brown−Out Protection (BO) The circuit prevents operation when the line voltage is too low to avoid an excessive stress of the LED driver. Operation resumes as soon as the line voltage is high enough and VCC is higher than VCC(on). www.onsemi.com 20 NCL30488 • CS pin short to ground The CS pin is checked at start−up (cold start−up or after a brown−out event). A current source (Ics(short)) is applied to the pin and no DRV pulse is generated until the CS pin exceeds Vcs(low). Ics(short) and Vcs(low) are 500 mA and 60 mV typically (VCS rising). The typical minimum impedance to be placed on the CS pin for operation is then 120 W. In practice, it is recommended to place more than • 250 W to take into account possible parametric deviations. Also, along the circuit operation, the CS pin could happen to be grounded. If it is grounded, the MOSFET conduction time is limited by the 20 ms maximum on−time. If such an event occurs, a new pin impedance test is made. Line overvoltage protection (see Line OVP section) ORDERING TABLE OPTION Maximum Dead−time OPN # NCL30488_ _ 250 ms 687 ms VREF 1.4 ms 200 mV 333 mV Max. On−time ZCD Blanking 20 ms 1 ms 33 ms 1.5 ms Valley Transition from LL to HL 1st to 2nd 1st to 3rd Standby Mode On Line Range Detector Off On NCL30488A2 x x x x x x x NCL30488A3 x x x x x x x NCL30488A4 x x x x x x x Frozen Peak Current During Standby Mode VCS(SBY) Line OVP Brown−out Levels OPN # NCL30488_ _ On NCL30488A2 x NA NCL30488A3 x NA x NCL30488A4 x NA x Off 380 mV 330 mV 280 mV On: 108 V Off: 98 V On: 138 V Off: 129 V Off COMP Pin Rpullup (CV OTA output disconnected) On x Off x x x ORDERING INFORMATION Marking Package type Shipping† NCL30488A2 L30486A2 SOIC7 – P7 COMP VHV PBFH (Pb−Free) 2500 / Tape & Reel NCL30488A3 L30488A3 SOIC7 – P7 COMP VHV PBFH (Pb−Free) 2500 / Tape & Reel NCL30488A4 L30488A4 SOIC7 – P7 COMP VHV PBFH (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 21 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−7 CASE 751U−01 ISSUE E DATE 20 OCT 2009 SCALE 1:1 −A− 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B ARE DATUMS AND T IS A DATUM SURFACE. 4. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 5. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5 −B− S 0.25 (0.010) B M M 1 4 G C R X 45 _ J −T− SEATING PLANE H 0.25 (0.010) K M D 7 PL M T B S A DIM A B C D G H J K M N S INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 S GENERIC MARKING DIAGRAM SOLDERING FOOTPRINT* 8 1.52 0.060 7.0 0.275 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 1 XXX A L Y W G 4.0 0.155 0.6 0.024 = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. 1.270 0.050 SCALE 6:1 XXXXX ALYWX G mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: 98AON12199D DESCRIPTION: 7−LEAD SOIC Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−7 CASE 751U−01 ISSUE E STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. 7. NOT USED 8. EMITTER DATE 20 OCT 2009 STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. NOT USED 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. NOT USED 8. SOURCE, #1 STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. 6. 7. NOT USED 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. 7. NOT USED 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. NOT USED 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR (DIE 1) 2. BASE (DIE 1) 3. BASE (DIE 2) 4. COLLECTOR (DIE 2) 5. COLLECTOR (DIE 2) 6. EMITTER (DIE 2) 7. NOT USED 8. COLLECTOR (DIE 1) STYLE 9: PIN 1. EMITTER (COMMON) 2. COLLECTOR (DIE 1) 3. COLLECTOR (DIE 2) 4. EMITTER (COMMON) 5. EMITTER (COMMON) 6. BASE (DIE 2) 7. NOT USED 8. EMITTER (COMMON) STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. NOT USED 8. GROUND STYLE 11: PIN 1. SOURCE (DIE 1) 2. GATE (DIE 1) 3. SOURCE (DIE 2) 4. GATE (DIE 2) 5. DRAIN (DIE 2) 6. DRAIN (DIE 2) 7. NOT USED 8. DRAIN (DIE 1) STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. NOT USED 8. COMMON CATHODE DOCUMENT NUMBER: 98AON12199D DESCRIPTION: 7−LEAD SOIC Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. 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