CCM Buck Controller for
Precise Current Regulation
and Wide Analog Dimming
NCL35076
The NCL35076 is a DC−DC buck controller for wide dimming
range down to 1% by analog dimming control to relieve audible noise
and flicker in PWM dimming. ON Semiconductor’s proprietary LED
current calculation technique driven by zero input offset amplifiers
performs precise constant current in the whole analog dimming range.
Multi−mode operation provides low LED current ripple with small
output capacitor by CCM at heavy load and deep analog dimming by
DCM at light load.
PWM dimming is also provided in case that constant LED color
temperature is required. NCL35076 ensures high system reliability
with LED short protection, over current protection and thermal
shutdown.
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8
1
SOIC−8 NB
CASE 751
MARKING DIAGRAM
Features
•
•
•
•
•
•
•
•
Wide Analog Dimming Range: 1~100%
Low CC Tolerance: ±2% at 100% Load & ±20% at 1% Load
Low System BOM
LED Off Mode at Standby
Low Standby Current
PWM Dimming Available
Gate Sourcing and Sinking Current of 0.5 A/0.8 A
Robust Protection Features
♦ LED Short Protection
♦ Over Current Protection
♦ Thermal Shutdown
♦ VDD Over Voltage Protection
Typical Applications
• LED Lighting System
L35076AA
AWLYYWW
L30076
AA
A
WL
YYWW
= Specific Device Code
= Default Trimming Option
= Assembly Location
= Wafer Lot Traceability Code
= 4 Digit Data Code
PIN ASSIGNMENT
BIAS
PG
CSZCD
DRV
SG
VDD
FB
DIM
(Top View)
ORDERING INFORMATION
Device
Package
Shipping
NCL35076AADR2G
SOIC−8 NB
3000 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2020
April, 2021 − Rev. 2
1
Publication Order Number:
NCL35076/D
NCL35076
APPLICATION SCHEMATIC
30~200 Vin
PFC
VAC
Flyback
FB
DRV
DIM
Dimming
Signal
CSZCD
RCS
NCL35076
SG
BIAS
PG
VDD
External source
Figure 1. Application Schematic
BLOCK DIAGRAM
VDD
3.3 V
LDO
BIAS
VDD−ON
10 V /
8V
V PDIM || V SHUTDOWN
VTO FF.SS
Soft start
V FB
S
DRV
Q
VOFF
Toff generator
OTA
VPWM
VON
VTO FF.FB
R
VCS.LIM
VLED
CSZCD
FB
VREF
+ 30 mV
Reference control
VCS.LIM
DIM
PWM dimming control
VPDIM
Standby mode control
VSHUTDOWN
VDD
Precise LED
current calculator
PG
Over voltage protection
SG
LED short protection
Protection
AR control
Over current protection
VCSZCD
TJ
Thermal Shutdown
Figure 2. Simplified Block Diagram
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2
V SHUTDOWN
NCL35076
PIN CONFIGURATION
BIAS
PG
CSZCD
DRV
SG
VDD
FB
DIM
(Top View)
Figure 3. Pin Configuration
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Function
1
BIAS
3.3 V BIAS
2
CSZCD
CS and ZCD Sensing
3
SG
Signal Ground
Description
This pin is 3.3 V LDO output to bias the internal digital circuit
This pin detects the switch current and the inductor current zero cross time
Signal Ground is close to control pin circuit such as CSZCD, DIM and FB
4
FB
Feedback
5
DIM
Dimming Input
Output of feedback OTA
Dimming signal is provided to this pin
6
VDD
Power Supply
IC operating current is supplied to this pin
7
DRV
Output Drive
This pin is connected to drive external switch
8
PG
Power Ground
Power Ground is close to the capacitors at BIAS and VDD pin
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3
NCL35076
SPECIFICATIONS
MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
VDD, DRV Pin Voltage Range
VMV(MAX)
−0.3 to 30
V
DIM, FB, CSZCD, BIAS Pin Voltage Range
VLV(MAX)
−0.3 to 5.5
V
Maximum Power Dissipation (TA < 50°C)
PD(MAX)
550
mW
Maximum Junction Temperature
TJ(max)
150
°C
Storage Temperature Range
TSTG
−55 to 150
°C
Junction−to−Ambient Thermal Impedance
RθJA
145
°C/W
ESD Capability, Human Body Model (Note 2)
ESDHBM
2
kV
ESD Capability, Charged Device Model (Note 2)
ESDCDM
1
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
2. This device series incorporates ESD protection and is tested by the following methods:
− ESD Human Body Model per JEDEC Standard JESD22−A114
− ESD Charged Device Model per JEDEC Standard JESD22−C101
− Latch−up Current Maximum Rating ±100 mA per JEDEC Standard JESD78
RECOMMENDED OPERATING RANGES
Parameter
Junction Temperature
Symbol
Min
Max
Unit
TJ
−40
125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
ELECTRICAL CHARACTERISTICS (VDD = 15 V and TJ = −40~125°C unless otherwise specified)
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
VDD(ON)
9.3
10.0
10.7
V
VDD(OFF)
7.4
8.0
8.6
V
IDD(ST)
−
250
400
mA
Operating Current
IDD(OP)
−
6.5
8.0
mA
Standby Current
IDD(SB)
−
200
300
mA
VBIAS
3.23
3.30
3.37
V
3.25
3.30
3.35
V
VDIM(REF−MAX)
2.44
2.50
2.56
V
DIM Voltage for 99% VREF
VDIM(MAX−EFF)
2.400
2.475
2.528
V
Standby Enabling DIM Voltage
VDIM(SB−ENA)
50
75
100
mV
Standby Disabling DIM Voltage
VDIM(SB−DIS)
60
100
140
mV
tSB(DELAY)
9
10
11
ms
VDD SECTION
IC Turn−On Threshold Voltage
IC Turn−Off Threshold Voltage
Startup Current
VDD = VDD(ON) − 1.6 V
BIAS SECTION
BIAS Voltage
TJ = 25~100°C (Note 4)
DIM SECTION
DIM Voltage for 100% VREF
VDIM = 2.6 V
Standby Delay Time
FB SECTION
FB OTA Source Current
IFB = (VLED − VREF) x gM(FB) x 12.5
VREF = 120 mV, VLED = 80 mV
IFB(SOURCE)
−14.0
−11.5
−9.0
mA
FB OTA Sink Current
IFB = (VLED − VREF) x gM(FB) x 12.5
VREF = 40 mV, VLED = 80 mV
IFB(SINK)
9.0
11.5
14.0
mA
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NCL35076
ELECTRICAL CHARACTERISTICS (VDD = 15 V and TJ = −40~125°C unless otherwise specified) (continued)
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
FB OTA Transconductance
gM(FB) = IFB / {(VREF − VLED) x 12.5}
gM(FB)
18
23
28
mmho
FB OTA High Voltage
VREF = 120 mV, VLED = 80 mV
VFB(HIGH)
4.7
−
−
V
FB Minimum Clamping Voltage
VREF = 0 mV, VLED = 80 mV
VFB(CLP)
0.4
0.5
0.6
V
VCS(REG−MAX)
175
180
185
mV
CS Current Ripple Voltage
VCS(RIPPLE)
25
30
35
mV
CS Current Limit Minimum
VCS(LIM−MIN)
72
80
88
mV
Leading Edge Blanking Time at
Turn−on
tLEB(TON)
360
400
440
ns
Maximum Ton Time
tON(MAX)
45
50
55
ms
tOFF(MIN)
400
850
1000
ns
FB SECTION
CS SECTION
CS Regulation
DUTY SECTION
Minimum Toff Time
VFB = 3.8 V
Maximum Toff Time
VFB = 0.5 V
tOFF(MAX)
1.17
1.30
1.43
ms
Maximum FB Voltage for Min. Toff
VFB(MAX−TOFF)
3.30
3.43
3.55
V
Minimum FB Voltage for Max. Toff
VFB(MIN−TOFF)
0.9
1.1
1.3
V
VDRV(LOW)
−
−
0.2
V
VDRV(HIGH)
11
12
13
V
DRV SECTION
DRV Low Voltage
DRV High Voltage
VDD = 15 V
DRV Rising Time
CDRV = 3.3 nF
tDRV(R)
60
100
145
ns
DRV Falling Time
CDRV = 3.3 nF
tDRV(F)
25
55
105
ns
tAR(PROT)
0.9
1.0
1.1
s
VDD(OVP)
22
23
24
V
SLP Monitoring Triggering Delay
Time
tSLP(MON−DEL)
18
20
22
ms
SLP Monitoring Disable Time at
Startup
tSLP(MON−DIS)
10.8
12.0
13.2
ms
VCS(OCP)
0.4
0.5
0.6
V
TSD
130
150
170
°C
TSD(HYS)
25
30
35
°C
AUTO RESTART SECTION
Auto Restart Time at Protection
VDD OVER VOLTAGE PROTECTION SECTION
VDD Over Voltage Threshold Voltage
SHORT LED PROTECTION SECTION
OVER CURRENT PROTECTION SECTION
CS Over Current Protection Threshold
THERMAL SHUTDOWN SECTION
Thermal Shut Down Temperature
(Note 3)
Thermal Shut Down Hysteresis
(Note 3)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Guaranteed by design.
4. Guaranteed by characterization.
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NCL35076
TYPICAL CHARACTERISTICS
1.006
1.006
1.004
1.004
Normalized at 255C
Normalized at 255C
(These characteristic graphs are normalized at TA = 25°C)
1.002
1
0.998
0.996
0.994
−40
−20
0
20
40
60
80
100
120
1.002
1
0.998
0.996
0.994
−40
140
−20
0
1.03
1.006
1.02
1.004
1.01
1
0.99
0.98
−20
0
20
40
60
80
100
120
0.994
−40
140
−20
0
Normalized at 255C
Normalized at 255C
1.002
1
0.998
0.996
80
20
40
60
80
100
120
140
Figure 7. VCS(REG−MAX) vs. Temperature
1.004
60
140
Temperature (5C)
1.004
40
120
0.996
1.006
20
100
0.998
1.006
0
80
1
Figure 6. gM(FB) vs. Temperature
−20
60
1.002
Temperature (5C)
0.994
−40
40
Figure 5. VDIM(MAX) vs. Temperature
Normalized at 255C
Normalized at 255C
Figure 4. VBIAS vs. Temperature
0.97
−40
20
Temperature (5C)
Temperature (5C)
100
120
1.002
1
0.998
0.996
0.994
−40
140
−20
0
20
40
60
80
100
Temperature (5C)
Temperature (5C)
Figure 8. VCS(LIM−MIN) vs. Temperature
Figure 9. VDD(OVP) vs. Temperature
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6
120
140
NCL35076
APPLICATION INFORMATION
OTA, CC tolerance is less than ±2% at 100% load and ±20%
at 1% load in the system variation.
General
NCL35076 provides wide analog dimming down to 1%
with high CC accuracy. According to buck inductor, input
voltage and output voltage, deep dimming down to
0.1~0.2% load can be achieved. Thanks to the ON
semiconductor’s proprietary LED current calculation
technique, NCL35076 is able to measure the current of LED
load connected at input voltage node without the upper limit
of the input voltage with high system reliability. LED
current is sensed and regulated by internal zero input offset
amplifiers so that NCL35076 performs precise CC
regulation in the whole analog dimming range. Therefore,
CC tolerance is tightly controlled in ±2% at 100% load and
±20% at 1% load.
Soft start
Without soft start in the closed loop CC control, the LED
current overshoot is easily occurred at startup so that the
overshoot can affect a lifetime of LEDs and incur an
undesirable flash. NCL35076 provides soft start technique
to prevent the LED current overshoot by TOFF time control.
Standby Mode
When VDIM is lower than a standby threshold voltage for
10 ms, standby mode is triggered with LED turn−off and IC
current consumption is minimized.
Auto Restart (AR) at Protection
Wide Analog Dimming
Once protection is triggered, IC operation stops for
1 second and begins soft start operation after the auto restart
time delay.
Wide analog dimming range is obtained by transitioning
multi−mode between CCM and DCM according to the
dimming condition. At full load condition, CCM with ±17%
inductor current ripple minimizes the conduction loss with
high efficiency and DCM is entered at light load condition
to perform analog deep dimming. Dimming curve linearity
is obtained by a digital compensator in the entire dimming
range.
VDD Over Voltage Protection (OVP)
When VDD is higher than 23 V, over voltage protection
is triggered.
Short LED Protection (SLP)
When LED is short circuited, the buck stage operates in
CCM with maximum turn−off time. By detecting this
condition, short LED protection is triggered.
PWM Dimming
Analog dimming has benefits for less audible noise and
flicker compared to PWM dimming. However, there is
a need of PWM dimming method to keep the constant LED
color temperature in specific applications. NCL35076
supports PWM dimming by simply inputting PWM
dimming signal to DIM pin.
Over Current Protection (OCP)
When CSZCD voltage exceeds the over current threshold
voltage, switching is immediately shut down after leading
edge blanking time in the short circuit condition of the
inductor, the freewheeling diode or the LED load.
Precise CC Regulation
Thermal Shot Down (TSD)
CC regulation is very important especially in
programmable LED driver because the driver should keep
precise CC control under the system variation of LED load,
inductor, temperature, etc. Since NCL35076 applies zero
input offset amplifiers at LED current calculator block and
When IC junction temperature is higher than 150°C, TSD
is triggered and released when the temperature is lower than
120°C.
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NCL35076
BASIC OPERATION
NCL35076 is the current mode buck controller in which
DRV is off when VCSZCD reaches to VCS.LIM (= VREF +
30 mV) and DRV is on by TOFF generator controlled by VFB.
VLED is calculated based on VCSZCD in precise LED current
calculator block composed of zero input offset amplifiers
and VREF is controlled by DIM signal. In reference control
block, VREF is obtained by below equation.
V REF [V] +
V DIM * 0.25 V
C
I INDUCTOR x RCS
A
V CS.LIM
210 mV
A(CCM)
+ 30 mV
180 mV
VREF
B(DCM)
80 mV
(eq. 1)
V DIM
12.5
t
VLED is compared with VREF at OTA to generate VFB
which controls TOFF time in TOFF generator. TOFF is
inversely proportional to VFB. Therefore, TOFF is shorter as
VFB increases. TOFF is set by below equation.
T OFF [ms] +
B
1.8
) 0.1
V FB * 1.1
VFB
1.1 V
0.5 V
V DIM
0.75 V
0.25 V
(eq. 2)
2.5 V
0.1/0.07 5 V
Figure 11. Operation Mode vs. VDIM
Flyback
CIN
VAC
ILED =
VDIM − 0.25 V
DLED
CLED
Precise CC Regulation
DBUCK
12.5 x RCS
The output of the precise LED current calculator, VLED,
is generated by analog sensing amplifiers and VLED is
compared with VREF by OTA to generate VFB. Those
sensing amplifiers and OTA have zero input offset
compensation technique which performs the excellent CC
regulation.
Table 1 shows CC tolerance measured by changing
inductor (±20%), temperature (−10, 25, 90 °C), output
voltage (10, 30, 50 V) and controller 150 pcs(3 lot variation)
in 60 V input 75 W driver. As a result, CC tolerance with
system variables at 1% deep dimming condition is less than
±20% and less than ±2.0% at full load condition.
LBUCK
RZCD1
Soft
start
TOFF.SS
TOFF.FB
VON
VOFF
VFB
VCS.LIM
QBUCK
RZCD2
CSZCD
VLED
VREF
DIM
DRV
R
TOFF
generator
OTA
FB
S Q
VPWM
Precise LED
current calculator
VLED = ILED x RCS
Reference control
+ 30 mV
Standby mode control
VSTANDBY
RCS
VCS.LIM
Figure 10. NCL35076 Block Diagram
Wide Analog Dimming
NCL35076 operates in CCM at heavy load and in DCM
at light load for a wide analog dimming. Figure 11 shows
how NCL35076 operates with VDIM.
• A: VCS.LIM follows VREF + 30 mV which is ±17%
inductor current ripple at 2.5 VDIM. VFB is almost
constant with same TOFF in the CCM region.
• B: VCS.LIM is clamped to 80 mV and doesn’t changed by
VDIM. TOFF is lengthened for dimming as VFB is
decreased. Operating mode is transitioned from CCM to
DCM at the boundary of A and B region.
• C: When VDIM is lower than 0.25 V, VREF is set to 0 V and
VFB is pulled down to 0.5 V clamping voltage with min.
LED current under open loop control. When VDIM is
further lower than 0.1/0.075 V, standby is triggered with
LED turn−off.
Figure 12. NCL35076 Dimming Curve and CC
Tolerance
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NCL35076
Table 1. CC TOLERANCE (150 pcs)
Inductor : + 20%
Temp. : −10 / 25 / 90 5C
100% Load
50% Load
10% Load
5% Load
2% Load
1% Load
VOUT : 10 V
1.52
1.92
3.24
4.18
7.43
13.06
VOUT : 30 V
1.40
1.54
3.26
4.38
7.99
13.87
VOUT : 50 V
1.25
1.37
2.68
3.57
7.17
14.06
VOUT : 10 / 30 / 50 V
1.62
1.98
4.10
4.94
8.24
15.40
Standby Mode
t OFF (MAX )
1300 ms
Standby mode is triggered by VDIM as shown in
Figure 13.
• A: When VDIM is lower than VDIM(SB−ENA), DRV block
is shut down. So, LED lamps turn off.
• B: After tSB(DELAY) (10 ms), standby mode is entered and
NCL35076 current consumption drops to IDD(SB).
• C: When VDIM is higher than VDIM(SB−DIS), standby
mode is immediately terminated and IC starts up.
A
B
C
Fast
SS
Slow
SS
Steady
State
T OFF
T OFF.SS
T OFF.FB
A
B
C
100 mV VDIM(SB−DIS)
VFB
75 mV VDIM(SB−ENA)
VDRV
tSB(DELAY)
VREF
Standby Mode
VLED
VFB
I INDUCTOR
Time
Figure 13. NCL35076 Standby Mode
Soft Start
ZCD in DCM
During soft start operation, TOFF is decided by either
TOFF_SS or TOFF_FB. TOFF is governed by TOFF_SS in early
start up because TOFF_SS decreases from tOFF(MAX). When
TOFF_SS reaches to the steady state level, VFB is settled to the
regulation level and TOFF is finally decided by TOFF_FB. In
the end of the soft start time, TOFF_SS reaches to 0 and
doesn’t affect TOFF control anymore. Figure 14 shows how
the soft start operates.
No ZCD in CCM
Time
Figure 14. Soft Start Sequence
• A: VFB is pulled up as VLED is far below VREF. TOFF_SS
•
•
is reduced quickly from tOFF(MAX) in Fast SS. Fast SS
ends when inductor current zero cross (ZCD) is not
detected.
B: Slow SS starts when there is no ZCD in CCM.
C: VLED is closer to VREF, and VFB starts falling. Then,
TOFF is determined by TOFF_FB and the steady state starts.
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NCL35076
• Short LED Protection (SLP)
Protections
When protection is triggered, all functional blocks stop
operating and begin to start up after 1 second AR time.
• VDD Over Voltage Protection (OVP)
When VDD is higher than VDD(OVP) (23 V), VDD OVP
is triggered. Open LED protection can be implemented by
VDD OVP when VDD is supplied by auxiliary winding
in the buck inductor.
• Over Current Protection (OCP)
When CSZCD voltage is higher than VCS(OCP) (0.5 V)
after leading edge blanking time, tLEB(TON) (400 ns), IC
immediately shuts down.
VCSZCD
•
t LE B(TON)
OCP
VCS(OCP)
When LED load is short−circuited, demagnetizing time of
the inductor is very long due to zero output voltage so that
TOFF is lengthened and TON is very short. If CCM and
tOFF(MAX) are detected for SLP monitoring time,
tSLP(MON−DEL) (20 ms), SLP is triggered. In order to
prevent abnormal SLP triggering at startup, SLP
monitoring is disabled for tSLP(MON−DIS) (12 ms) after 1st
switching begins.
Thermal Shut Down (TSD)
When the junction temperature is higher than TSD, the
system shuts down and the junction temperature is
monitored at every 1 second delay time (AR time). When
the temperature is lower than TSD – TSD(HYS), the system
restarts.
Figure 15. OCP Block
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10
NCL35076
APPENDIX: DIMMING CURVE AND CC TOLERANCE WITH SYSTEM VARIABLES
− System: NCL35076 75 W (VIN: 60V / VOUT: 10 ~ 50V / IOUT(MAX): 1.5 A)
− Temperature variation: −10 / 25 / 90 °C
− Inductance variation: ±20% (120 uH ~ 180 uH)
− Output Voltage: 10 / 30 / 50 V
− NCL35076 Controller: 150 pcs (3 lot variation)
Wide Output Condition (10/30/50V)
NCL35076 150pcs (3lot) + Temp & Inductor variation
+/− 20%
+/− 10%
+/− 5%
+/− 6%
+/− 3%
Single Output Condition (10V)
NCL35076 150pcs (3lot) + Temp & Inductor variation
+/− 15%
+/− 8%
+/− 4%
+/− 5%
+/− 3%
Single Output Condition (30V)
NCL35076 150pcs (3lot) + Temp & Inductor variation
+/− 15%
+/− 8%
+/− 4%
+/− 5%
+/− 3%
Single Output Condition (50V)
NCL35076 150pcs (3lot) + Temp & Inductor variation
+/− 15%
+/− 8%
+/− 4%
+/− 5%
Figure 16. CC Tolerance (150 pcs)
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11
+/− 3%
NCL35076
PCB LAYOUT GUIDANCE
(75−W Demo Board Schematic)
2
(PCB Layout Guidance)
Jumper
1
4
3
Jumper
Jumper
L
(75−W Demo Board PCB Layout − Bottom)
Figure 17. Layout Guidance
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12
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
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