NCN2612B
6-Channel Differential 1:2
Switch for PCIe 2.0 and
Display Port 1.1
The NCN2612B is a 6−Channel differential SPDT switch designed
to route PCI Express Gen2 and/or DisplayPort 1.1a signals. Due to the
ultra−low ON−state capacitance (2.1 pF typ) and resistance (8 W typ),
this switch is ideal for switching high frequency signals up to a signal
bit rate (BR) of 5 Gbps. This switch pinout is designed to be used in
BTX form factor desktop PCs and is available in a space−saving
5x11x0.75 mm WQFN56 package. The NCN2612B uses 80% less
quiescent power than other comparable PCIe switches.
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MARKING
DIAGRAM
NCN2612B
AWLYYWWG
WQFN56
CASE 510AK
Features
BTX Pinout
VDD Power Supply from 3 V to 3.6 V
Low Supply Current: 250 mA typ
6 Differential Channels, 2:1 MUX/DEMUX
Compatible with Display Port 1.1a & PCIe 2.0
Data Rate: Supports 5 Gbps
Low RON Resistance: 8 W typ
Low CON Capacitance: 2.1 pF
Space Saving, Small WQFN−56 Package
This is a Pb−Free Device
A
WL
YY
WW
G
Typical Applications
D1 +/−
D2 +/−
PCIe BUFF1
IN_0 +/−
PCIe BUFF2
IN_1 +/−
IN_2 +/−
IN_3 +/−
D3 +/−
HPD1/HPD2
AUX +/−
NCN2612B
X +/−
OUT +/−
AUX
Package
Shipping†
NCN2612BMTTWG
WQFN56
(Pb−Free)
2000 /
Tape & Reel
Tx0 +/−
Tx1 +/−
Tx2 +/−
Tx3 +/−
Rx0 +/−
Rx1 +/−
PCIe Graphics (PEG) Connector
D0 +/−
Graphics and
Memory
Controller Hub
(GMCH)
PCIe IN
Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
• Notebook Computers
• Desktop Computers
• Server/Storage Networks
PCI
Express PCIe BUFF3
Graphics
(PEG) PCIe BUFF4
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Display Port Connector
•
•
•
•
•
•
•
•
•
•
1
Figure 1. Application Schematic
© Semiconductor Components Industries, LLC, 2011
August, 2011 − Rev. 0
1
Publication Order Number:
NCN2612B/D
NCN2612B
IN_0+
D0+
IN_0−
D0−
IN_1+
D1+
IN_1−
D1−
IN_2+
D2+
IN_2−
D2−
IN_3+
D3+
IN_3−
D3−
Tx0+
Tx0−
Tx1+
Tx1−
Tx2+
Tx2−
Tx3+
Tx3−
OUT+
AUX+
OUT−
AUX−
X+
HPD1
X−
HPD2
Rx0+
Rx0−
Rx1+
Rx1−
SEL
Logic Control
LE
Figure 2. NCN2612B Block Diagram
TRUTH TABLE (SEL Control)
Function
TRUTH TABLE (Latch Control)
SEL
LE
PCI Express Gen2 Path is Active (Tx, Rx)
L
L
Respond to Changes on SEL
Digital Video Port is Active (D, HPD, AUX)
H
H
Latched
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2
Internal Mux Select
49 GND
50 VDD
51 D1−
52 D1+
53 D0−
54 D0+
55 VDD
56 GND
NCN2612B
GND
1
48 GND
SEL
2
47 D2+
LE
3
46 D2−
IN_0+
4
45 D3+
IN_0−
5
44 D3−
VDD
6
43 Tx0+
IN_1+
7
42 Tx0−
IN_1−
8
41 Tx1+
IN_2+
9
40 Tx1−
Exposed Pad on
Underside
(solder to external
Gnd)
IN_2− 10
GND
11
IN_3+
12
39 Tx2+
38 Tx2−
37 Tx3+
IN_3− 13
36 Tx3−
14
35 GND
OUT− 15
34 VDD
OUT+
GND
16
33 AUX+
VDD
17
32 AUX−
X+
18
31 HPD1
X− 19
30 HPD2
29 GND
Figure 3. Pinout
(Top View)
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3
GND 28
VDD 27
Rx0+ 26
Rx0− 25
Rx1+ 24
Rx1− 23
VDD 22
20
GND 21
GND
NCN2612B
PIN FUNCTION AND DESCRIPTION
Pin
Name
6, 17, 22, 27,
34,50, 55
VDD
DC Supply, 3.3 V $10%
Description
1, 11, 16, 20, 21,
28, 29, 35, 48,
49, 56
GND
Power Ground.
Exposed Pad
−
2
SEL
3
LE
4
IN_0+
Differential input from GMCH PCIE outputs. IN_0+ makes a differential pair with IN_0−.
5
IN_0−
Differential input from GMCH PCIE outputs. IN_0− makes a differential pair with IN_0+.
7
IN_1+
Differential input from GMCH PCIE outputs. IN_1+ makes a differential pair with IN_1−.
8
IN_1−
Differential input from GMCH PCIE outputs. IN_1− makes a differential pair with IN_1+.
The exposed pad on the backside of package is internally connected to Gnd. Externally the exposed
pad should also be user−connected to GND.
SEL controls the mux through a flow−through latch. Do not float this pin.
SEL = 0 for PCIE Mode; SEL = 1 for DP Mode
LE controls the latch gate. Do not float this pin.
9
IN_2+
Differential input from GMCH PCIE outputs. IN_2+ makes a differential pair with IN_2−.
10
IN_2−
Differential input from GMCH PCIE outputs. IN_2− makes a differential pair with IN_2+.
12
IN_3+
Differential input from GMCH PCIE outputs. IN_3+ makes a differential pair with IN_3−.
13
IN_3−
Differential input from GMCH PCIE outputs. IN_3− makes a differential pair with IN_3+.
14
OUT+
Pass−through output from AUX+ input when SEL = 1. Pass−through output from Rx0+ input when
SEL = 0.
15
OUT−
Pass−through output from AUX− input when SEL = 1. Pass−through output from Rx0− input when
SEL = 0.
18
X+
X+ is an analog pass−through output corresponding to Rx1+.
19
X−
X− is an analog pass−through output corresponding to the Rx1− input. The path
from Rx1− to X− must be matched with the path from Rx1+ to X+. X+ and X− form a
differential pair when the pass−through mux mode is selected.
23
Rx1−
Differential input from PCIE connector or device. Rx1− makes a differential pair with Rx1+. Rx1− is
passed through to the X− pin on the path that matches the Rx1+ to X+ pin.
24
Rx1+
Differential input from PCIE connector or device. Rx1+ makes a differential pair with Rx1−. Rx1+ is
passed through to the X+ pin when SEL = 0.
25
Rx0−
Differential input from PCIE connector or device. Rx0− makes a differential pair with Rx0+. Rx0− is
passed through to the OUT− pin when SEL = 0.
26
Rx0+
Differential input from PCIE connector or device. Rx0+ makes a differential pair with Rx0−. Rx0+ is
passed through to the OUT+ pin when SEL = 0.
30
HPD2
Negative low frequency HPD input handshake protocol signal (normally not connected).
31
HPD1
Positive low frequency HPD input handshake protocol signal.
32
AUX−
Differential input from HDMI/DP connector. AUX− makes a differential
pair with AUX+. AUX− is passed through to the OUT− pin when SEL = 1.
33
AUX+
Differential input from HDMI/DP connector. AUX+ makes a differential
pair with AUX−. AUX+ is passed through to the OUT+ pin when SEL = 1.
37, 36
Tx3+, Tx3−
Analog pass−through output#2 corresponding to IN_3+ and IN_3− when SEL = 0.
39, 38
Tx2+, Tx2−
Analog pass−through output#2 corresponding to IN_2+ and IN_2− when SEL = 0.
41, 40
Tx1+, Tx1−
Analog pass−through output#2 corresponding to IN_1+ and IN_1− when SEL = 0.
43, 42
Tx0+, Tx0−
Analog pass−through output#2 corresponding to IN_0+ and IN_0− when SEL = 0.
45, 44
D3+, D3−
Analog pass−through output#1 corresponding to IN_3+ and IN_3−, when SEL = 1.
47, 46
D2+, D2−
Analog pass−through output#1 corresponding to IN_2+ and IN_2−, when SEL = 1.
52, 51
D1+, D1−
Analog pass−through output#1 corresponding to IN_1+ and IN_1−, when SEL = 1.
54, 53
D0+, D0−
Analog pass−through output#1 corresponding to IN_0+ and IN_0−, when SEL = 1.
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4
NCN2612B
MAXIMUM RATINGS
Symbol
Rating
Unit
Power Supply Voltage
Parameter
VDD
−0.5 to 5.3
VDC
Input/Output Voltage Range of the Switch
(Tx, Rx, D, HPD, AUX, IN_, OUT, X)
VIS
−0.5 to VDD + 0.3
VDC
Selection Pin Voltages (SEL and LE)
VIN
−0.5 to VDD + 0.3
VDC
Continuous Current Through One Switch Channel
IIS
±120
mA
Maximum Junction Temperature (Note 1)
TJ
150
°C
Operating Ambient Temperature
TA
−40 to +85
°C
Storage Temperature Range
Tstg
−65 to +150
°C
Thermal Resistance, Junction−to−Air (Note 2)
RqJA
37
°C/W
ILU
±100
mA
Human Body Model (HBM) ESD Rating (Note 4)
ESD HBM
7000
V
Machine Model (MM) ESD Rating (Note 4)
ESD MM
400
V
MSL
Level 1
−
Latch−up Current (Note 3)
Moisture Sensitivity (Note 5)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded.
2. This parameter is based on EIA/JEDEC 51−7 with a 4−layer PCB, 80 mm x 80 mm, two 1oz Cu material internal planes and top planes of
2oz Cu material.
3. Latch up Current Maximum Rating: ±100 mA per JEDEC standard: JESD78.
4. This device series contains ESD protection and passes the following tests:
Human Body Model (HBM) ±7.0 kV per JEDEC standard: JESD22−A114 for all pins.
Machine Model (MM) ±400 V per JEDEC standard: JESD22−A115 for all pins.
5. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
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5
NCN2612B
ELECTRICAL CHARACTERISTICS (VDD = +3.3V ±10%, TA = −40°C to +85°C, unless otherwise noted. All Typical values are at
VDD = +3.3 V, TA = +25°C, unless otherwise noted.)
Characteristics
Symbol
Conditions
Min
Typ
Max
Unit
POWER SUPPLY
VDD
Supply Voltage Range
IDD
Power Supply Current
3.0
VDD = 3.6 V, VIN = GND or VDD
3.3
3.6
V
250
350
mA
1.2
V
DATA SWITCH PERFORMANCE (for both PCIe and Display Port applications, unless otherwise noted)
VIS
Data Input/Output Voltage
Range
0
RON
On Resistance (Tx, Rx)
VDD = 3 V, VIS = 0 V to 1.2 V, IIS = 15 mA
8.0
13
W
RON
On Resistance (D, HPD, AUX)
VDD = 3 V, VIS = 0 V to 1.2 V, IIS = 15 mA
9.0
13
W
RON(flat)
On Resistance Flatness
VDD = 3 V, VIS = 0 V to 1.2 V, IIS = 15 mA
(Note 6)
0.1
1.24
W
DRON
On Resistance Matching
(Tx, Rx)
VDD = 3 V, VIS = 0 V, IIS = 15 mA
0.35
W
DRON
On Resistance Matching
(D, HPD, AUX)
VDD = 3 V, VIS = 0 V, IIS = 15 mA
0.35
W
pF
CON
On Capacitance
f = 1 MHz, Switch On, Open Output
2.1
COFF
Off Capacitance
f = 1 MHz, Switch Off
1.6
pF
ION
On Leakage Current
(IN_/ X/OUT)
VDD = 3.6 V, VIN_ = Vx = VOUT = 0 V, 1.2 V;
Switch On to D/HPD/AUX or Tx/Rx; outputs
unconnected
−1
+1
mA
IOFF
Off Leakage Current
(D/Tx/HPD/Rx/AUX)
VDD = 3.6 V, VIN_ = VX_ = VOUT_ = 0 V, 1.2 V;
Switch Off; VD = VHPD = VAUX or VD = VHPD =
VAUX set to 1.2 V, 0 V
−1
+1
mA
V
CONTROL LOGIC CHARACTERISTICS (SEL and LE pins)
VIL
Off voltage input
0
0.8
VIH
High voltage input
2
VDD
V
IIN
Off voltage input
−1
+1
mA
CIN
High voltage input
VIN = 0 V or VDD
f = 1 MHz
1
pF
5
Gbps
f = 100 MHz
−0.7
dB
f = 1.35 GHz
−1.3
f = 2.5 GHz
−1.9
f = 3.0 GHz
−1.9
f = 100 MHz
−54
f = 1.35 GHz
−30
f = 2.5 GHz
−24
f = 3.0 GHz
−22
f = 5.0 GHz
−17
f = 100 MHz
−50
f = 1.35 GHz
−32
f = 2.5 GHz
−27
f = 3.0 GHz
−25
f = 5.0 GHz
−25
DYNAMIC CHARACTERISTICS
BR
Signal Data Rate
DIL
Differential Insertion Loss
DISO
DCTK
DRL
Differential Off Isolation
Differential Crosstalk
Differential Return Loss
f = 100 MHz
−20
f = 1.35 GHz
−14
f = 2.5 GHz
−10
f = 3.0 GHz
−6
6. Guaranteed by characterization and/or design.
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6
dB
dB
dB
NCN2612B
SWITCHING CHARACTERISTICS (VDD = +3.3 V, TA = 25°C, unless otherwise specified)
Symbol
tb−b
tch−ch
Characteristics
Bit−to−bit skew
Channel−to−channel skew
Conditions
Min
Typ
Max
Unit
Within the same differential pair
7
ps
Maximum skew between all channels
55
ps
SELECTION PINS SWITCHING CHARACTERISTICS (VDD = +3.3 V, TA = 25°C, unless otherwise specified)
Symbol
Characteristics
Conditions
TSELON
SEL to Switch turn ON time
VIS = 1 V, RL = 50 W, VLE = VDD, CL = 100 pF
9.5
ns
TSELOFF
Min
Typ
Max
Unit
SEL to Switch turn OFF time
VIS = 1 V, RL = 50 W, VLE = VDD, CL = 100pF
5
ns
TSET
LE setup time SEL to LE
VIS = 1 V, RL = 50 W, VLE = VDD, CL = 100 pF
1
ns
THOLD
LE hold time LE to SEL
VIS = 1 V, RL = 50 W, VLE = VDD, CL = 100 pF
1
ns
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7
NCN2612B
TYPICAL OPERATING CHARACTERISTICS
Figure 5. Eye Diagram for DisplayPort at 2.7 Gbps,
340 mVpp Differential Swing (Minimum Case)
0
0
−10
−10
−20
−20
−30
MAGNITUDE (dB)
MAGNITUDE (dB)
Figure 4. Eye Diagram for PCI Express at 5 Gbps,
800 mVpp Differential Swing (Minimum Case)
−40
−50
−60
−70
−80
−30
−40
−50
−60
−70
−80
−90
−100
10000000
100000000
1E+09
1E+10
−90
10000000
100000000
FREQUENCY (Hz)
0
12
−4
11
−12
−16
−20
−24
−28
10000000
100000000
1E+09
1E+10
Figure 7. Differential Off Isolation
RON, ON RESISTANCE (W)
MAGNITUDE (dB)
Figure 6. Differential Crosstalk
−8
1E+09
FREQUENCY (Hz)
1E+10
VCC=3.0
VCC=3.3
10
VCC=3.6
9
8
7
6
5
0
0.5
1
VIS (V)
FREQUENCY (Hz)
Figure 8. Differential Return Loss
Figure 9. RON vs. VIS
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8
1.5
2
NCN2612B
PARAMETER MEASUREMENT INFORMATION
Figure 10. Differential Insertion Loss (SDD21) and
Differential Return Loss (SDD11)
Figure 11. Differential Off Isolation (SDD21)
Figure 12. Differential Crosstalk (SDD21)
Figure 13. Bit−to−Bit and Channel−to−Channel Skew
tskew = |tPLH1-tPLH2| or |tPHL1-tPHL2|
Figure 14. tON and tOFF
Figure 16. On State Leakage
Figure 15. Off State Leakage
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9
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WQFN56 5x11, 0.5P
CASE 510AK−01
ISSUE A
SCALE 2:1
A B
D
ÉÉÉ
ÉÉÉ
ÉÉÉ
PIN ONE
LOCATION
L
DATE 02 MAR 2010
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L
L1
DETAIL A
ALTERNATE
CONSTRUCTIONS
E
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
ÉÉ
ÉÉ
EXPOSED Cu
MOLD CMPD
DETAIL B
0.15 C
ALTERNATE
CONSTRUCTION
TOP VIEW
0.15 C
DETAIL B
(A3)
0.10 C
0.08 C
SIDE VIEW
NOTE 4
A
A1
C
RECOMMENDED
SOLDERING FOOTPRINT
GENERIC
MARKING DIAGRAM*
5.30
XXXXXXXX
XXXXXXXX
AWLYYWWG
SEATING
PLANE
56X
0.63
2.50
0.10 C A B
D2
DETAIL A
56X
L
1
0.10 C A B
8.50
11.30
PKG
OUTLINE
1
0.50
PITCH
56
e
56X
e/2
BOTTOM VIEW
DOCUMENT NUMBER:
DESCRIPTION:
XXXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking. Pb−Free indicator, “G”, may
or not be present.
E2
K
MILLIMETERS
MIN
MAX
0.70
0.80
−−−
0.05
0.20 REF
0.20
0.30
5.00 BSC
2.30
2.50
11.00 BSC
8.30
8.50
0.50 BSC
0.20 MIN
0.30
0.50
−−−
0.15
b
0.10 C A B
0.05 C
56X
0.35
DIMENSIONS: MILLIMETERS
NOTE 3
98AON45390E
WQFN56 5x11, 0.5P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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