NCN4557
1.8 V/3.0 V Dual SIM/SAM/
Smart Card Power Supply
and Level Shifter
The NCN4557 is a dual interface analog circuit designed to
translate the voltages between SIM, SAM or Smart Cards and a
microcontroller (or similar control device). It integrates two LDOs
for power conversion and three level shifters per channel allowing
the management of two independent chip cards. The device fulfills
the ISO7816 and EMV smart card interface requirements as well as
the GSM and 3G mobile standard. Due to a built−in sequencer, the
device enables automatic activation and deactivation. Through the
ENABLE pin a low current shutdown mode can be activated
extending the battery life.
The card power supply voltage (1.8 V or 3.0 V) and the card socket
A or B are selected using two dedicated pins (SEL0 & SEL1).
Features
• Supports 1.8 V or 3.0 V Operating SIM/SAM/Smart Cards
• The LDOs are able to Supply more than 50 mA Under 1.8 V and
•
•
•
•
•
•
3.0 V
Built−in Active and Passive Pullup Resistor for I/O and
CRD_IOA/B Pins in Both Directions
All Pins are Fully ESD Protected According to ISO−7816
Specifications – ESD Protection on Card Pins in Excess of 8.0 kV
(JEDEC HBM)
Built−in Sequencer for Activation and Deactivation
Supports up to more than 5.0 MHz Clock
Very Compact Low−Profile 3x3 QFN−16 Package
These are Pb−Free Devices*
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MARKING
DIAGRAM
ÇÇÇ
ÇÇÇ
16
1
1
QFN16
MT SUFFIX
CASE 488AK
A
L
Y
W
G or G
NCN
4557
ALYWG
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
Applications
•
•
•
•
SIM Card Interface Circuit for 2G, 2.5G and 3G Mobile Phones
Wireless PC/Laptop Cards (PCMCIA Cards)
POS Terminals (SAM Card Interfaces)
Smart Card Readers
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques Reference
Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 0
1
Publication Order Number:
NCN4557/D
NCN4557
VDD
1.8 V to 5.5 V
VBAT
2.7 V to 5.5 V
0.1 mF
0.1 mF
1.8 V/3 V SIM/Smart Card
VCC
13
P3
VBAT
CRD_VCCA
ENABLE
CRD_RSTA
12 SEL0
11 SEL1
CRD_CLKA
CRD_I/OA
P0
10
8
3
4
RST
CLK
I/O
6
VCC
RST
CLK
C4
GND
Vpp
I/O
C8
5
6
7
8
5
7
1 mF
GND
17
1 mF
CRD_I/OB 14
CRD_CLKB 16
CRD_RSTB
GND
CARD B
15
4
3
2
1
CRD_VCCB 1
C4
CLK
RST
VCC
C8
I/O
Vpp
GND
8
7
6
5
1.8 V/3 V SIM/Smart Card
CRD_CLKB
CRD_RSTB
CRD_I/OB
ENABLE
Figure 1. Typical Interface Application
16
15
14
13
Exposed Pad (EP)
CRD_VCCB
1
12 SEL0
VDD
2
NCN4557
11 SEL1
VBAT
3
17
GND
10 CLK
CRD_VCCA
4
5
6
CRD_CLKA
CRD_RSTA
9
7
8
I/O
P1
9
4
CRD_I/OA
P2
1
2
VDD
NCN4557
MPU or Microcontroller
2
P4
CARD A
3
RST
Figure 2. QFN−16 Pinout (Top View)
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2
NCN4557
VBAT
3
CRD_VCCB 1
LDO B > 50 mA
LDO A > 50 mA
1.8 V/3.0 V/Enable
1.8 V/3.0 V/Enable
CRD_VCCB
4 CRD_VCCA
CRD_VCCA
CRD_CLKB 16
En
En
5 CRD_CLKA
CRD_RSTB 15
En
En
6 CRD_RSTA
CRD_I/OB 14
14 k
I/O
I/O
DATA DATA
I/O
En
DATA DATA
I/O
En
CRD_VCCB
7 CRD_I/OA
14 k
CRD_VCCA
CLK 10
13 ENABLE
CONTROL
LOGIC
12 SEL0
RST 9
MUX
I/O 8
11 SEL1
SEQUENCING
18 k
17 GROUND
VDD
VDD 2
GND
Figure 3. NCN4557 Block Diagram
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3
NCN4557
PIN DESCRIPTIONS
PIN
Name
Type
Description
1
CRD_VCCB
POWER
This pin is connected to the Card power supply pin (C1) (Card B).The corresponding LDO is
programmable using the pins SEL0, SEL1 and ENABLE to provide 1.8 V, 3.0 V or 0 V (disable).
CRD_VCCB can not be active when CRD_VCCA is active and conversely.
2
VDD
POWER
This pin is connected to the controller power supply. It configures the level shifter input stage to accept
the signal coming from the microcontroller. A 0.1 mF capacitor shall be used to bypass the power supply
voltage. When VDD is below 1.5 V typical CRD_VCCA and B are disabled; the NCN4557 comes into a
shutdown mode.
3
VBAT
POWER
DC/DC converter power supply input shared by the LDOs A & B. This pin has to be bypassed by a
0.1 mF capacitor.
4
CRD_VCCA
POWER
This pin is connected to the Card power supply pin (C1) (Card A).The corresponding LDO is
programmable using the pins SEL0, SEL1 and ENABLE to provide 1.8 V, 3.0 V or 0 V (disable).
CRD_VCCA can not be active when CRD_VCCB is active and conversely.
5
CRD_CLKA
OUTPUT
This pin is connected to the clock pin (C3) of the card connector A. The clock (CLK) signal comes from
the external clock generator (standalone clock source or microcontroller). The internal level shifter
adapts the voltage levels CLK to CRD_CLKA. An internal active pull− down NMOS device maintains this
pin to Ground during either the CRD_VCCA start−up sequence, or when CRD_VCCA = 0 V.
6
CRD_RSTA
OUTPUT
This pin is connected to the RESET pin (C2) of the card connector A. A level translator adapts the
RESET signal from the microcontroller to the external card A. The output current is internally limited to
15 mA max. Similarly to the CRD_CLK A or B pins this pin is maintained Low when CRD_VCCA = 0 V
and during the corresponding LDO transient phase of power−up.
7
CRD_I/OA
INPUT /
OUTPUT
This pin handles the connection to the serial I/O pin (C7) of the card connector A. A bidirectional level
translator adapts the serial I/O signal between the card and the micro−controller. A 14 kW (typical)
pull−up resistor provides a High Impedance state to the card I/O link; during the operating phase, a
dynamic pull−up circuit is activated making the CRD_I/OA rise time compliant with the ISO7816, EMV,
GSM and related standards. An internal active pull−down MOS device forces this pin to Ground during
either the CRD_VCCA start−up sequence or when CRD_VCCA = 0 V. The CRD_I/OA pin is internally
limited by a 15 mA max current.
8
I/O
INPUT /
OUTPUT
This pin is connected to an external microcontroller or cellular phone management unit (Baseband circuit
or PMU). A bidirectional level translator adapts the serial I/O signal between the smart card A or B and
the controller. Only one card, the selected card, communicates through the bidirectional I/O interface. A
built−in 18 kW typical resistor provides a high impedance state when the interface is not activated. An
additional dynamic pullup circuit accelerates the I/O rise time making the bidirectional channel perfectly
balanced in regards to the standard rise time requirements.
9
RST
INPUT
The RESET signal present at this pin is connected to the card through the internal level shifter which
translates the levels according to the CRD_VCCA or B programmed value.
10
CLK
INPUT
The clock signal, coming from the external controller, must have a Duty Cycle within the Min/Max values
defined by the specification (typically 50%). The built−in level shifter translates the input signal to the
external card CLK input.
11
SEL1
INPUT
SEL1 allows the selection of the Card A or B (Table 1).
SEL1 = Low ! Card A selected
SEL1 = High ! Card B selected
12
SEL0
INPUT
SEL0 allows programming CRD_VCCA or B (1.8 V or 3.0 V) (Table 1).
SEL0 = Low ! CRD_VCCA/B = 1.8 V
SEL0 = High ! CRD_VCCA/B = 3.0 V
13
ENABLE
INPUT
Power Up and Down pin:
ENABLE = Low ! Low current shutdown mode activated
ENABLE = High ! Normal Operation
A Low level on this pin switches off the card interface.
14
CRD_I/OB
INPUT /
OUTPUT
This pin handles the connection to the serial I/O pin (C7) of the card connector B. A bidirectional level
translator adapts the serial I/O signal between the card and the micro−controller. A 14 kW (typical)
pull−up resistor provides a High Impedance state to the card I/O link; during the operating phase a
dynamic pull−up circuit is activated making the CRD_I/OB rise time compliant with the ISO7816, EMV,
GSM and related standards. An internal active pulldown MOS device forces this pin to Ground during
either the CRD_VCCB start−up sequence or when CRD_VCCB = 0 V. The CRD_I/OB pin is internally
limited by a 15 mA maximum current.
15
CRD_RSTB
OUTPUT
This pin is connected to the RESET pin of the card connector B. A level translator adapts the RESET
signal from the microcontroller to the external card B. The output current is internally limited by a 15 mA
max current. Similarly to the CRD_CLK A or B pins this pin is maintained Low when CRD_VCCB = 0 V
and during the corresponding LDO transient phase of powerup.
16
CRD_CLKB
OUTPUT
This pin is connected to the clock pin (C3) of the card connector B. The clock (CLK) signal comes from
the external clock generator (standalone clock source or microcontroller). The internal level shifter
adapts the voltage levels CLK to CRD_CLKB. An internal active pull down NMOS device maintains this
pin to Ground during either the CRD_VCCB start−up sequence, or when CRD_VCCB = 0 V.
17
GND
GND
This pin number is the Exposed Pad which is the electrical Ground of the device. It must be soldered to
the PCB ground plane.
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NCN4557
ATTRIBUTES
Characteristics
Values
ESD protection
Human Body Model (HBM):
Card Pins (1, 4, 5, 6, 7, 14, 15 , 16 & 17) (Note 1)
All Other Pins (Note 1)
Machine Model (MM):
Card Pins (1, 4, 5, 6, 7, 14, 15 , 16 & 17)
All Other Pins
Charged Device Model (CDM):
Card Pins (1, 4, 5, 6, 7, 14, 15 , 16 & 17)
All Other Pins
Moisture sensitivity (Note 2)
Flammability Rating
QFN−16
Oxygen Index: 28 to 34
8 kV
2 kV
600 V
200 V
2 kV
400 V
Level 1
UL 94 V−0 @ 0.125 in
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. Human Body Model (HBM): R =1500 W, C = 100 pF.
2. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS
Rating
LDO Power Supply Voltage
Power Supply Microcontroller Side
External Card Power Supply
Digital Input Pins
Symbol
Value
Unit
VBAT
−0.5 ≤ VBAT ≤ 6
V
VDD
−0.5 ≤ VDD ≤ 6
V
CRD_VCC
−0.5 ≤ CRD_VCC ≤ 6
V
Vin
−0.5 ≤ Vin ≤ VDD + 0.5
but < 6.0
±5
V
Iin
Digital Output Pins
Vout
Iout
CRD Output Pins
Vout
CRD_I/O & CRD_RST Pins
CRD_CLK Pin
Iout
QFN−16 Low Profile package
Power Dissipation @ TA = +85°C
Thermal Resistance Junction−to−Air
−0.5 ≤ Vout ≤ VDD + 0.5
but < 6.0
± 10
−0.5 ≤ Vout ≤ CRD_VCC + 0.5
but < 6.0
15 (Internally Limited)
70 (Internally Limited)
mA
V
mA
V
mA
PD
RqJA
450
90
mW
°C/W
Operating Ambient Temperature Range
TA
−40 to +85
°C
Operating Junction Temperature Range
TJ
−40 to +125
°C
TJmax
+125
°C
Tstg
−65 to + 150
°C
Maximum Junction Temperature
Storage Temperature Range
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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5
NCN4557
POWER SUPPLY SECTION (−40°C to +85°C)
Pin
Symbol
Rating
Min
3
VBAT
Power Supply
3
IVBAT
Operating current
CRD_VCCA = 3.0 V, CRD_VCCB = 0 V, ICCA & B = 0 mA
CRD_VCCA = 1.8 V, CRD_VCCB = 0 V, ICCA & B = 0 mA
CRD_VCCA = 0 V, CRD_VCCB = 3.0 V, ICCA & B = 0 mA
CRD_VCCA = 0 V, CRD_VCCB = 1.8 V, ICCA & B = 0 mA
Typ
2.7
3
IVBAT_SD
2
VDD
Operating Voltage
2
IVDD
Operating Current (CLK & RST Low)
2
IVDD_SD
Shutdown Current – ENABLE = Low
2
VDD
1,4
1,4
Max
Unit
5.5
V
mA
26
25
26
25
80
80
80
80
3
mA
5.5
V
0.1
2
mA
0.05
1
mA
1.5
V
3.0
1.8
3.25
1.95
V
mA
Shutdown current – ENABLE = Low
1.8
Undervoltage Lockout
0.6
CRD_VCCA or B
3.0 V Mode, VBAT = 3.3 V to 5.5 V, ICRD_VCC = 0 mA to 50 mA
1.8 V Mode, VBAT = 2.7 V to 5.5 V, ICRD_VCC = 0 mA to 50 mA
2.75
1.65
ICRD_VCC_SC
Short –Circuit Current – CRD_VCC Shorted to GND, TA = 25°C
50
175
Channel Turn−on Time
ICCA or B = 0 mA, ENABLE rise edge to CRD_I/OA or B rise edge
0.8
2.5
7,13,14
ms
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating
temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are
applied individually under normal operating conditions and not valid simultaneously.
DIGITAL INPUT/OUTPUT SECTION CLK, RST, I/O, ENABLE, SEL0, SEL1 (−40°C to + 85°C)
Pin
Symbol
Rating
9,10
VIH
VIL
High Level Input Voltage (RST, CLK)
Low Level Input Voltage (RST, CLK)
11,12,13
VIH
VIL
9,10,11,
12,13
IIH, IIL
8
VOH_I/O
VOL_I/O
8
tR, tF
8
Rpu_I/O
Min
Max
Unit
0.85 * VDD
VDD
0.15 * VDD
V
High Level Input Voltage (ENABLE, SEL0, SEL1)
Low Level Input Voltage (ENABLE, SEL0, SEL1)
0.85 * VDD
VDD
0.15 * VDD
V
Input current (RST, CLK, ENABLE, SEL0, SEL1)
−1
1
mA
0.75 * VDD
VDD
0.3
V
0.8
ms
24
kW
High Level Output Voltage (CRD_ I/O = CRD_VCC, IOH_I/O=−20 mA)
Low Level Output Voltage (CRD_ I/O = 0 V, IOL_I/O = 500 mA)
Typ
Rise and Fall times (I/O), Cout = 30 pF
I/0 Pullup Resistor
12
18
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating
temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are
applied individually under normal operating conditions and not valid simultaneously.
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6
NCN4557
CARD INTERFACE SECTION (−40°C to +85°C)
Pin
Symbol
6,15
CRD_RSTA
CRD_RSTB
Rating
Min
CRD_VCC = +3 V
Output RESET VOH @ ICRD_rst = −20 mA
Output RESET VOL @ ICRD_rst = +200 mA
Output RESET Rise Time @ Cout = 30 pF
Output RESET Fall Time @ Cout = 30 pF
CRD_VCC = +1.8 V
Output RESET VOH @ ICRD_rst = −20 mA
Output RESET VOL @ ICRD_rst = +200 mA
Output RESET Rise Time @ Cout = 30 pF
Output RESET Fall Time @ Cout = 30 pF
5,16
CRD_CLKA
CRD_CLKB
CRD_VCC = +3 V
Output Duty Cycle
Max Output Frequency
Output VOH @ ICRD_clk = −20 mA
Output VOL @ ICRD_clk = +200 mA
Output CRD_CLK Rise Time @ Cout = 30 pF
Output CRD_CLK Fall Time @ Cout = 30 pF
CRD_VCC = +1.8 V
Output Duty Cycle
Max Output Frequency
Output VOH @ ICRD_clk = −20 mA
Output VOL @ ICRD_clk = +200 mA
Output CRD_CLK Rise Time @ Cout = 30 pF
Output CRD_CLK Fall Time @ Cout = 30 pF
7,14
CRD_I/OA
CRD_I/OB
Max
Unit
0.9 * CRD_VCC
0
CRD_VCC
0.3
0.8
0.8
V
V
ms
ms
0.9 * CRD_VCC
0
CRD_VCC
0.3
0.8
0.8
40
5
0.9 * CRD_VCC
0
60
CRD_VCC = +3 V
Output VOH @ ICRD_IO = −20 mA, VI/O =VDD
Output VOL @ ICRD_IO = +1 mA, VI/O = 0V
CRD_I/O Rise Time @ Cout = 30pF
CRD_I/O Fall Time @ Cout = 30 pF
Card I/O Pullup Resistor
V
V
ms
ms
%
MHz
V
V
ns
ns
CRD_VCC
0.3
18
18
%
MHz
V
V
ns
ns
0.8 * CRD_VCC
0
CRD_VCC
0.4
0.8
0.8
V
V
ms
ms
0.8 * CRD_VCC
0
CRD_VCC
0.3
0.8
0.8
V
V
ms
ms
4
15
mA
14
18
kW
Short−Circuit Current, VI/O = 0 V
Rpu_CRD_I/O
CRD_VCC
0.3
18
18
40
5
0.9 * CRD_VCC
0
CRD_VCC = +1.8 V
Output VOH @ ICRD_IO = −20 mA, VI/O = VDD
Output VOL @ ICRD_IO = +1 mA, VI/O = 0 V
CRD_I/O Rise Time @ Cout = 30 pF
CRD_I/O Fall Time @ Cout = 30 pF
8
Typ
10
60
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating
temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are
applied individually under normal operating conditions and not valid simultaneously.
3. All the dynamic specifications (AC specifications) are guaranteed by design over the operating temperature range.
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NCN4557
TYPICAL CHARACTERISTICS
30
1.2
1.0
28
−40°C
IBAT_SD (mA)
IBAT (mA)
Drop−out
26
CRD_VCCA/B = 3.0 V
24
CRD_VCCA/B = 1.8 V
22
25°C
0.8
0.6
85°C
0.4
0.2
20
0
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
2.7
3.1
3.5
3.9
4.3
4.7
5.1
VBAT (V)
VBAT (V)
Figure 4. IBAT Operating Current vs. VBAT,
TA = 25°C, ICC = 0 mA
Figure 5. IBAT Shutdown Current vs. VBAT
5.5
50
IVDD_SD (nA)
40
30
20
10
0
1.8 2.2
2.6
3.0
3.4
3.8
4.2
4.6
5.0
5.4
5.8
Y AXIS LABEL (UNIT)
Figure 7. Activation Sequence, Ch1 : CRD_VCC,
Ch2 : CRD_IO, Ch4 : CRD_RST, Ch3 : CRD_CLK
Figure 6. IVDD Shutdown Current vs. VDD,
TA = 25°C, VBAT = 5.5 V
Figure 8. Automatic Deactivation
Ch4: CRD_RST, Ch3: CRD_CLK, Ch2: CRD_IO,
Ch1: CRD_VCC
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8
NCN4557
APPLICATION INFORMATION
Card Supply Converter
The NCN4557 is a dual LDO−based DC/DC converter
and level shifter able to handle independently 2 smart card
interfaces. When one of these interfaces is operating the
other one is not active and conversely. Class B (3.0 V) and
C (1.8 V) cards can be used.
The Card and the CRD_VCC power supply are selected
using the pins SEL0, SEL1 and ENABLE according to
Table 1.
The built−it NCN4557 DC/DC converters are Low
Drop−Out Voltage Regulators capable to supply a current
in excess of 50 mA under 1.8 V or 3.0 V. These voltages are
selected according to Table 1. Using the Boolean input
ENABLE pin the NCN4557 device can be disabled setting
the circuit in a shutdown mode for which the power
consumption features values typically in the range of a few
tens of nA. Figure 9 shows a simplified view of the
NCN4557 voltage regulator. The CRD_VCC output is
internally current limited and protected against short
circuits. The short−circuit current IVCC varies with VBAT
typically in the range of 30 mA to 60 mA.
In order to guarantee a stable and satisfying operating of
the LDO the CRD_VCC output will be connected to a
1.0 mF bypass ceramic capacitor to the ground. At the
input, VBAT will be bypassed to the ground with a 0.1 mF
ceramic capacitor.
Table 1. CARD AND CRD_VCC SELECTION
ENABLE
SEL1
SEL0
Card# / CRD_VCC
1
0
0
Card A / 1.8 V
1
0
1
Card A / 3.0 V
1
1
0
Card B / 1.8 V
1
1
1
Card B / 3.0 V
0
X
X
A & B Disabled
VBAT
Q1
CRD_VCC
Ilim
R1
−
Cin = 0.1 mF
+
Cout = 1.0 mF
+
R2
Vref
ENABLE
GND
Figure 9. Simplified Block Diagram of the LDO
Voltage Regulator
Level Shifters
The level shifters accommodate the voltage difference
that might exist between the microcontroller and the smart
card. The RESET and CLOCK level shifters are
mono−directional and feature both the same architecture.
The bidirectional I/O line provides a way to
automatically adapt the voltage difference between the
controller and the card in both directions. In addition with
the pull−up resistor, a dynamic pullup circuit (Figure 10,
Q1 and Q2) provides a fast charge of the stray capacitance,
yielding a rise time fully within the ISO7816, EMV and
GSM specifications.
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NCN4557
CRD_VCC
VDD
Q1
Q2
18 k
14 k
200 ns
200 ns
I/O
CRD_I/O
GND
Q3
LOGIC
IO/CONTROL
GND
Figure 10. Basic I/O line Interface
The typical waveform provided in Figure 11 shows how
the accelerator operates. During the first 200 ns (typical),
the slope of the rise time is solely a function of the pullup
resistor associated with the stray capacitance. During this
period, the PMOS devices are not activated since the input
voltage is below their Vgs threshold. When the input slope
crosses the Vgsth, the opposite one shot is activated,
providing a low impedance to charge the capacitance, thus
increasing the rise time as depicted in Figure 11. The same
mechanism applies for the opposite side of the line to make
sure the system is optimum.
3.0 V). Figure 7 shows the typical NCN4557 activation
sequence.
About 800 ms after CRD_VCC has reached its nominal
voltage value, CRD_IO and CRD_RST are released.
CRD_CLK is enabled during the rising slope of the
second clock cycle after CRD_IO and CRD_RST are
enabled.
ENABLE
CRD_VCCA/B
CRD_IOA/B
CRD_RSTA/B
CRD_CLKA/B
TON ~ 0.9 ms
2nd Rise Edge After
CRD_IOA/B Rising
Figure 12. NCN4557 Power−Up
In all cases the application software is responsible for the
smart card signal sequence (contact activation sequence,
cold reset and warm reset sequences).
Figure 11. CRD_IO Typical Rise and Fall Times
with Stray Capacitance > 30 pF
(33 pF capacitor connected on the board)
Powerdown Sequence
The NCN4557 provides a powerdown sequence which is
activated by setting the ENABLE Boolean signal LOW.
The communication I/O session is terminated immediately
according to the ISO7816 and EMV specifications as
depicted in Figures 8 and 13.
ISO7816 Sequence:
• CRD_RST is forced to LOW
• CRD_CLK is forced to LOW 2 clock cycles after
ENABLE is set LOW unless CRD_CLK is already in
Powerup Sequence
The powerup sequence makes sure all the card−related
signals are LOW during the CRD_VCC positive going
slope. The Powerup sequence is activated by setting the
ENABLE Boolean signal HIGH. CRD_RST, CRD_CLK
and CRD_I/O are maintained LOW during the activation
stage until CRD_VCC reaches its nominal value (1.8 V or
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10
NCN4557
•
•
this state or 8 ms after the ENABLE pin is set LOW in
the other cases.
CRD_I/O is forced to LOW about 8 ms after the
ENABLE pin is set LOW.
Then CRD_VCC Supply Shuts Off
Shutdown Operating
In order to save power or for other purpose required by
the application it is possible to put the NCN4557 in a
shutdown mode by setting LOW the pin ENABLE. On the
other hand the device enters automatically in a shutdown
mode when VDD becomes lower than 1.0 V typically.
ESD Protection
ENABLE
The NCN4557 CRD interface features an Human Body
Model ESD voltage protection in excess of 8 kV for all the
CRD pins (CRD_IOA & B, CRD_CLKA & B,
CRD_RSTA & B, CRD_VCCA & B and GND). All the
other pins (microcontroller side) sustain at least 2 kV.
These values are guaranteed for the device in its full
integrity without considering the external capacitors added
to the circuit for a proper operating. Consequently in the
operating conditions it is able to sustain much more than
8 kV on its CRD pins making it perfectly protected against
electrostatic discharge well over the Human Body Model
ESD voltages required by the ISO7816 standard (4 kV).
CRD_RSTA/B
CRD_CLKA/B
CRD_IOA/B
CRD_VCCA/B
TOFF ~ 8.0 ms
Figure 13. NCN4557 Power Down Sequence
Input Schmitt Triggers
All the logic input pins (excepted I/O and CRD_I/O,
Figure 3) have built−in Schmitt trigger circuits to prevent
the NCN4557 against uncontrolled operation. The typical
dynamic characteristics of the related pins are depicted in
Figure 14.
Printed Circuit Board Layout
Careful layout routing will be applied to achieve a good
and efficient operating of the device in its mobile or
portable environment and fully exploit its performance.
The bypass capacitors have to be connected as close as
possible to the device pins (CRD_VCCA and B, VDD or
VBAT) in order to reduce as much as possible parasitic
behaviors (ripple and noise). It is recommended to use
ceramic capacitors.
The exposed pad of the QFN−16 package will be
connected to the ground. A relatively large ground plane is
recommended.
OUTPUT
VDD
ON
OFF
INPUT
0.2 x VDD 0.7 x VDD
or
0.4 V
Figure 14. Typical Schmitt Trigger Characteristics
ORDERING INFORMATION
Package
Shipping†
NCN4557MTG
QFN−16
(Pb−Free)
123 Units / Rail
NCN4557MTR2G
QFN−16
(Pb−Free)
3000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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11
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFN16 3*3*0.75 MM, 0.5 P
CASE 488AK−01
ISSUE O
DATE 13 SEP 2004
1
SCALE 2:1
D
PIN 1
LOCATION
ÇÇ
ÇÇ
0.15 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM
SPACING BETWEEN LEAD TIP AND FLAG.
A
B
E
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
TOP VIEW
0.15 C
(A3)
0.10 C
A
16 X
SEATING
PLANE
0.08 C
SIDE VIEW
A1
C
16X
L
16
1
5
8
4
16X
e
EXPOSED PAD
XXXX
XXXX
ALYW
9
E2
K
16
16X
XXXX
A
L
Y
W
12
1
13
b
0.10 C A B
0.05 C
GENERIC
MARKING DIAGRAM*
ÇÇ
ÇÇ
ÇÇ
D2
NOTE 5
MILLIMETERS
MIN
MAX
0.70
0.80
0.00
0.05
0.20 REF
0.18
0.30
3.00 BSC
1.65
1.85
3.00 BSC
1.65
1.85
0.50 BSC
0.20
−−−
0.30
0.50
BOTTOM VIEW
*This information is generic. Please refer
to device data sheet for actual part
marking. Pb−Free indicator, “G”, may
or not be present.
NOTE 3
DOCUMENT NUMBER:
DESCRIPTION:
98AON19612D
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
QFN16, 3*3*0.75 MM, 0.5 PITCH
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