NCN6000
Compact Smart Card
Interface IC
The NCN6000 is an integrated circuit dedicated to the smart card
interface applications. The device handles any type of smart card
through a simple and flexible microcontroller interface. On top of that,
due to the built−in chip select pin, several couplers can be connected in
parallel. The device is particularly suited for low cost, low power
applications, with high extended battery life coming from extremely
low quiescent current.
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MARKING
DIAGRAM
Features
20
• 100% Compatible with ISO7816−3 and EMV Standard
• Wide Battery Supply Voltage Range: 2.7 v Vbat v 6.0 V
• Programmable CRD_VCC Supply to Cope with either 3.0 V or 5.0 V
Card Operation
• Built−in DC−DC Converter Generates the CRD_VCC Supply with a
•
•
•
•
•
•
•
•
Single External Low Cost Inductor only, providing a High Efficiency
Power Conversion
Full Control of the Power Up/Down Sequence Yields High Signal
Integrity on both the Card I/O and the Signal Lines
Programmable Card Clock Generator
Built−in Chip Select Logic allows Parallel Coupling Operation
ESD Protection on Card Pins (8.0 kV, Human Body Model)
Fault Monitoring includes Vbatlow and Vcclow, providing Logic
Feedback to External CPU
Card Detection Programmable to Handle Positive or Negative
Going Input
Built−in Programmable CRD_CLK Stop Function Handles both
High or Low State
These are Pb−Free Devices**
Typical Application
• E−Commerce Interface
• ATM Smart Card
• Pay TV System
1
A = Assembly Location
L
= Wafer Lot
Y = Year
W = Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
A0 1
20 Vbat
A1 2
19 Lout_H
PGM 3
18 Lout_L
PWR_ON 4
17 PWR_GND
STATUS 5
16 GROUND
CS 6
15 CRD_VCC
RESET 7
14 CRD_IO
I/O 8
13 CRD_CLK
INT 9
12 CRD_RST
CLOCK_IN 10
11 CRD_DET
(Top View)
ORDERING INFORMATION
ISO/EMV
MICRO
CONTROLLER
NCN
6000
ALYWG
G
TSSOP−20
DTB SUFFIX
CASE 948E
1
NCN6000
SMART CARD
INTERFACE
Device
Package
Shipping †
NCN6000DTB
TSSOP−20*
75 Units / Rail
NCN6000DTBG
TSSOP−20*
75 Units / Rail
NCN6000DTBR2
TSSOP−20* 2500/Tape & Reel
NCN6000DTBR2G TSSOP−20* 2500/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
*This package is inherently Pb−Free.
Figure 1. Simplified Application
**For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
March, 2006 − Rev. 4
1
Publication Order Number:
NCN6000/D
NCN6000
+5 V
PB7
2
PB6
3
PB5
PB4
PB3
PB2
PB1
PB0
4
5
6
7
8
9
IRQ
10
MCU
20
A0
Vbat
A1
Lout_H
PGM
Lout_L
PWR_ON PWR_GND
STATUS
GROUND
CS
CRD_VCC
RESET
10 F
C1
U1
1
CRD_IO
I/O
CRD_CLK
INT
CRD_RST
XTAL
CLOCK_IN CRD_DET
GND
NCN6000
GND
19
L1
18
22 H
17
16
GND
15
C2
10 F
C3
100 nF
14
13
GND
17
18
12
8
11
4
3
2
1
GND
GND
5
7
Swb
C8
C4
CLK
RST
VCC
GND
I/O
VPP
J1
SMARTCARD
Figure 2. Typical Application
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2
GND
GND
Swa
ISO7816
VCC
NCN6000
+Vbat
+
−
Vbat_OK
20 Vbat
2.0 V
50 k
INT
9
500 k
Vbat
GND
11
Q
R
GND
+Vbat
CARD DETECTION
POLARITY
PROGRAMMABLE
50 k
CS
CRD_DET
50 s
Delay
S
STATUS INT
6
CLK STOP
PGM
3
A1
2
A0
1
Fout
DC−DC CONVERTER
DATA
SELECT
DECODER
1:16
VCC
CLOCK
15 CRD_VCC
19 Lout_H
3V/5V
Set_VCC
Power Down
Active Pwr_Down
1/1
1/2
1/4
1/8
CLOCK_IN 10
CLOCK
DIVIDER
18 Lout_L
GND
FAULT
17 PWR_GND
ON/OFF
STATUS INT
DC−DC STATUS
ENABLE VCC
CARD STATUS
PWR_ON
4
16 GROUND
LOGIC & CARD PINS SEQUENCER
SEQ 3
50 k
SEQ 2
SEQ 1
Vbat
STATUS
GND
5
Vbat
VCC
Vbat_OK
CLOCK
CLK_STOP
CLOCK
13 CRD_CLK
SEQ 2
2
A
GND
Vbat
1
20 k
Vbat_OK
I/O
20 k
SEQ 1
8
I/O
DATA
DATA
14 CRD_IO
I/O
1
RESET
7
2
Vbat
3
SEQ 3
PWR_ON
Figure 3. Block Diagram
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3
RESET
12 CRD_RST
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
H/L
H/L
L/H
H/L
2
3
4
5
6
7
4
8
9
10
11
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12
13
14
15
16
17
18
19
20
Z
Z
Z
Z
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
STATUS PGM RESET A1
1
H
L
H
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
A0
Z
Z
Z
Z
H
L
H
L
H
L
L
H
H
L
H
L
H
L
H
L
I/O
Program Chip
Normal Chip Operation
CARD PRESENT NO CARD DC−DC OK DC−DC OVERLOADED
Figure 4. Programming and Normal Operation Basic Timing
Read CRD_VCC status−> Low = CRD_VCC Low Voltage
Read STATUS = 1−>DC−DCOK/ = 0−> DC−DC Overloaded
Read Vbat status−> Low = Battery OK
CRD_DET = Normally Close
Read STATUS = 1−> Card Present/ = 0−> No Card
CRD_DET = Normally Close
CRD_DET = Normally Close
CRD_DET = Normally Open
Reserved
STOP CRD_CLKLow
STOP CRD_CLKHigh
5 V CLOCK_IN 1/8
ENABLE CRD_CLK
5 V CLOCK_IN 1/2
5 V CLOCK_IN 1/4
3 V CLOCK_IN 1/8
5 V CLOCK_IN 1/1
3 V CLOCK_IN 1/2
3 V CLOCK_IN 1/4
3 V CLOCK_IN 1/1
CS
I/O
A0
A1
RESET
PGM
STATUS
NCN6000
NCN6000
The programming can be achieved with the card powered
ON or OFF. The identification of the interrupt is carried out
by polling the STATUS pin, the Vbat voltage and the
DC−DC results being provided on the same pin as depicted
INTERRUPT
ACKNOWLEDGE
by the table in Figure 4. During the programming mode, the
PGM pin can be released to High since the mode is internally
latched by the Negative going transition presents on the Chip
Select pin.
CARD IDENTIFICATION
POLLING
50 s
CARD EXTRACTED
50 s
CRD_DET
INT
CS
PGM
High
A0
Low
A1
Low
STATUS
S1 CLEAR INTERRUPT
S2 CARD PRESENT: STATUS = 1
S3 CLEAR INTERRUPT
S4 CARD PRESENT: STATUS = 0
Figure 5. Interrupt Servicing and Card Polling
otherwise a Low is presented pin 5. The 50 s digital filter
is activated during both Insertion and Extraction of the card.
The MPU shall clear the INT line when the card has been
extracted, making the interrupt function available for other
purposes. However, neither the NCN6000 operation nor the
smart card I/O line or commands are affected by the state of
the INT pin.
On the other hand, clearing the INT and reading the
STATUS register can be performed by a single read by the
MPU: states S1 and S2 can be combined in a single
instruction, the same for S3 and S4.
When a card is either inserted or extracted, the CRD_DET
pin signal is debounced internally prior to pull the INT pin
to Low. The built−in logic circuit automatically
accommodates positive or negative input signal slope, on
both insertion and extraction state, depending upon the
polarity defined during the initialization sequence. The
default condition is Normally Open switch, negative going
card detection. The external CPU shall acknowledge the
request by forcing CS = L which, in turn, releases the INT
pin to High upon positive going of Chip Select (Table 4).
Polling the STATUS pin as depicted in Table 3 identifies the
active card. If a card is present, the STATUS returns High,
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5
NCN6000
ABBREVIATIONS
Lout_H
DC−DC External Inductor
Lout_L
DC−DC External Inductor
Cout
Output Capacitor
VCC
Card Power Supply Input
Icc
Current at CRD_VCC Pin
Class A
5.0 V Smart Card
Class B
3.0 V Smart Card
CS
Chip Select (from MPU)
Z
High Impedance Logic State
(according to ISO7816)
CRD_VCC
Interface IC Card Power Supply Output
CRD_CLK
Interface IC Card Clock Output
CRD_RST
Interface IC Card Reset Output
CRD_IO
Interface IC Card I/O Signal Line
CRD_DET
Interface IC Card Detection
ATR
Answer to Reset
PGM
Select Programming or Normal Operation
INT
Interrupt (to MPU)
tr
Rise Time
tf
Fall Time
td
Delay Time
ts
Storage Time
PIN FUNCTIONS AND DESCRIPTION
Pin
Name
Type
Description
1
A0
INPUT
This pin is combined with A1, PGM, RESET and I/O to program the chip mode of operation
and to read the data provided by STATUS. (Figures 4 and 5 and Tables 2 and 3)
2
A1
INPUT
This pin is combined with A0, PGM, RESET and I/O to program the chip mode of operation
and to read the data provided by STATUS. (Figures 4 and 5 and Tables 2 and 3)
3
PGM
INPUT
This pin is combined with A0, A1, RESET and I/O to program the chip mode of operation
and to read the data provided by STATUS. (Figures 4 and 5 and Tables 2 and 3)
4
PWR_ON
INPUT
Pull Down
This pin validates the operation of the internal DC−DC converter:
CS = L + PWR_ON = Negative going: DC−DC is OFF
CS = L + PWR_ON = Positive going: DC−DC is ON
Note: The PWR_ON bit must be combined with a Low state CS signal to activate
the function. (Table 2)
5
STATUS
OUTPUT
This pin provides logic state related to the card and NCN6000 status. According to the A0,
A1 and PGM logic state, this pin carries either the Card present status or the Vbat or the
DC−DC operation state. When PGM = L, STATUS is not affected, see Table 2.
6
CS
INPUT
Pull Up
This pin provides the NCN6000 chip select function. The PWR_ON, RESET, I/O, A0, A1 and
PGM signals are disabled when CS = H. When PGM = L and CS = L, the device jumps to
the programming mode (Figure 4 and Tables 1, 2 and 3). The Chip Select pin must be a
unique physical address when more than one card are controlled by a single MPU. The data
presented by the MPU are latched upon positive going edge of the Chip Select pin.
7
RESET
INPUT
Pull Down
This pin provides two modes of operation depending upon the logic state of PGM pin 3:
PGM = 1: The signal present at this pin is translated to pin 12 (card reset
signal) when CS = L and PWR_ON = H. It is latched when CS = H.
PGM = 0: The signal present on this pin is used as a logic input to program the
internal functions (Figure 5 and Tables 2 and 3).
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6
NCN6000
PIN FUNCTIONS AND DESCRIPTION (continued)
Pin
Name
Type
Description
8
I/O
Input/Output
Pull Up
This pin is connected to an external microcontroller interface. A bidirectional level translator
adapts the serial I/O signal between the smart card and the microcontroller. The level
translator is enabled when CS = L. The signal present on this pin is latched when CS = H.
This pin is also used in programming mode (Tables 1, 2 and 3, Figures 4 and 5).
9
INT
OUTPUT
Pull Down
This pin is activated LOW when a card has been inserted and detected by the interface or
when the NCN6000 reports Vbat or CRD_VCC status (See Table 6). The signal is reset to
a logic 1 on the rising edge of either CS or PWR_ON. The Collector open mode makes
possible the wired AND/OR external logic. When two or more interfaces share the INT
function with a single microcontroller, the software must poll the STATUS pin to identify the
origin of the interrupt (Figure 5).
10
CLOCK_IN
CLOCK INPUT
High Impedance
This pin can be connected to either the microcontroller master clock, or to any clock signal,
to drive the external smart cards. The signal is fed to internal clock selector circuit and
translated to the CRD_CLK pin at either the same frequency, or divided by 2 or 4 or 8,
depending upon the programming mode (Tables 1, 2 and 3).
Care must be observed, at PCB level, to minimize the pick−up noise coming from the
CLOCK_IN line. It is recommended to put a shield, built with a 10 mil copper track, around
this line and terminated to the GND.
11
CRD_DET
INPUT
The signal coming from the external card connector is used to detect the presence of the
card. A built−in pull up low current source makes this pin active LOW or HIGH, assuming
one side of the external switch is connected to ground. At Vbat start up, the default
condition is Normally Open switch, negative going insertion detection. The Normally
Closed switch, positive going insertion detection, can be defined by programming the
NCN6000 accordingly. In this case, the polarity must be set up during the first cycles of the
system initialization, otherwise an already inserted card will not be detected by the chip.
12
CRD_RST
OUTPUT
This pin is connected to the RESET pin of the card connector. A level translator adapts the
RESET signal from the microcontroller to the external card. The output current is internally
limited to 15 mA. The CRD_RST is validated when PWR_ON = H and PGM = H and hard
wired to Ground when the card is deactivated.
13
CRD_CLK
OUTPUT
This pin is connected to the CLK pin of the card connector. The CRD_CLK signal comes
from the clock selector circuit output. Combining A0, A1, PGM and I/O, as depicted in
Table 3 and Figure 3, programs the clock selection. This signal can be forced into a
standby mode with CRD_CLK either High or Low, depending upon the mode defined by
the programming sequence (Tables 1, 2 and 3 and Figure 4).
Care must be observed, at PCB level, to minimize the pick−up noise coming from the
CRD_CLK line. It is recommended to put a shield, built with a 10mil copper track, around
this line and terminated to the GND.
14
CRD_IO
I/O
This pin handles the connection to the serial I/O pin of the card connector. A bidirectional
level translator adapts the serial I/O signal between the card and the microcontroller. The
CRD_IO pin current is internally limited to 15 mA. A built−in register holds the previous
state presents on the I/O input pin.
15
CRD_VCC
POWER
This pin provides the power to the external card. It is the logic level “1” for CRD_IO,
CRD_RST and CRD_CLK signals. The energy stored by the DC−DC external inductor
Lout must be smoothed by a 10 F capacitor, associated with a 100 nF ceramic in parallel,
connected across CRD_VCC and GND. In the event of a CRD_VCC UVLOW voltage, the
NCN6000 detects the situation and feedback the information in the STATUS bit. The device
does not take any further action, particularly the DC−DC converter is neither stopped nor
reprogrammed by the NCN6000. It is up to the external MPU to handle the situation.
However, when the CRD_VCC is overloaded, the NCN6000 shut off the DC−DC converter,
pulls the INT pin Low and reports the fault in the STATUS register.
16
GROUND
SIGNAL
The logic and low level analog signals shall be connected to this ground pin. This pin must
be externally connected to the PWR_GND pin 17. The designer must make sure no high
current transients are shared with the low signal currents flowing into this pin.
17
PWR_GND
POWER
This pin is the Power Ground associated with the built−in DC−DC converter and must be
connected to the system ground together with GROUND pin 11. Using good quality ground
plane is recommended to avoid spikes on the logic signal lines.
18
Lout_L
POWER
The High Side of the external inductor is connected between this pin and Lout_H to provide
the DC−DC function. The built−in MOS devices provide the switching function together with
the CRD_VCC voltage rectification.
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7
NCN6000
PIN FUNCTIONS AND DESCRIPTION (continued)
Pin
Name
Type
Description
19
Lout_H
POWER
The High Side of the external inductor is connected between this pin and Lout_L to provide
the DC−DC function. The current flowing into this inductor is limited by a sense resistor
internally connected from Vbat/pin 20 and pin 19. Typically, Lout = 22H, with ESR
< 2.0 , for a nominal 55 mA output load.
20
Vbat
POWER
This pin is connected to the supply voltage and monitored by the NCN6000. The operation
is inhibited when Vbat is below the minimum 2.70 V value, followed by a PWR_DOWN
sequence and a Low STATUS state.
MAXIMUM RATINGS (Note 1)
Rating
Symbol
Value
Unit
Battery Supply Voltage
Vbat
7.0
V
Battery Supply Current (Note 2)
Ibat
300
mA
Power Supply Voltage
Vcc
6.0
V
Power Supply Current
Icc
"100
mA
Digital Input Pins
Vin
−0.5 V < Vin < Vbat +0.5 V,
but < 7.0 V
V
Iin
"5.0
mA
Digital Output Pins
Vout
−0.5 V < Vin < Vbat +0.5 V,
but < 7.0 V
V
Digital Output Pins
Iout
"10
mA
Card Interface Pins
Vcard
−0.5 V < Vcard < CRD_VCC +0.5 V
V
Card Interface Pins, except CRD_CLK
Icard
"15
mA
Inductor Current
ILout
300
mA
ESD Capability (Note 3)
Standard Pins
Card Interface Pins and CRD_DET
VESD
Digital Input Pins
kV
2.0
8.0
TSSOP−20 Package
Power Dissipation @ Tamb = +85°C
Thermal Resistance Junction to Air (Rja)
PDS
Rja
320
125
mW
°C/W
Operating Ambient Temperature Range
TA
−25 to +85
°C
Operating Junction Temperature Range
TJ
−25 to +125
°C
TJmax
+150
°C
Tsg
−65 to +150
°C
Maximum Junction Temperature (Note 4)
Storage Temperature Range
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at TA = +25°C.
2. This current represents the maximum peak current the pin can sustain, not the NCN6000 consumption (see Ibatop).
3. Human Body Model, R = 1500 , C = 100 pF.
4. Absolute Maximum Rating beyond which damage to the device may occur.
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8
NCN6000
POWER SUPPLY SECTION (−25°C to +85°C ambient temperature, unless otherwise noted.)
Rating
Symbol
Pin
Min
Typ
Max
Unit
Power Supply
Vbat
20
2.7
−
6.0
V
Standby Supply Current Conditions:
PWR_ON = L, STATUS = H, CLOCK_IN = H,
CS = H. All other logic inputs and outputs are open:
Vbat = 3.0 V
Vbat = 5.0 V
Ibatsb
20
DC Operating Current (Figure 19)
PWR_ON = H, CLOCK_IN = 0, CS = H, all CRD pins
unloaded
@ Vbat = 6.0 V, CRD_VCC = 5.0 V
@ Vbat = 3.6 V, CRD_VCC = 5.0 V
Ibatop
Vbat Undervoltage DetectionHigh
Vbat Undervoltage DetectionLow
Vbat Undervoltage DetectionHysteresis
VbatLH
VbatLL
VbatHY
20
Vcc
15
Output Card Supply Voltage @ Icc = 55 mA
@ 2.70 V vVbat v6.0 V
CRD_VCC = 3.0 V
CRD_VCC = 5.0 V
@ VbatLL < Vbat < 2.70 V
CRD_VCC = 5.0 V
Output Card Supply Peak Current @ Vcc = 5.0 V
@ CRD_VCC = 5.0 V
@ CRD_VCC = 3.0 V
@ Vbat = 3.6 V, CRD_VCC = 5.0 V, Tamb < 65°C
A
−
−
3.0
−
8.0
15
20
mA
−
−
7.0
2.0
−
5.0
2.1
2.0
−
−
−
100
2.7
2.6
−
V
VC3H
VC5H
2.75
4.75
−
−
3.25
5.25
VC5H
4.50
−
−
55
55
65
−
−
−
−
−
−
Iccp
V
V
mV
15
mA
Output Current Limit Time Out
tdoff
15
−
4.0
−
ms
Output Over Current Limit
Iccov
15
−
−
100
mA
Output Dynamic Peak Current @ CRD_VCC = 3.0 V
or 5.0 V, Cout = 10 F Ceramic XR7, Pulse Width
400 ns (Notes 5 and 6)
Iccd
15
100
−
−
mA
Battery Start−Up Current
@ CRD_VCC = 3.0 V, −25°C v TA v+ 85°C
@ CRD_VCC = 5.0 V, −25°CvTAv+ 85°C
Iccst
20
−
−
140
300
−
−
Output Card Supply Voltage Ripple @ Lout = 22 H,
Cout 1 = 10 F, Cout 2 = 100 nF, Vbat = 3.6 V
Iout = 55 mA
CRD_VCC = 5.0 V
(Note 5)
CRD_VCC = 3.0V
Vccrip
Output Card Supply Turn On Time @ Lout = 22 F,
Cout1 = 10 F, Cout2 = 100 nF, Vbat = 2.7 V,
CRD_VCC = 5.0 V
VccTON
Output Card Supply Shut Off Time @ Cout1 = 10 F,
Ceramic, Vbat = 2.7 V, CRD_VCC = 5.0 V,
VccOFF < 0.4 V
mA
15
mV
−
−
−
−
50
50
15
−
−
2.0
ms
VccTOFF
15
−
−
250
s
Fsw
18
−
600
−
kHz
Power Switch Drain/Source Resistor
RONS
18
−
1.9
2.2
Output Rectifier ON Resistor
ROND
15
−
2.8
3.4
DC−DC Converter Operating Frequency
5. Ceramic X7R, SMD types capacitors are mandatory to achieve the CRD_VCC specifications. When electrolytic capacitor is used, the
external filter must include a 100 nF, max 50 m ESR capacitor in parallel, to reduce both the high frequency noise and ripple to a minimum.
Depending upon the PCB layout, it might be necessary is to use two 6.8 F/10 V/ceramic/X7R//SMD1206 in parallel, yielding an improved
CRD_VCC ripple over the temperature range.
6. According to ISO7816−3, paragraph 4.3.2.
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9
NCN6000
DIGITAL PARAMETERS SECTION @ 2.70 VvVbatv6.0 V, NORMAL OPERATING MODE (−25°C to +85°C ambient
temperature, unless otherwise noted.) Note: Digital inputs undershoot < −0.30 V to ground, Digital inputs overshoot
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