NCN8025 / NCN8025A
Compact SMART CARD
Interface IC
The NCN8025 / NCN8025A is a compact and cost−effective single
smart card interface IC. It is dedicated for 1.8 V / 3.0 V / 5.0 V smart
card reader/writer applications. The card VCC supply is provided by a
built−in very low drop out and low noise LDO.
The device is fully compatible with the ISO 7816−3, EMV 4.3,
UICC and related standards including NDS and other STB standards
(Nagravision, Irdeto...). It satisfies the requirements specifying
conditional access into Set−Top−Boxes (STB) or Conditional Access
Modules (CAM and CAS).
This smart card interface IC is available in a QFN−24 package
(NCN8025A) providing all of the industry−standard features usually
required for STB smart card interface. It is also offered in a very
compact package profile, QFN−16 (NCN8025), satisfying the
requirements of cost−efficiency and space−saving requested by CAM
and SIM applications.
For details regarding device implementation refer to application
note AND8003/D, available upon request (please contact your local
ON Semiconductor sales office or representative).
Features
• Single IC Card Interface
• Fully Compatible with ISO 7816−3, EMV 4.3, UICC and Related
•
•
•
•
•
•
•
•
•
•
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MARKING
DIAGRAMS
1
QFN24
MN SUFFIX
CASE 485L
NCN
8025A
ALYWG
G
QFN16
MT SUFFIX
CASE 488AK
NCN
8025
ALYWG
G
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W = Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
Standards Including NDS and Other STB Standards (Nagravision,
ORDERING INFORMATION
Irdeto...)
See detailed ordering and shipping information in the package
3 Bidirectional Buffered I/O Level Shifters (C4, C7 and C8)
dimensions section on page 13 of this data sheet.
(QFN−24) − 1 Bidirectional I/O Level Shifter for the QFN−16
compact version
1.8 V, 3.0 V or 5.0 V $ 5 % Regulated Card Power Supply
Generation such as ICC v 70 mA
Regulator Power Supply: VDDP = 2.7 V to 5.5 V (@ 1.8 V),
3.0 V to 5.5 V (@ 3.0 V) & 4.85 V to 5.5 V (@ 5.0 V)
Independent Power Supply range on Controller
• Interrupt Signal INT for Card Presence and Faults
Interface such as VDD = 2.7 V to 5.5 V
• External Under−Voltage Lockout Threshold
Handles Class A, B and C Smart Cards
Adjustment on VDD (PORADJ Pin) (Except QFN−16)
Short Circuit Protection on all Card Pins
• Available in 2 Package Formats: QFN−24
(NCN8025A) and QFN−16 (NCN8025)
Support up to 27 MHz input Clock with Internal
• These are Pb−Free Devices
Division Ratio 1/1, 1/2, 1/4 and 1/8 through CLKDIV1
and CLKDIV2
Typical Application
ESD Protection on Card Pins up to +8 kV (Human
• Pay TV, Set Top Box Decoder with Conditional Access
Body Model)
and Pay−per−View
Activation / Deactivation Sequences (ISO7816
• Conditional Access Module (CAM / CAS)
Sequencer)
• SIM card interface applications (UICC / USIM)
Fault Protection Mechanisms Enabling Automatic
• Point Of Sales and Transaction Terminals
Device Deactivation in Case of Overload, Overheating,
• Electronic Payment and Identification
Card Take−off or Power Supply Drop−out (OCP, OTP,
UVP)
© Semiconductor Components Industries, LLC, 2016
October, 2016 − Rev. 5
1
Publication Order Number:
NCN8025/D
NCN8025 / NCN8025A
VDDP
10 uF
VDD
100 nF
VD D P
100 nF
VDD
INT
VDD
R1
PRES
PORADJ
SMART CARD
R2
PRES
NCN8025A
CONTROL
Host Controller
CMDVCC
VSEL0
VSEL1
CLKDIV1
100 nF
220 nF
CVCC
1
2
CRST
3
CCLK
4
CAUX1
CLKDIV2
DET
DET
VCC
GND
RST
VPP
CLK
C4
I/O
C8
NO
5
6
7
8
CAUX2
CI/O
CLKIN
DATA PORT
GND
GND
RSTIN
I/Ouc
GND
AUX1uc
AUX2uc
GND
GND
GND
GND
CLKDIV2
CLKDIV1
AUX2uc
AUX1uc
I/Ouc
21
20
19
18 CLKIN
NCN8025A
17 INT
VSEL0
I/Ouc
2
22
CLKDIV1
VDDP
23
CLKDIV2
1
24
VSEL1
VSEL0
VSEL1
Figure 1. Typical Smart Card Interface Application
16
15
14
13
1
NCN8025
PRES
3
25
16 GND
VDDP
2
PRES
4
Exposed Pad
15 VDD
PRES
3
10
11
12
CVCC
CMDVCC
7
8
CMDVCC
9
6
CVCC
8
5
CCLK
7
4
CRST
CI/O
13 PORADJ
CRST
6
CCLK
CAUX2
GND
14 RSTIN
GND
GND
5
CAUX1
CI/O
17
Exposed Pad
12
CLKIN
11
INT
10
VDD
9
RSTIN
Figure 2. NCN8025A − QFN−24 Pinout
Figure 3. NCN8025 − QFN−16 Pinout
(Top View)
(Top View)
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2
GND
NCN8025 / NCN8025A
VDD
15
GND
16
Supply Voltage
Monitoring
VDDP
2
PORADJ
13
VSEL0
1
VSEL1
24
CMDVCC
12
INT
17
CLKDIV1
22
CLKDIV2
23
CLKIN
18
RSTIN
14
I/Ouc
19
AUX1uc
20
AUX2uc
21
GND
25
Thermal
Control
1.8 V / 3 V / 5 V LDO
Control Logic
and
Fault Detection
Card
Detection
Card Pin Level Shifters & Drivers
ISO7816
Sequencer
Clock Divider
11
CVCC
3
PRES
4
PRES
9
CCLK
10
CRST
5
CIO
7
CAUX1
6
CAUX2
8
GND
Figure 4. NCN8025A Block Diagram (QFN−24 Pin Numbering)
PIN FUNCTION AND DESCRIPTION
Pin
(QFN24)
Pin
(QFN16)
Name
Type
1
1
VSEL0
Input
2
2
VDDP
Power
3
3
PRES
Input
Card presence pin active (card present) when PRES = Low. A built−in debounce timer of
about 8 ms is activated when a card is inserted. Convenient for Normally Open (NO)
Smart card connector.
4
−
PRES
Input
Card presence pin active (card present) when PRES = High. A built−in debounce timer of
about 8 ms is activated when a card is inserted. Convenient for Normally Closed (NC)
smart card connector.
5
4
CI/O
Input/
Output
This pin handles the connection to the serial I/O (C7) of the card connector. A
bi−directional level translator adapts the serial I/O signal between the card and the micro
controller. A 11 kW (typical) pull up resistor to CVCC provides a High impedance state for
the smart card I/O link.
Description
Allows selecting card VCC power supply voltage mode (5V/3V or 1.8V/3V)
VSEL0 = Low; CVCC = 5 V when VSEL1 = High or 3 V when VSEL1 = Low
VSEL0 = High; CVCC = 1.8 V when VSEL1 = High or 3 V when VSEL1 = Low
Regulator power supply.
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3
NCN8025 / NCN8025A
PIN FUNCTION AND DESCRIPTION
Pin
(QFN24)
Pin
(QFN16)
Name
Type
Description
6
−
CAUX2
Input/
Output
This pin handles the connection to the chip card’s serial auxiliary AUX2 I/O pin (C8). A
bi−directional level translator adapts the serial I/O signal between the card and the micro
controller. A 11 kW (typical) pull up resistor to CVCC provides a High impedance state for
the smart card C8 pin.
7
−
CAUX1
Input/
Output
This pin handles the connection to the chip card’s serial auxiliary AUX1 I/O pin (C4). A
bi−directional level translator adapts the serial I/O signal between the card and the micro
controller. A 11 kW (typical) pull up resistor to CVCC provides a High impedance state for
the smart card C4 pin.
8
−
GND
Ground
Card Ground
9
5
CCLK
Output
This pin is connected to the CLOCK card connector’s pin (Chip card’s pin C3). The Clock
signal comes from the CLKIN input through clock dividers and level shifter.
10
6
CRST
Output
This pin is connected to the chip card’s RESET pin (C2) through the card connector. A
level translator adapts the external Reset (RSTIN) signal to the smart card.
11
7
CVCC
Power
Output
This pin is connected to the smart card power supply pin (C1). An internal low dropout
regulator is programmable using the pins VSEL0 and VSEL1 to supply either 5 V or 3 V
or 1.8 V output voltage. An external distributed ceramic capacitor ranging from 80 nF to
1.2 mF recommended must be connected across CVCC and CGND. This set of capacitor
(if distributed) must be low ESR (< 100 mW).
12
8
CMDVCC
Input
Command VCC pin. Activation sequence Enable/Disable pin (active Low). The activation
sequence is enabled by toggling CMDVCC High to Low and when a card is present.
13
−
PORADJ
Input
Power−on reset threshold adjustment input pin for changing the reset threshold (VDD
UVLO threshold) thanks to an external resistor power divider. Needs to be connected to
ground when unused.
14
9
RSTIN
Input
This Reset input connected to the host and referred to VDD (microcontroller side), is
connected to the smart card Reset pin through the internal level shifter which translates
the level according to the CVCC programmed value.
15
10
VDD
Power
input
This pin is connected to the system controller power supply. It configures the level shifter
input stage to accept the signals coming from the controller. A 0.1 mF decoupling
capacitor shall be used. When VDD is below 2.30 V typical the card pins are disabled.
16
−
GND
Ground
Ground
17
11
INT
Output
The interrupt request is activated LOW on this pin. This is enabled when a card is present
and the card presence is detected by PRES or PRES pins. Similarly an interrupt is
generated when CVCC is overloaded. Inverter output (An open−drain output configuration
with 50 kW pull−up resistor is available under request (metal change)).
18
12
CLKIN
Input
19
13
I/Ouc
Input /
Output
This pin is connected to an external micro−controller. A bi−directional level translator
adapts the serial I/O signal between the smart card and the external controller. A built−in
constant 11 kW (typical) resistor provides a high impedance state.
20
−
AUX1uc
Input /
Output
This pin is connected to an external micro−controller. A bi−directional level translator
adapts the serial C4 signal between the smart card and the external controller. A built−in
constant 11 kW (typical) resistor provides a high impedance state.
21
−
AUX2uc
Input /
Output
This pin is connected to an external micro−controller. A bi−directional level translator
adapts the serial C8 signal between the smart card and the external controller. A built−in
constant 11 kW (typical) resistor provides a high impedance state.
22
14
CLKDIV1
Input
This pin coupled with CLKDIV2 is used to program the clock frequency division ratio
(Table 2).
23
15
CLKDIV2
Input
This pin coupled with CLKDIV1 is used to program the clock frequency division ratio
(Table 2).
24
16
VSEL1
Input
Allows selecting card VCC power supply voltage.
VSEL0 = Low: CVCC = 5 V when VSEL1 = High or 3 V when VSEL1 = Low.
VSEL0 = High: CVCC = 1.8 V when VSEL1 = High or 3 V when VSEL1 = Low.
25
17
GND
Ground
NOTE:
Clock Input for External Clock
Regulator Power Supply Ground
All information below refers to QFN−24 pin numbering unless otherwise noted. This information can be transposed to
the QFN−16 package according to the above “PIN FUNCTION AND DESCRIPTION” Table.
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4
NCN8025 / NCN8025A
ATTRIBUTES
Characteristics
Values
ESD protection
Human Body Model (HBM) (Note 1)
Card Pins (card interface pins 3−11)
All Other Pins
Machine Model (MM)
Card Pins (card interface pins 3−11)
All Other Pins
8 kV
2 kV
400 V
150 V
Moisture sensitivity (Note 2) QFN−24 and QFN−16
Level 1
Flammability Rating Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latch−up Test
1. Human Body Model (HBM), R = 1500 W, C = 100 pF.
2. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 3)
Rating
Symbol
Value
Unit
Regulator Power Supply Voltage
VDDP
−0.3 ≤ VDDP ≤ 5.5
V
Power Supply from Microcontroller Side
VDD
−0.3 ≤ VDD ≤ 5.5
V
CVCC
−0.3 ≤ CVCC ≤ 5.5
V
External Card Power Supply
Digital Input Pins
Vin
−0.3 ≤ Vin ≤ VDD
V
Digital Output Pins (I/Ouc, AUX1uc, AUX2uc, INT)
Vout
−0.3 ≤ Vout ≤ VDD
V
Smart card Output Pins
Vout
−0.3 ≤ Vout ≤ CVCC
V
RqJA
37
48
°C/W
Operating Ambient Temperature Range
TA
−40 to +85
°C
Operating Junction Temperature Range
TJ
−40 to +125
°C
TJmax
+125
°C
Tstg
−65 to + 150
°C
Thermal Resistance Junction−to−Air (Note 4)
QFN−24
QFN−16
Maximum Junction Temperature
Storage Temperature Range
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
3. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at TA = +25°C.
4. Exposed Pad (GND) must be connected to PCB.
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NCN8025 / NCN8025A
POWER SUPPLY SECTION (VDD = 3.3 V; VDDP = 5 V; Tamb = 25°C; FCLKIN = 10 MHz)
Symbol
VDDP
Parameter
Regulator Power Supply,
CVCC = 5.0 V,
|ICC| ≤ 70 mA (EMV Conditions)
|ICC| ≤ 70 mA (NDS Conditions)
CVCC = 3.0 V,
|ICC| ≤ 70 mA
CVCC = 1.8 V,
|ICC| ≤ 70 mA
Min
Typ
Max
4.75
4.85
3.0
2.7
5.0
5.0
5.5
5.5
5.5
5.5
Unit
V
IDDP
Inactive mode (CMDVCC = High)
−
−
1
mA
IDDP
DC Operating supply current, FCLKIN = 10 MHz, CoutCCLK = 33 pF, |ICVCC| = 0
(CMDVCC = Low)
−
−
3.0
mA
IDDP
DC Operating supply current,
CVCC = 5 V, ICVCC = 70 mA
CVCC = 3 V, ICVCC = 70 mA
CVCC = 1.8 V, ICVCC = 70 mA
−
−
−
−
−
−
150
150
150
2.7
−
5.5
mA
VDD
Operating Voltage
IVDD
Inactive mode − standby current (CMDVCC = High)
−
−
60
mA
IVDD
Operating Current − FCLK_IN = 10 MHz , CoutCCLK = 33 pF |ICVCC| = 0 (CMDVCC =
Low)
−
−
1
mA
2.20
2.30
2.40
50
100
180
mV
UVLOVDD
UVLOHys
Under Voltage Lock−Out (UVLO), no external resistor at pin PORADJ
(connected to GND), falling VDD level
UVLO Hysteresis, no external resistor at pin PORADJ (Connected to GND)
V
V
PORADJ pin
VPORth+
External Rising threshold voltage on VDD for Power On Reset − pin PORADJ
1.20
1.27
1.34
V
VPORth−
External Falling threshold voltage on VDD for Power On Reset − pin PORADJ
1.15
1.20
1.28
V
VPORHys
Hysteresis on VPORth (pin PORADJ)
30
80
100
mV
Width of Power−On Reset pulse (Note 5)
No external resistor on PORADJ
External resistor on PORADJ
4
4
8
8
12
12
ms
ms
tPOR
IIL
Low level input leakage current, VIL < 0.5 V (Pull−down source current)
mA
5
Low Dropout Regulator
CCVCC
Output Capacitance on card power supply CVCC (Note 6)
0.08
0.32
1.2
mF
CVCC
Output Card Supply Voltage (including ripple)
1.8 V CVCC mode @ ICC ≤ 70 mA
3.0 V CVCC mode @ ICC ≤ 70 mA
5.0 V CVCC mode @ ICC ≤ 70 mA with 4.85 V ≤ VDDP ≤ 5.5 V (NDS)
5.0 V CVCC mode @ ICC ≤ 70 mA with 4.75 V ≤ VDDP ≤ 5.5 V (EMV)
1.70
2.85
4.75
4.60
1.80
3.00
5.00
5.00
1.90
3.15
5.25
5.25
V
V
V
1.66
1.80
1.90
V
2.70
3.00
3.30
V
4.60
5.00
5.30
V
CVCC
ICVCC
Current pulses 15 nAs (t < 400 ns & |ICC| < 100 mA peak) (Note 5)
1.8 V mode / Ripple v 250 mV (2.7 V v VDDP v 5.5 V)
Current pulses 40 nAs (t < 400 ns & |ICC| < 200 mA peak)
3.0 V mode / Ripple v 250 mV (2.9 V v VDDP v 5.5 V)
Current pulses 40 nAs (t < 400 ns & |ICC| < 200 mA peak)
5.0 V mode / Ripple v 250 mV (4.85 V v VDDP v 5.5 V)
Card Supply Current
@ CVCC = 1.8 V
@ CVCC = 3.0 V
@ CVCC = 5.0 V
mA
70
70
70
ICVCC_SC
Short −Circuit Current − CVCC shorted to ground
DVCVCC
CVCCSR
120
150
mA
Output Card Supply Voltage Ripple peak−to−peak − fripple = 100 Hz to 200 MHz (load
transient frequency with 65 mA peak current and 50% Duty Cycle) (Note 5)
300
mV
Slew Rate on CVCC turn−on / turn−off (Note 5)
0.22
V/ms
5. Guaranteed by design and characterization.
6. These values take into account the tolerance of the cms capacitor used. CMS capacitor very low ESR (< 100 mW, X5R / X7R).
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6
NCN8025 / NCN8025A
HOST INTERFACE SECTION CLKIN, RSTIN, I/Ouc, AUX1uc, AUX2uc, CLKDIV1, CLKDIV2, CMDVCC, VSEL0, VSEL1 (VDD =
3.3 V; VDDP = 5 V; Tamb = 25°C; FCLKIN = 10 MHz)
Symbol
FCLKIN
Parameter
Clock frequency on pin CLKIN (Note 7)
Min
Typ
Max
Unit
−
−
27
MHz
VIL
Input Voltage level Low: CLKIN, RSTIN, CLKDIV1, CLKDIV2, CMDVCC, VSEL0,
VSEL1
−0.3
−
0.3 x VDD
V
VIH
Input Voltage level High: CLKIN, RSTIN, CLKDIV1, CLKDIV2, CMDVCC, VSEL0,
VSEL1
0.7 x VDD
−
VDD + 0.3
V
|IIL|
CLKDIV1, CLKDIV2, CMDVCC, RSTIN, CLKIN, VSEL0, VSEL1 Low Level Input
Leakage Current, VIL = 0 V
−
−
1
mA
|IIH|
CLKDIV1, CLKDIV2, CMDVCC, RSTIN, CLKIN, VSEL0, VSEL1 Low Level Input
Leakage Current, VIH = VDD
−
−
1
mA
VIL
Input Voltage level Low: I/Ouc, AUX1uc, AUX2uc
−0.3
0.5
V
0.7 x VDD
VIH
Input Voltage level High: I/Ouc, AUX1uc, AUX2uc
VDD + 0.3
V
|IIL |
I/Ouc, AUX1uc, AUX2uc Low level input leakage current, VIL = 0 V
−
−
600
mA
|IIH|
I/Ouc, AUX1uc, AUX2uc High level input leakage current, VIH = VDD
−
−
10
mA
VOH
I/Ouc, AUX1uc, AUX2uc data channels, @ Cs v 30 pF
High Level Output Voltage (CRD_I/O = CAUX1 = CAUX2 = CVCC)
IOH = −40 mA for VDD > 2 V (IOH = −20 mA for VDD v 2 V)
0.75 x VDD
−
VDD + 0.1
V
Low Level Output Voltage (CRD_I/O = CAUX1 = CAUX2 = 0 V)
IOL= + 1 mA
0
−
0.3
V
tRi/Fi
Input Rising/Falling times (Note 7)
−
−
1.2
ms
tRo/Fo
Output Rising/Falling times (Note 7)
−
−
0.1
ms
Rpu
I/0uc, AUX1uc, AUX2uc Pull Up Resistor
8
11
16
kW
VOH
Output High Voltage
INT @ IOH = −15 mA (source)
0.75 x VDD
−
−
Output Low Voltage
INT @ IOL = 2 mA (sink)
0
−
0.30
INT Pull Up Resistor (open−drain output configuration option) (Note 8)
40
50
60
VOL
VOL
RINT
V
V
7. Guaranteed by design and characterization.
8. Option available under request (metal change). The current option is an inverter−like output.
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7
kW
NCN8025 / NCN8025A
SMART CARD INTERFACE SECTION CI/O, CAUX1, CAUX2, CCLK, CRST, PRES, PRES (VDD = 3.3 V; VDDP = 5 V; Tamb = 25°C;
FCLKIN = 10 MHz)
Symbol
VOH
VOL
tR
tF
tR/F
td
Parameter
Min
Typ
Max
Unit
0.9 x CVCC
0
−
−
CVCC
0.20
V
V
−
−
−
−
−
−
100
100
200
ns
ns
ns
−
−
2
ms
−
−
27
MHz
0.9 x CVCC
0
−
−
CVCC
+0.2
V
V
45
−
55
%
−
−
−
−
16
16
ns
ns
0.2
−
−
V/ns
Input Voltage High Level
1.8 V Mode
3.0 V Mode
5.0 V Mode
1.0
1.6
2.3
−
−
−
CVCC + 0.3
CVCC + 0.3
CVCC + 0.3
V
V
V
Input Voltage Low Level
1.8 V mode
3.0 V mode
5.0 V mode
−0.30
−0.30
−0.30
−
−
−
0.50
0.80
1.00
V
V
V
600
10
mA
mA
CRST @ CVCC = 1.8 V, 3.0 V, 5.0 V
Output RESET VOH @ Irst = −200 mA
Output RESET VOL @ Irst = 200 mA
Output RESET Rise time @ Cout = 100 pF (Note 9)
Output RESET Fall time @ Cout = 100 pF (Note 9)
Output Rise/Fall times @ CVCC = 1.8 V & Cout = 100 pF (Note 9)
RSTIN to CRST delay − Reset enabled (Note 9)
CCLK @ CVCC = 1.8 V, 3.0 V or 5.0 V
FCRDCLK
Output Frequency (Note 9)
VOH
VOL
Output CCLK VOH @ Iclk = −200 mA
Output CCLK VOL @ Iclk = 200 mA
FDC
Output Duty Cycle (Note 9)
trills
tulsa
Rise & Fall time
Output CCLK Rise time @ Cout = 33 pF (Note 9)
Output CCLK Fall time @ Cout = 33 pF (Note 9)
SR
Slew Rate @ Cout = 33 pF (CVCC = 3.0 V or 5.0 V) (Note 9)
CAUX1, CAUX2, CI/O @ CVCC = 1.8 V, 3.0 V, 5.0 V
VIH
VIL
|IIL|
|IIH|
Low Level Input current VIL = 0 V
High Level Input current VIH = CVCC
VOH
Output VOH
@ IOH = −40 mA for CVCC = 3.0 V and 5.0 V
@ IOH = −20 mA for CVCC = 1.8 V
VOL
−
−
Output VOL
@ IOL = 1 mA, VIL = 0 V for CVCC = 1.8 V
@ IOL = 1 mA, VIL = 0 V for CVCC = 3.0 V and 5.0 V
0.8 x CVCC
0.8 x CVCC
−
−
CVCC + 0.1
CVCC + 0.1
V
V
0
0
−
−
0.27
0.30
V
V
tRi / Fi
Input Rising/Falling times (Note 9)
−
−
1.2
ms
tRo / Fo
Output Rising/Falling times / Cout = 80 pF (Note 9)
−
−
0.1
ms
Fbidi
Maximum data rate through bidirectional I/O, AUX1 & AUX2 channels (Note 9)
−
−
1
MHz
RPU
CAUX1, CAUX2, CI/O Pull− Up Resistor
8
11
16
kW
tIO
Propagation delay IOuc −> CI/O and CI/O −> IOuc (falling edge) (Note 9)
−
−
200
ns
tpu
Active pull−up pulse width buffers I/O, AUX1 and AUX2 (Note 9)
−
−
200
ns
Cin
Input Capacitance on data channels
−
−
10
pF
VIH
VIL
PRES, PRES
Card Presence Voltage High Level
Card Presence Voltage Low Level
0.7 x VDD
−0.3
−
−
VDD + 0.3
0.3 x VDD
V
www.onsemi.com
8
NCN8025 / NCN8025A
SMART CARD INTERFACE SECTION CI/O, CAUX1, CAUX2, CCLK, CRST, PRES, PRES (VDD = 3.3 V; VDDP = 5 V; Tamb = 25°C;
FCLKIN = 10 MHz)
Symbol
|IIH|
|IIL|
Tdebounce
Parameter
Min
Typ
Max
Unit
mA
PRES, PRES
High level input leakage current, VIH = VDD
PRES
PRES
Low level input leakage current, VIL = 0 V
PRES
PRES
5
10
1
5
1
10
Debounce time PRES and PRES (Note 9)
5
8
12
ms
ICI/O
CI/O, CAUX1, CAUX2 current limitation
−
−
15
mA
ICCLK
CCLK current limitation
−
−
70
mA
ICRST
CRST current limitation
−
−
20
mA
Tact
Activation Time (Note 9)
30
−
100
ms
Deactivation Time (Note 9)
30
−
250
ms
Shutdown temperature (Note 9)
−
150
−
°C
Tdeact
TempSD
9. Guaranteed by design and characterization.
POWER SUPPLY
VSEL1 are usually programmed before activating the smart
card interface that is when /CMDVCC is High.
There’s no specific sequence for applying VDD or VDDP.
They can be applied to the interface in any sequence. After
powering the device INT pin remains Low until a card is
inserted.
The NCN8025 / NCN8025A smart card interface has two
power supplies: VDD and VDDP.
VDD is common to the system controller and the interface.
The applied VDD range can go from 2.7 V up to 5.5 V. If VDD
goes below 2.30 V typical (UVLOVDD) a power−down
sequence is automatically performed. In that case the
interrupt (INT) pin is set Low.
A Low Drop−Out (LDO) and low noise regulator is used
to provide the 1.8 V, 3 V or 5 V power supply voltage
(CVCC) to the card. VDDP is the LDO’s input voltage.
CVCC is the LDO output. The typical distributed reservoir
output capacitor connected to CVCC is 100 nF + 220 nF. The
capacitor of 100 nF is connected as close as possible to the
CVCC’s pin and the 220 nF one as close as possible to the
card connector C1 pin. Both feature very low ESR values
(lower than 50 mW). The decoupling capacitors on VDD and
VDDP respectively 100 nF and 10 mF + 100 nF have also to
be connected close to the respective IC pins.
The CVCC pin can source up to 70 mA at 1.8 V, 3 V and
5 V continuously over the VDDP range (see corresponding
specification table), the absolute maximum current being
internally limited below 150 mA (Typical at 120 mA).
The card VCC voltage (CVCC) can be programmed with
the pins VSEL0 and VSEL1 and according to the below table:
SUPPLY VOLTAGE MONITORING
The supply voltage monitoring block includes the
Power−On Reset (POR) circuitry and the under−voltage
lockout (UVLO) detection (VDD voltage dropout
detection). PORADJ pin allows the user, according to the
considered application, to adjust the VDD UVLO threshold.
If not used PORADJ pin is connected to Ground
(recommended even if it may be left unconnected).
The input supply voltage is continuously monitored to
prevent under voltage operation. At power up, the system
initializes the internal logic during POR timing and no further
signal can be provided or supported during this period.
The system is ready to operate when the input voltage has
reached the minimum VDD. Considering this, the NCN8025
/ NCN8025A will detect an Under−Voltage situation when
the input supply voltage will drop below 2.30 V typical.
When VDD goes down below the UVLO falling threshold a
deactivation sequence is performed.
The device is inactive during power−on and power−off of
the VDD supply (8 ms reset pulse).
PORADJ pin is used to modify the UVLO threshold
according to the below relationship considering an external
resistor divider R1 / R2 (see block diagram Figure 1):
Table 1. CVCC PROGRAMMING
VSEL0
VSEL1
CVCC
0
0
3.0 V
0
1
5.0 V
1
0
3.0 V
1
1
1.8 V
UVLO +
R1 ) R2
V POR
R2
(eq. 1)
If PORADJ is connected to Ground the VDD UVLO
threshold (VDD falling) is typically 2.30 V. In some cases it
can be interesting to adjust this threshold at a higher value
and by the way increase the VDD supply dropout detection
VSEL0 can be used to select the CVCC programming
mode which can be 5V/3V (VSEL0 connected to Ground)
or 1.8V/3V (VSEL0 connected to VDD). VSEL0 and
www.onsemi.com
9
NCN8025 / NCN8025A
The current to and from the card I/O lines is limited
internally to 15 mA and the maximum guaranteed frequency
on these lines is 1 MHz.
level which enables a deactivation sequence if the VDD
voltage is too low.
For example, there are microcontrollers for which the
minimum supply voltage insuring a correct operating is
higher than 2.6 V; increasing UVLOVDD (VDD falling) is
consequently necessary. Considering for instance a resistor
bridge with R1 = 56 kW, R2 = 42 kW and VPOR− = 1.27 V
typical the VDD dropout detection level can be increased up
to:
UVLO +
56k ) 42k
42k
V POR− + 2.96 V
STANDBY MODE
After a Power−on reset, the circuit enters the standby mode.
A minimum number of circuits are active while waiting for
the microcontroller to start a session:
− All card contacts are inactive
− Pins I/Ouc, AUX1uc and AUX2uc are in the
high−impedance state (11 kW pull−up resistor to VDD)
− Card pins are inactive and pulled Low
− Supply Voltage monitoring is active
(eq. 2)
CLOCK DIVIDER:
The input clock can be divided by 1/1, 1/2, 1/4, or 1/8,
depending upon the specific application, prior to be applied
to the smart card driver. These division ratios are
programmed using pins CLKDIV1 and CLKDIV2 (see
Table 2). The input clock is provided externally to pin
CLKIN.
POWER−UP
In the standby mode the microcontroller can check the
presence of a card using the signals INT and CMDVCC as
shown in Table 3:
Table 3. CARD PRESENCE STATE
Table 2. CLOCK FREQUENCY PROGRAMMING
CLKDIV1
CLKDIV2
FCCLK
0
0
CLKIN / 8
0
1
CKLKIN / 4
1
0
CLKIN
1
1
CLKIN / 2
INT
CMDVCC
State
HIGH
HIGH
Card present
LOW
HIGH
Card not present
If a card is detected present (PRES or PRES active) the
controller can start a card session by pulling CMDVCC
Low. Card activation is run (t0, Figure 6). This Power−Up
Sequence makes sure all the card related signals are LOW
during the CVCC positive going slope. These lines are
validated when CVCC is stable and above the minimum
voltage specified. When the CVCC voltage reaches the
programmed value (1.8 V, 3.0 V or 5.0 V), the circuit
activates the card signals according to the following
sequence (Figure 6):
− CVCC is powered−up at its nominal value (t1)
− I/O, AUX1 and AUX2 lines are activated (t2)
− Then Clock is activated and the clock signal is applied
to the card (typically 500 ns after I/Os lines) (t3)
− Finally the Reset level shifter is enabled (typically
500 ns after clock channel) (t4)
The clock can also be applied to the card using a RSTIN
mode allowing controlling the clock starting by setting
RSTIN Low (Figure 5). Before running the activation
sequence, that is before setting Low CMDVCC RSTIN is set
High. The following sequence is applied:
− The Smart Card Interface is enable by setting
CMDVCC LOW (RSTIN is High).
− Between t2 (Figure 5) and t5 = 200 ms, RSTIN is reset
to LOW and CCLK will start precisely at this moment
allowing a precise count of clock cycles before toggling
CRST Low to High for ATR (Answer To Reset)
request.
− CRST remains LOW until 200 ms; after t5 = 200 ms
CRST is enabled and is the copy of RSTIN which has
no more control on the clock.
The clock input stage (CLKIN) can handle a 27 MHz
maximum frequency signal. Of course, the ratio must be
defined by the user to cope with Smart Card considered in
a given application
In order to avoid any duty cycle out of the 45% / 55%
range specification, the divider is synchronized by the last
flip flop, thus yielding a constant 50% duty cycle, whatever
be the divider ratio 1/2, 1/4 or 1/8. On the other hand, the
output signal Duty Cycle cannot be guaranteed 50% if the
division ratio is 1 and if the input Duty Cycle signal is not
within the 46% − 56% range at the CLKIN input.
When the signal applied to CLKIN is coming from the
external controller, the clock will be applied to the card
under the control of the microcontroller or similar device
after the activation sequence has been completed.
DATA I/O, AUX1 and AUX2 LEVEL SHIFTERS
The three bidirectional level shifters I/O, AUX1 and
AUX2 adapt the voltage difference that might exist between
the micro−controller and the smart card. These three
channels are identical. The first side of the bidirectional
level shifter dropping Low (falling edge) becomes the driver
side until the level shifter enters again in the idle state pulling
High CI/O and I/Ouc.
Passive 11 kW pull−up resistors have been internally
integrated on each terminal of the bidirectional channel. In
addition with these pull−up resistors, an active pull−up
circuit provides a fast charge of the stray capacitance.
www.onsemi.com
10
NCN8025 / NCN8025A
sequencing internally defined but at the end the actual
activation sequencing is the responsibility of the application
software and can be redefined by the micro−controller to
comply with the different standards and the different ways
the standards manage this activation (for example light
differences exist between the EMV and the ISO7816
standards).
If controlling the clock with RSTIN is not necessary
(Normal Mode), then CMDVCC can be set LOW with
RSTIN LOW. In that case, CLK will start minimum 500 ns
after the transition on I/O (Figure 6), and to obtain an ATR,
CRST can be set High by RSTIN also about 500 ns after the
clock channel activation (Tact).
The internal activation sequence activates the different
channels according to a specific hardware built−in
CMDVCC
CVCC
CIO
ATR
CCLK
RSTIN
CRST
t0
t1 t2
t4
t5
~200 ms
Figure 5. Activation Sequence − RSTIN Mode (RSTIN Starting High)
CMDVCC
CVCC
CIO
ATR
CCLK
RSTIN
CRST
t0
t1 t2 t3
t4
Tact
Figure 6. Activation Sequence − Normal Mode
www.onsemi.com
11
NCN8025 / NCN8025A
POWER−DOWN
−
−
−
−
When the communication session is completed the
NCN8025 / NCN8025A runs a deactivation sequence by
setting High CMDVCC. The below power down sequence
is executed:
CRST is forced to Low
CCLK is set Low 12 ms after CRST.
CI/O, CAUX1 and CAUX2 are pulled Low
Finally CVCC supply can be shut−off.
CMDVCC
CRST
CCLK
CIO
CVCC
Tdeact
Figure 7. Deactivation Sequence
FAULT DETECTION
− DC/DC operation: the internal circuit continuously
senses the CVCC voltage (in the case of either over or
under voltage situation).
− DC/DC operation: under−voltage detection on VDDP
− Overheating
− Card pin current limitation: in the case of a short circuit
to ground. No feedback is provided to the external
MPU.
In order to protect both the interface and the external smart
card, the NCN8025 / NCN8025A provides security features
to prevent failures or damages as depicted here after.
− Card extraction detection
− VDD under voltage detection
− Short−circuit or overload on CVCC
PRES
/INT
CMDVCC
debounce
debounce
CVCC
Powerdown resulting
of card extraction
Powerdown caused
by short−circuit
Figure 8. Fault Detection and Interrupt Management
Interrupt Pin Management:
increases again over the UVLO limit (including hysteresis),
a card being still present.
During a card session, CMDVCC is Low and INT pin
goes Low when a fault is detected. In that case a deactivation
is immediately and automatically performed (see Figure 7).
When the microcontroller resets CMDVCC to High it can
sense the INT level again after having got completed the
deactivation.
A card session is opened by toggling CMDVCC High to
Low.
Before a card session, CMDVCC is supposed to be in a
High position. INT is Low if no card is present in the card
connector (Normally open or normally closed type). INT is
High if a card is present. If a card is inserted (INT = High)
and if VDD drops below the UVLO threshold then INT pin
drops Low immediately. It switches High when VDD
www.onsemi.com
12
NCN8025 / NCN8025A
As illustrated by Figure 8 the device has a debounce timer
of 8 ms typical duration. When a card is inserted, output INT
goes High only at the end of the debounce time. When the
card is removed a deactivation sequence is automatically
and immediately performed and INT goes Low.
in structures have been designed to handle either 2 kV, when
related to the micro controller side, or 8 kV when connected
with the external contacts (HBM model). Practically, the
CRST, CCLK, CI/O, CAUX1, CAUX2, PRES and PRES
pins can sustain 8 kV. The CVCC pin has the same ESD
protection and can source up to 70 mA continuously, the
absolute maximum current being internally limited with a
max at 150 mA. The CVCC current limit depends on VDDP
and CVCC.
ESD PROTECTION
The NCN8025 / NCN8025A includes devices to protect
the pins against the ESD spike voltages. To cope with the
different ESD voltages developed across these pins, the built
APPLICATION SCHEMATIC
VDD
+3.3 V
100 nF
24 23 22
Exposed Pad
3
PRES
CI/O
CAUX2
I/Ouc
2
PRES
16
25
4
15
GND
5
14
13
6
VDD
+3.3 V
CAUX1
7
8
9
GND
VDD
100 nF
RSTIN
PORADJ
R1
10 11 12
Optional R1/R2 resistor
divider − if not used it is
recommended to connect
PORADJ to Ground
CMDVCC
10 mF
3.3 V Microcontroller
18 CLKIN
INT
17
1
CVCC
+
21 20 19
CRST
100 nF
VDDP
GND
VDDP
+5 V
CCLK
VSEL0
AUX1uc
AUX2uc
CLKDIV1
VSEL1
CLKDIV2
XTAL1 XTAL2
R2
220 nF
1
2
3
4
VCC
GND
RST
VPP
CLK
C4
I/O
C8
5
6
7
8
DET
100 nF
Normally Open
SMART CARD
Figure 9. Application Schematic
ORDERING INFORMATION
Package
Shipping†
NCN8025AMNTXG
QFN24
(Pb−Free)
3000 / Tape & Reel
NCN8025MTTBG
QFN16
(Pb−Free)
3000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
13
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFN24, 4x4, 0.5P
CASE 485L
ISSUE B
1 24
SCALE 2:1
D
PIN 1
REFEENCE
2X
0.15 C
2X
ÉÉÉ
ÉÉÉ
ÉÉÉ
0.15 C
DETAIL A
E
ALTERNATE
CONSTRUCTIONS
ÉÉÉ
ÉÉÉ
ÇÇÇ
EXPOSED Cu
DETAIL B
0.10 C
SEATING
PLANE
L
24X
7
DIM
A
A1
A3
b
D
D2
E
E2
e
L
L1
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.20
0.30
4.00 BSC
2.70
2.90
4.00 BSC
2.70
2.90
0.50 BSC
0.30
0.50
0.05
0.15
XXXXX
XXXXX
ALYWG
G
13
E2
1
24
A1
A3
GENERIC
MARKING DIAGRAM*
D2
DETAIL A
ÉÉ
ÉÉ
ÇÇ
ALTERNATE TERMINAL
CONSTRUCTIONS
C
A1
SIDE VIEW
MOLD CMPD
DETAIL B
A
A3
NOTE 4
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30 MM
FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
L1
TOP VIEW
0.08 C
L
L
A
B
DATE 05 JUN 2012
19
e
e/2
24X
b
0.10 C A B
0.05 C
BOTTOM VIEW
NOTE 3
RECOMMENDED
SOLDERING FOOTPRINT
4.30
24X
0.55
2.90
XXXXX = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
1
4.30
2.90
0.50
PITCH
24X
0.32
DIMENSIONS: MILLIMETERS
DOCUMENT NUMBER:
DESCRIPTION:
98AON11783D
QFN24, 4X4, 0.5P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFN16 3*3*0.75 MM, 0.5 P
CASE 488AK−01
ISSUE O
DATE 13 SEP 2004
1
SCALE 2:1
D
PIN 1
LOCATION
ÇÇ
ÇÇ
0.15 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM
SPACING BETWEEN LEAD TIP AND FLAG.
A
B
E
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
TOP VIEW
0.15 C
(A3)
0.10 C
A
16 X
SEATING
PLANE
0.08 C
SIDE VIEW
A1
C
16X
L
16
1
5
8
4
16X
e
EXPOSED PAD
XXXX
XXXX
ALYW
9
E2
K
16
16X
XXXX
A
L
Y
W
12
1
13
b
0.10 C A B
0.05 C
GENERIC
MARKING DIAGRAM*
ÇÇ
ÇÇ
ÇÇ
D2
NOTE 5
MILLIMETERS
MIN
MAX
0.70
0.80
0.00
0.05
0.20 REF
0.18
0.30
3.00 BSC
1.65
1.85
3.00 BSC
1.65
1.85
0.50 BSC
0.20
−−−
0.30
0.50
BOTTOM VIEW
*This information is generic. Please refer
to device data sheet for actual part
marking. Pb−Free indicator, “G”, may
or not be present.
NOTE 3
DOCUMENT NUMBER:
DESCRIPTION:
98AON19612D
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
QFN16, 3*3*0.75 MM, 0.5 PITCH
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
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Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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