NCP10671BD100R2G

NCP10670B, NCP10671B, NCP10672B High-Voltage Switcher for Low Power Offline SMPS The NCP1067X products integrate a fixed frequency current mode controller with a 700 V MOSFET. Available in a SOIC−7 package, the NCP1067X offer a high level of integration, including soft−start, frequency−jittering, short−circuit protection, skip−cycle, ramp compensation, and a Dynamic Self−Supply (eliminating the need for an auxiliary winding). During nominal load operation, the NCP1067X switches at one of the available frequencies (60 or 100 kHz). When the output power demand diminishes, the IC automatically enters into a skip mode to reduce the standby consumption down. Protection features include: a timer to detect an overload or a short−circuit event, Overvoltage Protection with auto−recovery. For improved standby performance, the connection of an auxiliary winding or supplying the IC from the output, stops the DSS operation and helps to reduce input power consumption below 25 mW at high line. NCP1067x can be seamlessly used both in non−isolated and in isolated topologies. Features • Built−in 700 V MOSFET with RDS(on) of 34  (NCP10670/1) and • • • • • • • • • • • • 12  (NCP10672) Large Creepage Distance Between High−Voltage Pins Current−Mode Fixed Frequency Operation – 60 or 100 kHz Fixed Ramp Compensation Direct Feedback Connection for Non−isolated Converter Skip−Cycle Operation at Low Peak Currents Only Dynamic Self−Supply: No Need for an Auxiliary Winding Internal 4 ms Soft−Start Auto−Recovery Output Short Circuit Protection with Timer−Based Detection Auto−Recovery Overvoltage Protection with Auxiliary Winding Operation Frequency Jittering for Better EMI Signature No Load Input Consumption < 25 mW These Devices are Pb−Free and are RoHS Compliant www.onsemi.com SOIC8 CASE 751EV MARKING DIAGRAM 8 P1067xy ALYW G 1 P1067 x y A L Y G = Specific Device Code = Current Limit (0, 1, 2) = Frequency (060, 100) = Assembly Location = Wafer Lot = Year = Pb−Free Package PIN CONNECTION VCC FB COMP GND GND DRAIN GND SOIC−7 ORDERING INFORMATION See detailed ordering and shipping information on page 23 of this data sheet. Applications • Auxiliary / Standby Isolated and Non−Isolated Power Supplies • Power Meter SMPS • Wide Vin Low Power Industrial SMPS © Semiconductor Components Industries, LLC, 2018 February, 2019 − Rev. 0 1 Publication Order Number: NCP10670/D NCP10670B, NCP10671B, NCP10672B Table 1. PRODUCTS INFOS & INDICATIVE MAXIMUM OUTPUT POWER 230 Vac +15% 85 − 265 Vac Product RDS(on) IIPK(0) Adapter OpenFrame Adapter OpenFrame NCP10670 60 kHz 34  100 mA 1.1 W 2.7 W 0.6 W 1.5 W NCP10671 60 kHz 34  250 mA 2.7 W 6.7 W 1.5 W 3.7 W NCP10672 100 kHz 12  780 mA 6.2 W 15.5 W 3.3 W 7.8 W 1. Informative values only, with Tamb = 25°C, Tcase = 100°C, Self supply via Auxiliary winding and circuit mounted on minimum copper area as recommended. Table 2. SELECTION TABLE Device Frequency RDS(on) IIPK(0) Package Type NCP10670 60 kHz 34 100 mA NCP10670 100 kHz 34 100 mA SOIC−7 (Pb−Free) NCP10671 60 kHz 34 250 mA NCP10671 100 kHz 34 250 mA NCP10672 60 kHz 12 780 mA NCP10672 100 kHz 12 780 mA Figure 1. Typical Non−Isolated Application (Buck Converter) Figure 2. Typical Isolated Application (Flyback Converter) www.onsemi.com 2 NCP10670B, NCP10671B, NCP10672B PIN DESCRIPTION Pin No. SOIC−7 Name Function 1 VCC Powers the internal circuitry 2 Comp Compensation 3 Description This pin is connected to an external capacitor. The VCC includes an auto−recovery over voltage protection. The error amplifier output is available on this pin. The network connected between this pin and ground adjusts the regulation loop bandwidth. Also, by connecting an opto−coupler to this pin, the peak current set point is adjusted accordingly to the output power demand. This missing pin ensures adequate creepage distance 4 Drain Drain connection 5−7 GND The IC Ground 8 FB Feedback signal input The internal drain MOSFET connection This is the inverting input of the trans conductance error amplifier. It is normally connected to the switching power supply output through a resistor divider. Table 3. TYPICAL APPLICATION Non Isolated Buck • If the output voltage is above 9.0 V typ. (between VCC(on) level and VOVP level) VCC is supplied from output via D2 • If the output voltage is below 9.0 V, D2 is redundant, the IC is supplied from DSS • Direct feedback, resistive divider formed by R3, R4 sets output voltage • If the output voltage is above 9.0 V typ. (between VCC(on) level and VOVP level) VCC is supplied from output via D3 • If the output voltage is below 9.0 V, D3 is redundant, the IC is supplied from DSS • Optocoupler feedback, output voltage is set by D4 Non Isolated Buck−Boost (Invert) • If the output voltage is above 9.0 V typ. between VCC(on) level and VOVP level, VCC is supplied from output via D2 • If the output voltage is below 9.0 V, D2 is redundant, the IC is supplied from DSS • Direct feedback, resistive divider formed by R3, R4 sets output voltage www.onsemi.com 3 NCP10670B, NCP10671B, NCP10672B Table 3. TYPICAL APPLICATION Non Isolated Flyback • If the output voltage is above 9.0 V typ. between VCC(on) level and VOVP level –VCC supplied from output via D4 • If the output voltage is below 9.0 V, D4 is redundant, the IC is supplied from DSS • Resistive divider formed by R2, R3 sets output voltage Isolated Flyback • VCC supplied from auxiliary winding • Optocoupler feedback, resistive divider formed by R6, R7 sets output voltage www.onsemi.com 4 NCP10670B, NCP10671B, NCP10672B Vcc DRAIN 80−s Filter V CC OVP SCP VOVP Ipflag UVLO Reset Vdd VCC Management S tSCP Q R t recovery UVLO Jittering OFF TSD VCOMP(REF) OSC V CC Sawtooth R COMP(up) S Sawtooth Q R ICOMPskip SKIP Ramp compensation SKIP = ”1” → Shut down some blocks to reduce consumption FB/COMP Processing COMP GND LEB Ipflag ICOMPfault ICOMP to CS setpoint Reset IFreeze IFB Soft −Start IIPK(0) Reset SS as recoving from SCP , TSD , VCC OVP or UVLO FB Figure 3. Simplified Internal Circuit Architecture www.onsemi.com 5 NCP10670B, NCP10671B, NCP10672B MAXIMUM RATINGS (All voltages related to GND terminal) Parameter Rating Units Power supply voltage, VCC pin, continuous voltage −0.3 to 20 V Vinmax Voltage on all pins, except Drain and VCC pin −0.3 to 10 V BVdss Drain voltage −0.3 to 700 V 10 mA 300 300 850 mA mA mA 335 335 950 mA mA mA 520 520 1500 mA mA mA 116 °C/W 102 °C/W 150 °C −60 to +150 °C Symbol VCC ICC IDS(PK) RθJ−A Maximum Current into VCC pin Drain Current Peak during Transformer Saturation (TJ = 150°C): NCP10670 NCP10671 NCP10672 Drain Current Peak during Transformer Saturation (TJ = 125°C): NCP10670 NCP10671 NCP10672 Drain Current Peak during Transformer Saturation (TJ = 25°C): NCP10670 NCP10671 NCP10672 Thermal Resistance Junction−to−Air – NCP10670(1) SOIC7 with 200 mm2 of 35− copper area RθJ−A Thermal Resistance Junction−to−Air – NCP10672 SOIC7 with 200 TJMAX Maximum Junction Temperature mm2 of 35− copper area Storage Temperature Range HBM Human Body Model ESD Capability per JEDEC JESD22−A114F 2 kV CDM Charged−Device Model ESD Capability per JEDEC JESD22−C101E 1 kV Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78. i D(t) < 1.5 x I DS ( PK ) < t LEB I DS ( PK ) Transformer Saturation t Figure 4. Spike Limits www.onsemi.com 6 NCP10670B, NCP10671B, NCP10672B ELECTRICAL CHARACTERISTICS (Tj = 25°C, for min/max values Tj = −40°C to +125°C, Vcc = 14 V unless otherwise noted) Symbol Rating Pin Min Typ Max Unit SUPPLY SECTION AND VCC MANAGEMENT VCC(on) VCC increasing level at which the switcher starts operation 1 8.4 9.0 9.5 V VCC(min) VCC decreasing level at which the HV current source restarts 1 7.0 7.5 7.8 V VCC(off) VCC decreasing level at which the switcher stops operation (UVLO) 1 6.7 7.0 7.2 V Internal IC consumption, NCP10670 switching at 60 kHz Internal IC consumption, NCP10670 switching at 100 kHz Internal IC consumption, NCP10671 switching at 60 kHz Internal IC consumption, NCP10671 switching at 100 kHz Internal IC consumption, NCP10672 switching at 60 kHz Internal IC consumption, NCP10672 switching at 100 kHz 1 − − − − − − 0.84 0.88 0.84 0.88 0.91 1.00 1.05 1.10 1.05 1.10 1.15 1.25 mA Internal IC consumption, COMP is 0 V (No switching on MOSFET) 1 − 340 − A − − 34 65 41 72   − − 12 22 14 24   700 − − V − − 7 1 − − A A − − 20 10 − − ns ns − − − 200 200 230 − − − ns ns ns ICC1 ICCskip POWER SWITCH CIRCUIT Power Switch Circuit on−state resistance NCP10670, NCP10671 (Id = 50 mA) Tj = 25°C Tj = 125°C NCP10672 (Id = 50 mA) Tj = 25°C Tj = 125°C 4 BVDSS Power Switch Circuit & Startup breakdown voltage (ID(off) = 120 A, Tj = 25°C) 4 IDSS(off) Power Switch & Startup breakdown voltage off−state leakage current Tj = 125°C (Vds = 700 V) Tj = 25°C (Vds = 700 V) 4 Switching characteristics (RL = 50 , VDS set for Idrain = 0.7 x Ilim) Turn−on time (90% − 10%) Turn−off time (10% − 90%) 4 Minimum on time NCP10670 NCP10671 NCP10672 4 RDS(on) tr tf ton(min) INTERNAL START−UP CURRENT SOURCE Istart1 High−voltage current source, VCC = VCC(on) – 200 mV 4 4 8 12 mA Istart2 High−voltage current source, VCC = 0 V 4 − 0.4 − mA VCC Transient level for Istart1 to Istart2 toggling point 1 − 1.2 − V Minimum startup voltage, VCC = 0 V 4 − − 22 V Maximum internal current setpoint at 50% duty cycle FB = 2 V, Tj = 25°C NCP10670 NCP10671 NCP10672 − − − − − − 83 208 650 − − − mA mA mA Maximum internal current setpoint at beginning of switching cycle FB = 2 V, Tj = 25°C NCP10670 NCP10671 NCP10672 − − − 85 223 702 100 250 780 115 277 858 mA mA mA Final switch current with a primary slope of 200 mA/s, FSW = 60 kHz (Note 3) NCP10670 NCP10671 NCP10672 − − − − − − 120 258 740 − − − mA mA mA VCCTH Vstart(min) CURRENT COMPARATOR IIPK IIPK(0) IIPKSW www.onsemi.com 7 NCP10670B, NCP10671B, NCP10672B ELECTRICAL CHARACTERISTICS (Tj = 25°C, for min/max values Tj = −40°C to +125°C, Vcc = 14 V unless otherwise noted) (continued) Symbol Rating Pin Min Typ Max Unit − − − 120 250 710 − − − mA mA mA CURRENT COMPARATOR IIPKSW Final switch current with a primary slope of 200 mA/s, FSW = 100 kHz (Note 3) NCP10670 NCP10671 NCP10672 tSS Soft−start duration (guaranteed by design) − − 4 − ms tprop Propagation delay from current detection to drain OFF state − − 70 − ns tLEB Leading Edge Blanking Duration NCP10670 NCP10671 NCP10672 − − − − − − 130 130 160 − − − ns ns ns INTERNAL OSCILLATOR fOSC Oscillation frequency, 60 kHz version, Tj = 25°C (Note 4) − 54 60 66 kHz fOSC Oscillation frequency, 100 kHz version, Tj = 25°C (Note 4) − 90 100 110 kHz fjitter Frequency jittering in percentage of fOSC − − ±6 − % fswing Jittering swing frequency − − 300 − Hz Dmax Maximum duty−cycle − 62 66 72 % ERROR AMPLIFIER SECTION Voltage Feedback Input (VCOMP = 2.5 V) 8 3.2 3.3 3.4 V IFB Input Bias Current (VFB = 3.3 V) 8 − 1 − A GM Transconductance 2 − 2 − mS IOTAlim OTA maximum current capability (VFB > VOTAen) 2 − +150/−150 − A VOTAen FB voltage to disable OTA 8 0.7 1.3 1.7 V VREF COMPENSATION SECTION ICOMPfault COMP current for which Fault is detected 2 − −40 − A ICOMP100% COMP current for which internal current set−point is 100% (IIPK(0)) 2 − −44 − A ICOMPfreeze COMP current for which internal current set−point is: IFreeze1, 2 or 3 (NCP10670/1/2) 2 − −80 − A VCOMP(REF) Equivalent pull−up voltage in linear regulation range (Guaranteed by design) 2 − 2.7 − V RCOMP(up) Equivalent feedback resistor in linear regulation range (Guaranteed by design) 2 − 17.7 − k The COMP pin current level to enter skip mode 2 − −120 − A IFreeze1 Internal minimum current setpoint (ICOMP = ICOMPFreeze) in NCP10670 − − 35 − mA IFreeze2 Internal minimum current setpoint (ICOMP = ICOMPFreeze) in NCP10671 − − 92 − mA IFreeze3 Internal minimum current setpoint (ICOMP = ICOMPFreeze) in NCP10672 − − 270 − mA SKIP CYCLE ICOMPskip RAMP COMPENSATION Sa(60) The internal ramp compensation @ 60 kHz: NCP10670 NCP10671 NCP10672 − − − − − − 2.8 8.4 15.6 − − − mA/s mA/s mA/s Sa(100) The internal ramp compensation @ 100 kHz: NCP10670 NCP10671 NCP10672 − − − − − − 4.7 14 26 − − − mA/s mA/s mA/s www.onsemi.com 8 NCP10670B, NCP10671B, NCP10672B ELECTRICAL CHARACTERISTICS (Tj = 25°C, for min/max values Tj = −40°C to +125°C, Vcc = 14 V unless otherwise noted) (continued) Symbol Rating Pin Min Typ Max Unit Fault validation further to error flag assertion − 35 48 − ms OFF phase in fault mode − − 400 − ms VOVP VCC voltage at which the switcher stops pulsing 1 17.0 18.0 18.8 V tOVP The filter of VCC OVP comparator − − 80 − s PROTECTIONS tSCP trecovery TEMPERATURE MANAGEMENT TSD Temperature shutdown (Guaranteed by design) − 150 163 − °C TSDHYST Hysteresis in shutdown (Guaranteed by design) − − 20 − °C Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. The final switch current is: IIPK(0) / (Vin/LP + Sa) x Vin/LP + Vin/LP x tprop, with Sa the built−in slope compensation, Vin the input voltage, LP the primary inductor in a flyback, and tprop the propagation delay.. 4. Oscillator frequency is measured with disabled jittering. TYPICAL CHARACTERISTICS VCC(on) 9.10 Voltage [V] Voltage [V] 9.05 9.00 8.95 8.90 8.85 8.80 −40 −20 0 20 40 60 80 100 120 7.48 7.46 7.44 7.42 7.40 7.38 7.36 7.34 7.32 7.30 −40 VCC(min) −20 0 20 80 100 Figure 5. VCC(on) vs. Temperature Figure 6. VCC(min) vs. Temperature Current [mA] 6.96 6.94 6.92 6.90 6.88 −20 0 20 40 120 IDSS(off) VCC(off) Voltage [V] 60 Temperature [5C] 6.98 6.86 −40 40 Temperature [5C] 60 80 100 120 10 9 8 7 6 5 4 3 2 1 0 −40 −20 0 20 40 60 80 100 Temperature [5C] Temperature [5C] Figure 7. VCC(off) vs. Temperature Figure 8. IDSS(off) vs. Temperature www.onsemi.com 9 120 NCP10670B, NCP10671B, NCP10672B TYPICAL CHARACTERISTICS (continued) ICC1(10670_60k) 0.89 0.88 Current [mA] Current [mA] 0.87 0.85 0.83 0.81 0.79 0.75 −40 0.86 0.85 0.84 0.82 −20 0 20 40 60 80 100 120 −40 0 20 40 60 80 100 120 Temperature [5C] Figure 9. ICC1 (10670_60k) vs. Temperature Figure 10. ICC1 (NCP10670_100k) vs. Temperature ICC1(10672_60k) ICC1(10672_100k) 1.04 0.91 Current [mA] 1.02 0.90 0.89 0.88 0.87 0.86 0.85 −40 −20 0 20 40 60 80 100 1.00 0.98 0.96 0.94 0.92 0.90 −40 120 −20 0 20 40 60 80 100 120 Temperature [5C] Temperature [5C] Figure 11. ICC1 (10672_60k) vs. Temperature Figure 12. ICC1 (10672_100k) vs. Temperature IIPK(0)10670 110 IIPK(0)10671 250 Current [mA] 105 100 95 90 85 −40 −20 0 20 40 60 80 100 245 240 235 230 225 220 −40 120 Temperature [5C] −20 40 60 80 100 120 Ifreeze10670 34.5 34.0 Current [mA] 760 750 740 730 720 710 −40 20 Figure 14. IIPK(0)10671 vs. Temperature IIPK(0)10672 770 0 Temperature [5C] Figure 13. IIPK(0)10670 vs. Temperature Current [mA] −20 Temperature [5C] 0.92 Current [mA] 0.87 0.83 0.77 Current [mA] ICC1(10670_100k) 0.89 33.5 33.0 32.5 32.0 31.5 −20 0 20 40 60 80 100 31.0 120 -40 -20 0 20 40 60 80 100 120 Temperature [5C] Temperature [5C] Figure 15. IIPK(0)10672 vs. Temperature Figure 16. Ifreeze10670 vs. Temperature www.onsemi.com 10 NCP10670B, NCP10671B, NCP10672B TYPICAL CHARACTERISTICS (continued) Ifreeze10671 86 268 Current [mA] Current [mA] 85 84 83 82 81 80 266 264 262 260 258 256 254 79 −40 −20 0 20 40 60 80 100 252 −40 120 0 100 120 Resistivity [W] 20 40 30 20 10 −20 0 20 40 60 80 100 15 10 5 0 −40 120 −20 0 40 60 80 100 120 Figure 20. RDS(on)10672 vs. Temperature fOSC60 62 20 Temperature [5C] Figure 19. RDS(on)10670/1 vs. Temperature fOSC100 110 60 Frequency [kHz] Frequency [kHz] 80 RDS(on)10672 25 Temperature [5C] 105 58 100 56 54 52 −20 0 20 40 60 80 100 95 90 85 −40 120 −20 0 Temperature [5C] Current [mA] 8 6 4 2 0 20 40 60 60 80 100 120 Istart2 0.7 10 −20 40 Figure 22. fOSC100 vs. Temperature Istart1 12 20 Temperature [5C] Figure 21. fOSC60 vs. Temperature Current [mA] 60 Figure 18. Ifreeze10672 vs. Temperature 50 0 −40 40 Figure 17. Ifreeze10671 vs. Temperature 60 50 −40 20 Temperature [5C] RDS(on)10670/1 0 −40 −20 Temperature [5C] 70 Resistivity [W] Ifreeze10672 270 80 100 0.6 0.5 0.4 0.3 0.2 0.1 −40 120 Temperature [5C] −20 0 20 40 60 80 100 Temperature [5C] Figure 23. Istart1 vs. Temperature Figure 24. Istart2 vs. Temperature www.onsemi.com 11 120 NCP10670B, NCP10671B, NCP10672B TYPICAL CHARACTERISTICS (continued) trecovery 440 Duty Cycle [%] Time [ms] 435 430 425 420 415 410 −40 −20 0 20 60 80 100 66.3 66.2 66.1 66.0 65.9 65.8 65.7 65.6 −40 120 0 VOVP Time [ms] 53 17.9 17.8 100 17.7 17.6 120 53 52 52 51 51 50 −20 0 20 40 60 80 100 50 −40 120 −20 0 Temperature [5C] 1.4 Voltage [V] 1.2 1.0 0.8 0.6 0.4 0.2 −20 0 20 40 60 40 60 80 100 80 100 120 3.34 3.33 3.32 3.31 3.30 3.29 3.28 3.27 3.26 3.25 3.24 −40 VREF −20 0 20 40 60 80 100 Temperature [5C] Temperature [5C] Figure 29. VOTAen vs. Temperature Figure 30. VREF vs. Temperature fmin 25.6 120 Figure 28. tSCP vs. Temperature VOTAen 1.6 20 Temperature [5C] Figure 27. VOVP vs. Temperature Voltage [V] 80 tSCP 54 17.5 25.4 20 25.2 19 25.0 24.8 24.6 24.4 120 Vstart(min) 20 Voltage [V] Frequency [kHz] 60 Figure 26. D(max) vs. Temperature 54 19 18 18 17 24.2 24.0 −40 40 Figure 25. trecovery vs. Temperature 18.0 0.0 −40 20 Temperature [5C] 18.1 17.4 −40 −20 Temperature [5C] 18.2 Voltage [V] 40 Dmax 66.4 −20 0 20 40 60 80 100 17 −40 120 −20 0 20 40 60 80 100 Temperature [5C] Temperature [5C] Figure 31. fmin vs. Temperature Figure 32. Vstart(min) vs. Temperature www.onsemi.com 12 120 NCP10670B, NCP10671B, NCP10672B APPLICATION INFORMATION Introduction The NCP1067X offers a complete current−mode control solution. The component integrates everything needed to build a rugged and cost effective Switch−Mode Power Supply (SMPS) featuring low standby power. The Quick Selection Table is on details the differences between references, mainly peak current setpoints, RDS(on) value and operating frequency. • Current−mode operation: the controller uses current−mode control architecture. • 700 V – _ Power MOSFET: Due to ON Semiconductor Very High Voltage Integrated Circuit technology, the circuit hosts a high−voltage power MOSFET featuring a 34 or 12  RDS(on) – Tj = 25°C. This value lets the designer build a power supply up to 7.8 W operated on universal mains. An internal current source delivers the startup current, necessary to crank the power supply. • Dynamic Self−Supply: Due to the internal high voltage current source, this device could be used in the application without the auxiliary winding to provide supply voltage. • Short circuit protection: by permanently monitoring the COMP line activity, the IC is able to detect the presence of a short−circuit, immediately reducing the output power for a total system protection. A tSCP timer is started as soon as the COMP current is below threshold, ICOMPfault, which indicates the maximum peak current. If at the end of this timer the fault is still present, then the device enters a safe, auto−recovery burst mode, affected by a fixed timer recurrence, trecovery. Once the short has disappeared, the controller resumes and goes back to normal operation. • Built−in VCC Over Voltage Protection: when the auxiliary winding is used to bias the VCC pin (no DSS), an internal comparator is connected to VCC pin. In case the voltage on the pin exceeds a level of VOVP (18 V typically), the controller immediately stops switching and waits a full timer period (trecovery) before attempting to restart. If the fault is gone, the controller resumes operation. If the fault is still there, e.g. a broken opto−coupler, the controller protects the load through a safe burst mode. • Frequency jittering: an internal low−frequency modulation signal varies the pace at which the oscillator frequency is modulated. This helps spreading out energy in conducted noise analysis. • Soft−Start: a 4 ms soft−start ensures a smooth startup sequence, reducing output overshoots. • Skip: if SMPS naturally exhibits a good efficiency at nominal load, they begin to be less efficient when the output power demand diminishes. By skipping un−needed switching cycles, the NCP1067X drastically reduces the power wasted during light load conditions. Startup sequence When the power supply is first powered from the mains outlet, the internal current source (typically 8.0 mA) is biased and charges up the VCC capacitor from the drain pin. Once the voltage on this VCC capacitor reaches the VCC(on) level (typically 9.0 V), the current source turns off and pulses are delivered by the output stage: the circuit is awake and activates the power MOSFET if the bulk voltage is above Vstart(min) (22 V dc). Figure 33 details the simplified internal circuitry. Vbulk + I1 Rlimit Istart1 ← ICC1 1 Drain 5 I2 − + + CVCC VCC(on) VCC(min) + + − VOVP VCC >18 V ? → OVP fault 8 Figure 33. The Internal Arrangement of the Start−up Circuitry Being loaded by the circuit consumption, the voltage on the VCC capacitor goes down. When VCC is below VCC(min) level (7.5 V typically), it activates the internal current source to bring VCC toward VCC(on) level and stops again: a cycle takes place whose low frequency depends on the VCC capacitor and the IC consumption. A 1.5 V ripple takes place on the VCC pin whose average value equals (VCC(on) + VCC(min)) / 2. Figure 34 portrays a typical operation of the DSS. www.onsemi.com 13 NCP10670B, NCP10671B, NCP10672B 10 9 9.0 V 8 7 6 V [V] 7.5 V VCC 5 Device Internal Pulses 4 3 2 VCCTH 1 0 0 1 2 3 4 5 6 7 8 9 10 time [ms] Startup Duration Figure 34. The Charge/Discharge Cycle Over a 1 mF VCC Capacitor The VCC capacitor has only a supply role and its value does not impact other parameters such as fault duration or the frequency sweep period for instance. As one can see on Figure 33, an internal OVP comparator, protects the switcher against lethal VCC runaways. This situation can occur if the feedback loop optocoupler fails, for instance, and you would like to protect the converter against an over voltage event. In that case, the over voltage protection (OVP) circuit and immediately stops the output pulses for trecovery duration (400 ms typically). Then a new start−up attempt takes place to check whether the fault has disappeared or not. The OVP paragraph gives more design details on this particular section. As one can see, even if there is auxiliary winding to provide energy for VCC, it happens that the device is still biased by DSS during start−up time or some fault mode when the voltage on auxiliary winding is not ready yet. The VCC capacitor shall be dimensioned to avoid VCC crosses VCC(off) level, which stops operation. The V between VCC(min) and VCC(off) is 0.5 V. There is no current source to charge VCC capacitor when driver is on, i.e. drain voltage is close to zero. Hence the VCC capacitor can be calculated using C VCC ≥ I CC1D max f OSC @ V (eq. 1) Take the 60 kHz device as an example. CVCC should be above 0.84 m @ 72% 54 kHz @ 0.5 + 22 nF (eq. 2) A margin that covers the temperature drift and the voltage drop due to switching inside FET should be considered, and thus a capacitor above 0.1 F is appropriate. www.onsemi.com 14 NCP10670B, NCP10671B, NCP10672B Fault Condition – Short−circuit on VCC Fault Condition – Output Short−circuit In some fault situations, a short−circuit can purposely occur between VCC and GND. In high line conditions (VHV = 370 VDC) the current delivered by the startup device will seriously increase the junction temperature. For instance, since Istart1 equals 4 mA (the min corresponds to the highest Tj), the device would dissipate 370 · 4 m 1.48 W. To avoid this situation, the controller includes a novel circuitry made of two startup levels, Istart1 and Istart2. At power−up, as long as VCC is below a 1.2 V level, the source delivers Istart2 (around 400 A typical), then, when VCC reaches 1.2 V, the source smoothly transitions to Istart1 and delivers its nominal value. As a result, in case of short−circuit between VCC and GND, the power dissipation will drop to 370 · 400  = 148 mW. Figure 34 portrays this particular behavior. The first startup period is calculated by the formula C · V = I · t, which implies a 1  · 1.2 / 400  = 3 ms startup time for the first sequence. The second sequence is obtained by toggling the source to 8 mA with a delta V of VCC(on) – VCCTH = 9.0 – 1.2 = 7.8 V, which finally leads to a second startup time of 1  · 7.8 / 8 m = 975 s. The total startup time becomes 3 m + 0.975 m = 3.975 ms. Please note that this calculation is approximated by the presence of the knee in the vicinity of the transition. As soon as VCC reaches VCC(on), drive pulses are internally enabled. If everything is correct, the auxiliary winding increases the voltage on the VCC pin as the output voltage rises. During the start−sequence, the controller smoothly ramps up the peak drain current to maximum setting, i.e. IIPK, which is reached after a typical period of 4 ms. When the output voltage is not regulated, the current coming through COMP pin is below ICOMPfault level (40 A typically), which is not only during the startup period but also anytime an overload occurs, an internal error flag is asserted, Ipflag, indicating that the system has reached its maximum current limit set point. The assertion of this flag triggers a fault counter tSCP (48 ms typically). If at counter completion, Ipflag remains asserted, all driving pulses are stopped and the part stays off in trecovery duration (about 400 ms). A new attempt to re−start occurs and will last 48 ms providing the fault is still present. If the fault still affects the output, a safe burst mode is entered, affected by a low duty−cycle operation (11%). When the fault disappears, the power supply quickly resumes operation. Figure 35 depicts this particular mode: VCC(on) VCC(min) V CC IpFlag VCOMP Open Loop FB 48 ms typ . Fault level TIMER 400 ms .typ DRV internal Figure 35. In Case of Short−circuit or Overload, the NCP1067X Protects Itself and the Power Supply via a Low Frequency Burst Mode. The VCC is Maintained by the Current Source and Self−supplies the Controller. www.onsemi.com 15 NCP10670B, NCP10671B, NCP10672B Auto−recovery Over Voltage Protection and to filter out the Vcc line to avoid undesired OVP activation. Rlimit should be carefully selected to avoid triggering the OVP as we discussed, but also to avoid disturbing the VCC in low / light load conditions. Self−supplying controllers in extremely low standby applications often puzzles the designer. Actually, if a SMPS operated at nominal load can deliver an auxiliary voltage of an arbitrary 16 V (Vnom), this voltage can drop below 10 V (Vstby) when entering standby. This is because the recurrence of the switching pulses expands so much that the low frequency re−fueling rate of the VCC capacitor is not enough to keep a proper auxiliary voltage. The particular NCP1067X arrangement offers a simple way to prevent output voltage runaway when the optocoupler fails. As Figure 36 shows, a comparator monitors the VCC pin. If the auxiliary pushes too much voltage into the CVCC capacitor, then the controller considers an OVP situation and stops the internal drivers. When an OVP occurs, all switching pulses are permanently disabled. After trecovery delay, it resumes the internal drivers. If the failure symptom still exists, e.g. feedback opto−coupler fails, the device keeps the auto−recovery OVP mode. It is recommended insertion of a resistor (Rlimit ) between the auxiliary dc level and the VCC pin to protect the IC against high voltage spikes, which can damage the IC, Drain VCC(on) = 9.0 V VCC(min) = 7.5 V Istart1 VCC Shut down Internal DRV CVCC 80 s filter D1 Rlimit CAUX NAUX GND VOVP Figure 36. A More Detailed View of the NCP1067X Offers Better Insight on How to Properly Wire an Auxiliary Winding VOVP VCC(on) VCC(min) VCC VCOMP 48 ms typ Fault level TIMER 400 ms typ DRV internal Figure 37 Describes the Main Signal Variations when the Part Operates in Auto−recovery OVP: Figure 37. If the VCC Current Exceeds a Certain Threshold, an Auto−recovery Protection is Activated www.onsemi.com 16 NCP10670B, NCP10671B, NCP10672B Soft−start The NCP1067X features a 4 ms soft−start which reduces the power−on stress but also contributes to lower the output overshoot. Figure 38 shows a typical operating waveform. VCC The NCP1067X features a novel patented structure which offers a better soft−start ramp, almost ignoring the start−up pedestal inherent to traditional current−mode supplies: VCCON 0 V (fresh PON) Drain current Max IIPK 4 ms Figure 38. The 4 ms Soft−start Sequence Jittering Frequency jittering is a method used to soften the EMI signature by spreading the energy in the vicinity of the main switching component. The NCP1067X offers a ±6% deviation of the nominal switching frequency. The sweep sawtooth is internally generated and modulates the clock up and down with a fixed frequency of 300 Hz. Figure 39 shows the relationship between the jitter ramp and the frequency deviation. It is not possible to externally disable the jitter. Jitter ramp 63.6 kHz 60 kHz Internal sawtooth 56.4 kHz adjustable Figure 39. Modulation Effects on the Clock Signal by the Jittering Sawtooth www.onsemi.com 17 NCP10670B, NCP10671B, NCP10672B Ipk Reduction The internal peak current set−point is following the COMP current information until its level reaches IFreeze. Below this value, the peak current setpoint is frozen to 30% of the IIPK(0). This value is reached at a COMP current level of ICOMPskip (120 A typically). Below this point, if the output power continues to decrease, the part enters skip cycle for the best performance in no−load conditions. Figure 40 depict the adopted scheme for the part. 800 NCP10672 NCP10671 NCP10670 Current Set Point [mA] 700 600 500 400 300 200 100 0 40 50 60 70 80 90 100 ICOMP [mA] Figure 40. IIPK Set−point is Frozen at Lower Power Demand this linear operating range, the dynamic resistance is 17.7 k typically (RCOMP(up)) and the effective pull up voltage is 2.7 V typically (VCOMP(REF)). When ICOMP is decreases, the COMP voltage will increase to 3.2 V. Feedback and Skip Figure 41 depicts the relationship between COMP pin voltage and current. The COMP pin operates linearly as the absolute value of COMP current (ICOMP) is above 40 A. In 3.5 3.0 VCOMP [V] 2.5 2.0 1.5 1.0 0.5 0.0 −180 −160 −140 −120 −100 −80 −60 −40 ICOMP [mA] Figure 41. COMP Pin Voltage vs. Current www.onsemi.com 18 −20 0 NCP10670B, NCP10671B, NCP10672B Figure 42 depicts the skip mode block diagram. When the COMP current information reaches ICOMPskip, the internal clock to set the flip−flop is blanked and the internal consumption of the controller is decreased. The hysteresis of internal skip comparator is minimized to lower the ripple of the auxiliary voltage for VCC pin and VOUT of power supply during skip mode. It easies the design of VCC over load range. Jittering OSC S VCOMP(REF) RCOMP(UP) R ICOMPskip − SKIP DRV stage Q Q CS comparator + COMP Figure 42. Skip Cycle Schematic Ramp Compensation and Ipk Set−point In order to allow the NCP106X to operate in CCM with a duty cycle above 50%, a fixed slope compensation is internally applied to the current−mode control. Here we got a table of the ramp compensation, the initial current set point, and the final current set−point of different versions of switcher. NCP10670 NCP10671 NCP10672 Fsw 60 kHz 100 kHz 60 kHz 100 kHz 60 kHz 100 kHz Sa 2.8 mA/s 4.7 mA/s 8.4 mA/s 14 mA/s 15.6 mA/s 26 mA/s IIPK(Duty = 50%) 83 mA 208 mA 650 mA IIPK(0) 100 mA 250 mA 780 mA Figure 43 depicts the variation of IIPK set−point vs. the power switcher duty ratio, which is caused by the internal ramp compensation. 800 Current Set Point [mA] 700 600 500 NCP10672 NCP10671 NCP10670 400 300 200 100 0 0% 10% 20% 30% 40% 50% 60% 70% Dutty Ratio [%] Figure 43. IIPK Set−point Varies with Power Switch on Time, Which is Caused by the Ramp Compensation www.onsemi.com 19 NCP10670B, NCP10671B, NCP10672B 1. The lateral MOSFET body−diode shall never be forward biased, either during start−up (because of a large leakage inductance) or in normal operation as shown in Figure 45. This condition sets the maximum voltage that can be reflected during toff . As a result, the Flyback voltage which is reflected on the drain at the switch opening cannot be larger than the input voltage. When selecting components, you thus must adopt a turn ratio which adheres to the following equation: FB pin function The FB pin is used in non isolated SMPS application only. Portion of the output voltage is connected into the pin. The voltage is compared with internal VREF (3.3 V) using Operation Transconductance Amplifier (Figure 44). The OTAs output is connected to COMP pin. From the outside an user defined compensation network is connected to the COMP pin. The current capability of OTA is limited to −150 A typically. The positive current is defined by internal RCOMP(up) resistor and VCOMP(ref) voltage. If FB path loop is broken (i.e. the FB pin is disconnected), an internal current IFB (1 A typ.) will pull up the FB pin and the IC stops switching to avoid uncontrolled output voltage increasing. In isolated topology, the FB pin should be connected to GND pin. In this configuration no current flows from OTA to COMP pin (OTA is disabled) so the OTA has no influence on regulation at all. N (V out ) V f) t V in, min (eq. 3) 2. In our case, since we operate from a 127 V DC rail while delivering 12 V, we can select a reflected voltage of 120 V dc maximum. Therefore, the turn ratio Np:Ns must be smaller than V reflect V out ) V f + 120 + 9.6 12 ) 0.5 (eq. 4) or Np:Ns < 9.6. Here we choose N = 8 in this case. We will see later on how it affects the calculation. VCOMP(REF) RCOMP(up) 350 ICOMP COMP 250 IFB FB 150 OTA ouT = 0 A IOTAlim if FB = 0 V − OTA + 50.0 > 0 !! −50.0 VREF 1.004M 1.011M 1.018M 1.025M 1.032M Figure 45. The Drain−Source Wave Shall Always be Positive Figure 44. FB Pin Connection Design Procedure The design of an SMPS around a monolithic device does not differ from that of a standard circuit using a controller and a MOSFET. However, one needs to be aware of certain characteristics specific of monolithic devices. Let us follow the steps: IL Ipeak IL I1 Vin min = 90 Vac or 127 Vdc once rectified, assuming a low bulk ripple Vin max = 265 Vac or 375 Vdc Ivalley Vout = 12 V Iavg Pout = 5 W Operating mode is CCM h = 0.8 t dTsw Tsw Figure 46. Primary Inductance Current Evolution in CCM www.onsemi.com 20 NCP10670B, NCP10671B, NCP10672B 3. Lateral MOSFETs have a poorly doped body−diode which naturally limits their ability to sustain the avalanche. A traditional RCD clamping network shall thus be installed to protect the MOSFET. In some low power applications, a simple capacitor can also be used since V drain,max + V in ) N (V out ) V f) ) I peak Ǹ peak to peak The peak current can be evaluated to be: I peak + (eq. 5) d max + N (V out ) V f) ) V in,min 1 V in,min + 1) I d,rms + + (eq. 6) P off + + (eq. 7) I L (eq. 8) P on + + (127 @ 0.44) 2 60k @ 1 @ 5) LF SW + + 158 mA (eq. 11) 2 92.8 m + 111.6 mA (eq. 12) 2 Ǹǒ Ǹǒ d I 2peak * I peakI L ) d I 2peak * I peakI L ) I 2L 3 I 2L 3 Ǔ Ǔ + + 57 mA (eq. 13) (on) + 110mW (eq. 14) I peak (V bulk ) V clamp) t off 2T SW + 0.158 @ (127 ) 100 @ 2) @ 10 n 2 @ 16.7  + 15.5 mW (eq. 15) + 10.04 mH 127 @ 0.44 10.04 m @ 60 k (eq. 9) 92.8 mA I valley (V bulk ) N (V out ) V f)) t on 6T SW 0.0464 @ (127 ) 100 @ 2) @ 20 n 6 @ 16.7  + + 2.1 mW (eq. 16) It is noted that the overlap of voltage and current seen on MOSFET during turning on and off duration is dependent on the snubber and parasitic capacitance seen from drain pin. Therefore the toff and ton in eq. 15 and eq. 16 have to be modified after measuring on the bench. 8. The theoretical total power is then 117 + 15.5 + 2.1 = 127.6 mW 9. If the NCP106X operates at DSS mode, then the losses caused by DSS mode should be counted as losses of this device on the following calculation: From eq.17, a K factor of 1 (50% ripple), gives an inductance of: V ind 2 Where, assume the Vclamp is equal to 2 times of reflected voltage. I Lavg I L + 92.8 m 7. Off−time and on−time switching losses can be estimated based on the following calculations: and defines the amount of ripple we want in CCM (see Figure 46 ). • Small K: deep CCM, implying a large primary inductance, a low bandwidth and a large leakage inductance. • Large K: approaching DCM where the RMS losses are worse, but smaller inductance, leading to a better leakage inductance. L+ 0.44 ) + 158 m * 2 where K+ I L P cond + I d,dms R ds (V in d) 2 f sw K P in 49.2 m If we take the maximum Rds(on) for a 125°C junction temperature, i.e. 34 , then conduction losses worse case are: 5. To obtain the primary inductance, we have the choice between two equations: L+ 2 + 6. Based on the above numbers, we can now evaluate the conduction losses: + 0.44 N (V out)V f) I L I Lavg + I peak * where Lf is the leakage inductance, Ctot the total capacitance at the drain node (which is increased by the capacitor you will wire between drain and source), N the NP:NS turn ratio, Vout the output voltage, Vf the secondary diode forward drop and finally, Ipeak the maximum peak current. Worse case occurs when the SMPS is very close to regulation, e.g. the Vout target is almost reached and Ipeak is still pushed to the maximum. For this design, we have selected our maximum voltage around 650 V (at Vin = 375 Vdc). This voltage is given by the RCD clamp installed from the drain to the bulk voltage. We will see how to calculate it later on. 4. Calculate the maximum operating duty−cycle for this flyback converter operated in CCM: N (V out ) V f) d ) On , I1 can also be calculated: Lf C tot I avg (eq. 10) P DSS + I cc1 @ V in,max + 0.8 m @ 375 + 300 mW www.onsemi.com 21 (eq. 17) NCP10670B, NCP10671B, NCP10672B MOSFET Protection which is 700 V. implementations: As in any Flyback design, it is important to limit the drain excursion to a safe value, e.g. below the MOSFET BVdss HV HV Figure 47 a−b−c present possible HV Rclamp Dz Cclamp D NCP1067x D NCP1067x GND NCP1067x GND CVcc GND CVcc C GND CVcc GND a) GND b) c) Figure 47. Different Options to Clamp the Leakage Spike area is far bigger for a transient suppressor than that of zener. A 5 W zener diode like the 1N5388B will accept 180 W peak power if it lasts less than 8.3 ms. If the peak current in the worse case (e.g. when the PWM circuit maximum current limit works) multiplied by the nominal zener voltage exceeds these 180 W, then the diode will be destroyed when the supply experiences overloads. A transient suppressor like the P6KE200 still dissipates 5 W of continuous power but is able to accept surges up to 600 W @ 1 ms. Select the zener or TVS clamping level between 40 to 80 volts above the reflected output voltage when the supply is heavily loaded. As a good design practice, it is recommended to implement one of this protection to make sure Drain pin voltage doesn’t go above 650 V (to have some margin between Drain pin voltage and BVdss) during most stringent operating conditions (high Vin and peak power). Figure 47a: the simple capacitor limits the voltage according to the lateral MOSFET body−diode shall never be forward biased, either during start−up (because of a large leakage inductance) or in normal operation as shown by Figure 45. This condition sets the maximum voltage that can be reflected during toff . As a result, the flyback voltage which is reflected on the drain at the switch opening cannot be larger than the input voltage. When selecting components, you must adopt a turn ratio which adheres to the following equation eq. 5. This option is only valid for low power applications, e.g. below 5 W, otherwise chances exist to destroy the MOSFET. After evaluating the leakage inductance, you can compute C with (eq. 6). Typical values are between 100 pF and up to 470 pF. Large capacitors increase capacitive losses… Figure 47b: the most standard circuitry is called the RCD network. You can calculate Rclamp and Cclamp using the following formula: R clamp + C clamp + Power Dissipation and Heatsinking The NCP1067X welcomes two dissipating terms, the DSS current−source (when active) and the MOSFET. Thus, Ptot = PDSS + PMOSFET. It is mandatory to properly manage the heat generated by losses. If no precaution is taken, risks exist to trigger the internal thermal shutdown (TSD). To help dissipating the heat, the PCB designer must foresee large copper areas around the package. When the package is surrounded by a surface approximately 200 mm2 of 35 m copper, the maximum power the device can thus evacuate is: 2 V clamp (V clamp ) (V out ) V f) N) L leak I leak 2 F sw (eq. 18) V clamp V ripple F sw R clamp (eq. 19) Vclamp is usually selected 50 − 80 V above the reflected value N x (Vout + Vf ). The diode needs to be a fast one and a MUR160 represents a good choice. One major drawback of the RCD network lies in its dependency upon the peak current. Worse case occurs when Ipeak and Vin are maximum and Vout is close to reach the steady−state value. Figure 47c: this option is probably the most expensive of all three but it offers the best protection degree. If you need a very precise clamping level, you must implement a zener diode or a TVS. There are little technology differences behind a standard zener diode and a TVS. However, the die P max + t jmax * t ambmax R JA (eq. 20) which gives around 862 mW for an ambient of 50°C and a maximum junction of 150°C. If the surface is not large enough, the RθJA is growing and the maximum power the device can evacuate decreases. Figure 48 gives a possible layout to help drop the thermal resistance. www.onsemi.com 22 NCP10670B, NCP10671B, NCP10672B Figure 48. A Possible PCB Arrangement to Reduce the Thermal Resistance Junction−to−Ambient Bill of Material: C1 Bulk capacitor, input DC voltage is connected to the capacitor C2, R1, D1 Clamping elements C3 Vcc capacitor OK1 Optocoupler ORDERING INFORMATION Shipping† Device Marking Frequency RDS(on) IIPK(0) Package Type NCP10670BD060R2G P10670060 60 kHz 34 100 mA NCP10670BD100R2G P10670100 100 kHz 34 100 mA SOIC−8 MISSING PIN 3 (Pb−Free) NCP10671BD060R2G P10671060 60 kHz 34 250 mA 2500 / Tape & Reel NCP10671BD100R2G P10671100 100 kHz 34 250 mA 2500 / Tape & Reel NCP10672BD060R2G P10672060 60 kHz 12 780 mA 2500 / Tape & Reel NCP10672BD100R2G P10672100 100 kHz 12 780 mA 2500 / Tape & Reel 2500 / Tape & Reel 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 23 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC8 MISSING PIN 3 CASE 751EV ISSUE O SCALE 1:1 D A 8 NOTE 5 F 0.10 C 5 NOTE 6 M E A1 E1 L2 0.20 C 1 L DETAIL A 4 7X NOTE 5 B b 0.12 M C SEATING PLANE C A-B D TOP VIEW 0.10 C A-B D DETAIL A 7X 0.10 C A DATE 19 SEP 2017 c e SIDE VIEW C END VIEW SEATING PLANE RECOMMENDED SOLDERING FOOTPRINT* NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.10mm IN EXCESS OF MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D & E1 DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15mm PER SIDE. DIMENSIONS D AND E1 ARE DETERMINED AT DATUM F. 5. DATUMS A AND B ARE TO BE DETERMINED AT DATUM F. 6. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. DIM A A1 b c D E E1 e L L2 M MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 5.80 6.20 3.80 4.00 1.27 BSC 0.40 1.27 0.25 BSC 0° 8° GENERIC MARKING DIAGRAM* 8 XXXXXXXXX ALYWX G G 7X 1.17 6.30 1 1 7X 1.27 PITCH 0.60 DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. XXXXX A L Y W G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G”, may or not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON76133G SOIC8 MISSING PIN 3 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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