NCP1079ABP100G

NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B Enhanced Off-line Switcher for Robust and Highly Efficient Power Supplies The NCP107xuz products integrate a fixed frequency current mode controller with a 700 V MOSFET. Available in a two different pin−out of the very common PDIP−7 package, the NCP107xuz offers a high level of integration, including soft−start, frequency−jittering, short−circuit protection, skip−cycle, a maximum peak current set−point, ramp compensation, and a dynamic self−supply (DSS, eliminating the need for an auxiliary winding). Unlike other monolithic solutions, the NCP107xuz is quiet by nature: during nominal load operation, the part switches at one of the available frequencies (65, 100 or 130 kHz). When the output power demand diminishes, the IC automatically enters frequency foldback mode and provides excellent efficiency at light loads. When the power demand reduces further, it enters into a skip mode to reduce the standby consumption down to a no load condition. Protection features include: a timer to detect an overload or a short−circuit event, Over−voltage Protection with auto−recovery. Ac input line voltage detection prevents lethal runaway in low input voltage conditions (Brown−out) as well as too high an input line (Ac line Over−voltage Protection). This also allows an Over−power Protection to compensate all internal delays in high input voltage conditions and optimize the maximum output current capability. For improved standby performance, the connection of an auxiliary winding stops the DSS operation and helps to reduce input power consumption below 50 mW at high line. www.onsemi.com MARKING DIAGRAMS PDIP−7 (PDIP−8 LESS PIN 6) CASE 626A PDIP−7 (PDIP−8 LESS PIN 3) CASE 626AS x u z y A WL Y, YY W, WW G P107xPuzy AWL YYWWG P107xPuzy AWL YYWWG = Power Version (5, 6, 7, 9) = Pin Connections (A, B) = 2nd level OCP enabled/disabled (A, B) = Oscillator Frequency 65, 100, 130 (A, B, C) = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information on page 31 of this data sheet. Features • Built−in 700 V MOSFET with RDS(ON) of 13.5 W • • • • • • • • • • Adjustable Brown−out Protection and OVP • 2nd Leading Edge Blanking – Current Protection (NCP1075uz), 4.8 W (NCP1076uz/77uz) and 2.9 W (NCP1079uz) Large Creepage Distance Between High Voltage Pins Current−mode Fixed Frequency Operation – 65 / 100 / 130 kHz Various Options for Maximum Peak Current: see below table Fixed Slope Compensation Skip−cycle Operation at Low Peak Currents Only Dynamic Self−supply: No Need for an Auxiliary Winding Internal 10 ms Soft−start Auto−recovery Output Short−circuit Protection with Timer−based Detection Auto−recovery Over−voltage Protection with Auxiliary Winding Operation © Semiconductor Components Industries, LLC, 2017 September, 2018 − Rev. 3 • • • • • (NCP107xuA version only) Over Power Protection Frequency Jittering for Better EMI Signature No Load Input Consumption < 50 mW Frequency Foldback to Improve Efficiency at Light Load These are Pb−free Devices Typical Applications • • • • 1 Auxiliary / Standby Isolated Power Supplies Major Home Appliances Power Supplies Power Meter SMPS Wide Input Industrial SMPS Publication Order Number: NCP1076A/D NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B PIN CONNECTIONS VCC GND FB BO/AC_OVP GND VCC BO/AC_OVP GND GND GND FB GND DRAIN DRAIN (Top View) PDIP−7 NCP107xB (Top View) PDIP−7 NCP107xA PIN FUNCTION DESCRIPTION Pin No PDIP 7 A PDIP 7 B Pin Name Function 1 2 VCC IC supply pin This pin is connected to an external capacitor. The VCC management includes an auto−recovery over−voltage protection. 2 8 BO/AC_OVP Brown−out / Ac Line Over−voltage protection Detects both input voltage conditions (Brown− out) and too high an input voltage (Ac line OVP). Do not leave this pin floating – if this pin is not used it should be directly connected do GND. 3 5 GND The IC Ground 4 1 FB Feedback signal input 5 4 DRAIN Drain connection 6 3 NC 7 6 GND The IC Ground 8 7 GND The IC Ground Pin Description By connecting an opto−coupler to this pin, the peak current set−point is adjusted accordingly to the output power demand. The internal drain MOSFET connection This un−connected pin ensures adequate creepage distance PRODUCTS INFOS & INDICATIVE MAXIMUM OUTPUT POWER 230 Vrms +15% 85−265 Vrms Product RDS(ON) IPK Adapter Open Frame Adapter Open Frame NCP1075uz 13.5 W 400 mA 8.5 W 14 W 6W 10 W NCP1076uz / NCP1077uz 4.8 W 800 mA 19 W 31 W 14 W 23 W NCP1079uz 2.9 W 1050 mA 25 W 41 W 18 W 30 W NOTE: Informative values only, with Tamb = 25°C, Tcase = 100°C, PDIP−7 package, Self−supply via Auxiliary winding and circuit mounted on minimum copper area as recommended. QUICK SELECTION TABLE Device Frequency [kHz] RDS(ON) [W] IPK [mA] NCP1075uz 65, 100, 130* 13.5 400 NCP1076uz 65, 100, 130* 4.8 650 NCP1077uz 65, 100, 130* 4.8 800 NCP1079uz 65, 100, 130* 2.9 1050 *NOTE: 130 kHz option available in pin connection B only www.onsemi.com 2 Package type PDIP−7 (Pb−Free) NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B Figure 1. Typical Isolated Application (Flyback Converter), Enable Brown−out, Ac Line OVP and OPP Functions Figure 2. Typical Isolated Application (Flyback Converter), Disabled Brown−out Function – Against Line Detection www.onsemi.com 3 NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B DRAIN VCC Management VCC VCC OVP Line detection enable ISTOP Line detection enable TSD Line Detection S BO enable Q AC OVP VFB(REF) DRV R Feedback control Slope compensation Sawtooth RFB(UP) LEB 1 FB Current set−point BO/AC_OVP OPP Soft−Start Ifreeze IPK(0) Brown−out BO enable AC OVP ISTOP Figure 3. Simplified Internal Circuit Architecture www.onsemi.com 4 Peak current protection GND NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B MAXIMUM RATINGS TABLE (All voltages related to GND terminal) Rating Power supply voltage, VCC pin, continuous voltage Symbol Value Unit VCC −0.3 to 20 V Voltage on all pins, except DRAIN and VCC pin Vinmax −0.3 to 10 V DRAIN voltage BVDSS −0.3 to 700 V ICC 15 mA Maximum Current into VCC pin Drain Current Peak during Transformer Saturation (TJ = 150°C): NCP1075uz NCP1076uz/77uz NCP1079uz IDS(PK) A 0.9 2.2 3.6 Drain Current Peak during Transformer Saturation (TJ = 25°C): NCP1075uz NCP1076uz/77uz NCP1079uz 1.5 3.9 6.4 Thermal Resistance Junction−to−Air – PDIP7 0.36 Sq. Inch RθJ−A 1.0 Sq. Inch Maximum Junction Temperature 77 °C/W 68 TJMAX Storage Temperature Range 150 °C −60 to +150 °C Human Body Model ESD Capability (All pins except HV pin) per JEDEC JESD22−A114F HBM 2 kV Human Body Model ESD Capability (Drain pin) per JEDEC JESD22−A114F HBM 1 kV Charged−Device Model ESD Capability per JEDEC JESD22−C101E CDM 1 kV MM 200 V Machine Model ESD Capability per JEDEC JESD22−A115−A Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78. 2. Maximum drain current IDS(PK) is obtained when the transformer saturates. It should not be mixed with short pulses that can be seen at turn on. Figure 4 below provides spike limits the device can tolerate. iD(t) < 1.5 x IDS(PK) < tLEB IDS(PK) Transformer Saturation t Figure 4. Spike Limits www.onsemi.com 5 NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VCC = 12 V unless otherwise noted) Symbol Rating Pin Min Typ Max Unit SUPPLY SECTION AND VCC MANAGEMENT VCC(ON) VCC increasing level at which the switcher starts operation 1 (2) 8.0 8.4 8.9 V VCC(MIN) VCC decreasing level at which the HV current source restarts 1 (2) 6.5 6.9 7.3 V VCC(OFF) VCC decreasing level at which the switcher stops operation (UVLO) 1 (2) 6.1 6.5 6.9 V VCC(reset) VCC voltage at which the internal latch is reset (Guaranteed by design) 1 (2) Internal IC consumption, MOSFET switching (fSW = 65 kHz) NCP1075uz NCP1076uz/77uz NCP1079uz 1 (2) Internal IC consumption, VFB is 0 V (No switching on MOSFET) 1 (2) ICC1 ICC(skip) 4 V mA − − − 1.10 1.26 1.40 − − − − 400 − mA POWER SWITCH CIRCUIT RDS(ON) BVDSS IDSS(OFF) tR tF Power Switch Circuit on−state resistance (IDRAIN = 50 mA) NCP1075uz TJ = 25°C TJ = 125°C NCP1076uz/77uz TJ = 25°C TJ = 125°C NCP1079uz TJ = 25°C TJ = 125°C 5 (4) Power Switch Circuit & Start−up breakdown voltage (IDRAIN(OFF) = 120 mA, TJ = 25°C) W − − 13.5 26.0 16.8 31.6 − − 4.8 9.3 6.8 11.6 − − 2.9 5.3 3.9 7.5 5 (4) 700 − − V Power Switch & Start−up breakdown voltage off−state leakage current TJ = 125°C (VDS = 700 V) 5 (4) − 85 − mA Switching characteristics (RL = 50 W, VDS set for IDRAIN = 0.7 x Ilim) Turn−on time (90% − 10%) Turn−off time (10% − 90%) 5 (4) − − 20 10 − − ns INTERNAL START−UP CURRENT SOURCE Istart1 High−voltage current source, VCC = VCC(ON) – 200 mV 5 (4) 4.0 9.0 12.0 mA Istart2 High−voltage current source, VCC = 0 V 5 (4) − 0.5 − mA VHV(MIN) Minimum start−up voltage, VCC = 0 V 5 (4) − 21 − V VCC(TH) VCC Transient level for Istart1 to Istart2 toggling point 1 (2) − 1.6 − V CURRENT COMPARATOR IPK IPK(0) Maximum internal current set−point at 50% duty−cycle FB pin open, TJ = 25°C NCP1075uz NCP1076uz NCP1077uz NCP1079uz Maximum internal current set−point at beginning of switching cycle FB pin open, BO/AC_OVP pin voltage v 0.8 V, TJ = 25°C NCP1075uz NCP1076uz NCP1077uz NCP1079uz mA − − − − − − − − 400 650 800 1050 − − − − mA − − − − 420 690 850 1110 470 765 940 1230 520 840 1030 1350 3. The final switch current is: IPK(0) / (Vin/LP + Sa) x Vin/LP + Vin/LP x tprop, with Sa the built−in slope compensation, Vin the input voltage, LP the primary inductor in a flyback, and tprop the propagation delay. 4. Oscillator frequency is measured with disabled jittering. www.onsemi.com 6 NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VCC = 12 V unless otherwise noted) Symbol Rating Pin Min Typ Max Unit CURRENT COMPARATOR IPKSW(65) IPKSW(100) IPKSW(130) IPK(OPP) Final switch current with a primary slope of 200 mA/ms, fSW = 65 kHz (Note 3) NCP1075uz NCP1076uz NCP1077uz NCP1079uz Final switch current with a primary slope of 200 mA/ms, fSW =100 kHz (Note 3) NCP1075uz NCP1076uz NCP1077uz NCP1079uz Final switch current with a primary slope of 200 mA/ms, fSW =130 kHz (Note 3) NCP1075uz NCP1076uz NCP1077uz NCP1079uz mA − − − − − − − − 450 710 860 1100 − − − − mA − − − − − − − − 440 685 825 1040 − − − − mA − − − − − − − − 450 685 820 1020 − − − − Maximum internal current set−point at beginning of switching cycle FB pin open, BO/AC_OVP pin voltage = 2.65 V, TJ = 25°C NCP1075uz NCP1076uz NCP1077uz NCP1079uz mA − − − − − − − − 375 610 750 985 − − − − tSS Soft−start duration (Guaranteed by design) − − 10 − ms tprop Propagation delay from current detection to drain OFF state − − 100 − ns tLEB1 Leading Edge Blanking Duration 1 − − 300 − ns tLEB2 Leading Edge Blanking Duration 2 (NCP107xuA version only) − − 100 − ns 59 65 71 kHz INTERNAL OSCILLATOR fOSC(65) Oscillation frequency, 65 kHz version, TJ = 25°C (Note 4) − fOSC(100) Oscillation frequency, 100 kHz version, TJ = 25°C (Note 4) − 90 100 110 kHz fOSC(130) Oscillation frequency, 130 kHz version, TJ = 25°C (Note 4) − 117 130 143 kHz fjitter Frequency jittering in percentage of fOSC − − ±6 − % fswing Jittering modulation frequency − − 300 − Hz DMAX Maximum duty−cycle − 64 68 72 % FEEDBACK SECTION IFB(fault) FB current for which Fault is detected 4 (1) − −35 − mA IFB100% FB current for which internal current set−point is 100% (IPK(0)) 4 (1) − −44 − mA IFB(freeze) FB current for which internal current set-point is Ifreeze 4 (1) − −90 − mA VFB(REF) Equivalent pull−up voltage in linear regulation range (Guaranteed by design) 4 (1) − 3.3 − V RFB(UP) Equivalent feedback resistor in linear regulation range (Guaranteed by design) 4 (1) − 19.5 − kΩ Start of frequency foldback FB pin current level 4 (1) − −68 − mA End of frequency foldback FB pin current level, fSW = fMIN 4 (1) − −100 − mA FREQUENCY FOLDBACK & SKIP IFBfold IFBfold(END) 3. The final switch current is: IPK(0) / (Vin/LP + Sa) x Vin/LP + Vin/LP x tprop, with Sa the built−in slope compensation, Vin the input voltage, LP the primary inductor in a flyback, and tprop the propagation delay. 4. Oscillator frequency is measured with disabled jittering. www.onsemi.com 7 NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VCC = 12 V unless otherwise noted) Symbol Rating Pin Min Typ Max Unit − 4 (1) 23 27 31 kHz − −120 − FREQUENCY FOLDBACK & SKIP fMIN IFB(skip) Ifreeze The frequency below which skip−cycle occurs, TJ = 25°C (Note 4) The FB pin current level to enter skip mode Internal minimum current set−point (IFB = IFB(freeze)) NCP1075uz NCP1076uz NCP1077uz NCP1079uz mA mA − − − − − − − − 165 270 330 430 − − − − The internal slope compensation @ 65 kHz: NCP1075uz NCP1076uz NCP1077uz NCP1079uz − − − − − − − − 9 15 18 23 − − − − The internal slope compensation @ 100 kHz: NCP1075uz NCP1076uz NCP1077uz NCP1079uz − − − − − − − − 14 23 28 36 − − − − The internal slope compensation @ 130 kHz: NCP1075uz NCP1076uz NCP1077uz NCP1079uz − − − − − − − − 18 30 36 46 − − − − Fault validation further to error flag assertion − 35 48 − ms OFF phase in fault mode − − 420 − ms 1 (5) 17.0 18.0 18.8 V SLOPE COMPENSATION Sa(65) Sa(100) Sa(130) mA/ms mA/ms mA/ms PROTECTIONS tSCP trecovery VOVP VCC voltage at which the switcher stops pulsing tOVP The filter of VCC OVP comparator − − 80 − ms VBO(EN) Brown−out level detection 2 (8) − 50 − mV VBO(ON) Brown−out level, the switcher starts pulsing, OPP starts to decrease IPK 2 (8) 0.76 0.80 0.84 V Brown−out hysteresis (Guaranteed by design) 2 (8) − 100 − mV OVP level when the switcher stops pulsing 2 (8) 2.755 2.900 3.045 V VACOVP(OFF) OVP level when the switcher starts pulsing 2 (8) 2.3 2.6 2.9 V − − 20 − ms VBO(HYST) VACOVP(ON) tBOfilter tBO VBO filter Brown−out timer VHV(EN) The drain pin voltage above which the MOSFET operates. Checked after one of the following events: TSD, UVLO, SCP, or VCC OVP mode, BO/AC_OVP pin = 0 V IPK(150) High current protection, percent of max limit IPK (NCP107xuA version only) − − 50 − ms 5 (4) 72 91 110 V − − 150 − % TEMPERATURE MANAGEMENT TSD Temperature shutdown (Guaranteed by design) − 150 − − °C TSDHYST Hysteresis in shutdown (Guaranteed by design) − − 20 − °C 3. The final switch current is: IPK(0) / (Vin/LP + Sa) x Vin/LP + Vin/LP x tprop, with Sa the built−in slope compensation, Vin the input voltage, LP the primary inductor in a flyback, and tprop the propagation delay. 4. Oscillator frequency is measured with disabled jittering. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 8 NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B TYPICAL CHARACTERISTICS 6.98 8.50 6.96 8.45 6.94 VCC(min) (V) VCC(on) (V) 6.92 8.40 8.35 6.90 6.88 6.86 6.84 8.30 6.82 8.25 −40 6.80 6.78 −40 −20 −20 0 20 40 60 80 100 120 0 20 40 60 80 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 5. VCC(on) vs. Temperature Figure 6. VCC(min) vs. Temperature 120 130 6.49 120 6.48 110 100 IDSS(off) (mA) VCC(off) (V) 6.47 6.46 6.45 90 80 70 60 6.44 50 6.43 6.42 −40 40 −20 0 20 40 60 80 100 30 −40 120 20 40 60 80 100 TEMPERATURE (°C) Figure 7. VCC(off) vs. Temperature Figure 8. IDSS(off) vs. Temperature 1.28 1.14 1.27 ICC1(1076uz/77uz) (mA) 1.12 ICC1(1075uz) (mA) 0 TEMPERATURE (°C) 1.16 1.10 1.08 1.06 1.04 120 1.26 1.25 1.24 1.23 1.22 1.21 1.20 1.02 1.00 −40 −20 1.19 −20 0 20 40 60 80 100 1.18 −40 120 −20 0 20 40 60 80 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 9. ICC1(1075uz) vs. Temperature Figure 10. ICC1(1076uz/77uz) vs. Temperature www.onsemi.com 9 120 NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B TYPICAL CHARACTERISTICS 1.39 460 1.37 450 IPK(0)1075uz (mA) ICC1(1079uz) (mA) 1.35 1.33 1.31 1.29 1.27 440 430 1.25 1.23 1.21 −40 −20 0 20 40 60 80 100 420 −40 120 40 60 80 100 Figure 11. ICC1(1079uz) vs. Temperature Figure 12. IPK(0)1075uz vs. Temperature 120 960 940 IPK(0)1077uz (mA) IPK(0)1076uz (mA) 20 TEMPERATURE (°C) 760 740 720 700 920 900 880 860 −20 0 20 40 60 80 100 840 −40 −20 120 0 20 40 60 80 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 13. IPK(0)1076uz vs. Temperature Figure 14. IPK(0)1077uz vs. Temperature 120 12 1200 10 ISTART1 (mA) 1160 IPK(0)1079uz (mA) 0 TEMPERATURE (°C) 780 680 −40 −20 1120 1080 1040 8 6 4 2 1000 −40 −20 0 20 40 60 80 100 0 −40 120 −20 0 20 40 60 80 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 15. IPK(0)1079uz vs. Temperature Figure 16. ISTART1 vs. Temperature www.onsemi.com 10 120 NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B TYPICAL CHARACTERISTICS 0.65 30 0.60 NCP1075uz 25 0.50 RDS(on) (W) ISTART2 (mA) 0.55 0.45 0.40 20 15 10 NCP1076uz/77uz 5 NCP1079uz 0.35 0.30 0.25 −40 −20 0 20 40 60 80 100 0 −40 120 −20 0 20 40 60 80 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 17. ISTART2 vs. Temperature Figure 18. RDS(on) vs. Temperature 66 120 99 98 65 fOSC100 (kHz) fOSC65 (kHz) 97 64 63 62 96 95 94 93 61 92 60 −40 −20 0 20 40 60 80 100 91 −40 −20 120 0 20 40 60 80 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 19. fOSC65 vs. Temperature Figure 20. fOSC100 vs. Temperature 131 120 67.5 129 DMAX (%) fOSC130 (kHz) 67.4 127 125 67.3 123 67.2 121 119 −40 −20 0 20 40 60 80 100 67.1 −40 −20 120 0 20 40 60 80 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 21. fOSC130 vs. Temperature Figure 22. DMAX vs. Temperature www.onsemi.com 11 120 NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B TYPICAL CHARACTERISTICS 28.0 380 375 tRECOVERY (ms) fMIN (kHz) 27.5 27.0 370 365 360 26.5 355 −20 0 20 40 60 80 100 350 −40 −20 120 20 40 60 80 100 TEMPERATURE (°C) Figure 23. fMIN vs. Temperature Figure 24. tRECOVERY vs. Temperature 52 18.4 51 18.3 50 18.2 49 120 18.1 18.0 48 47 −40 0 TEMPERATURE (°C) VOVP (V) tSCP (ms) 26.0 −40 −20 0 20 40 60 80 100 17.9 −40 120 −20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) Figure 26. VOVP vs. Temperature Figure 25. tSCP vs. Temperature 92 0.810 91 0.805 VBO(on) (V) VHV(en) (V) 90 89 0.800 0.795 88 0.790 87 86 −40 −20 0 20 40 60 80 100 0.785 −40 −20 120 TEMPERATURE (°C) 0 20 40 60 80 100 TEMPERATURE (°C) Figure 27. VHV(en) vs. Temperature Figure 28. VBO(on) vs. Temperature www.onsemi.com 12 120 NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B 2.99 2.620 2.97 2.615 2.95 VACOVP(off) (V) VACOVP(on) (V) TYPICAL CHARACTERISTICS 2.93 2.91 2.89 2.610 2.605 2.600 2.595 2.87 2.85 −40 −20 0 20 40 60 80 100 2.590 −40 −20 120 0 20 40 60 80 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 29. VACOVP(on) vs. Temperature Figure 30. VACOVP(off) vs. Temperature 120 10 1.100 NCP1079uz 8 IDS(pk) (A) 1.050 1.025 1.000 NCP1076uz/77uz 6 4 0.975 NCP1075uz 2 0.950 0.925 −40 −20 0 20 40 60 80 100 0 −40 −20 120 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) Figure 31. BVDSS/BVDSS(255C) vs. Temperature Figure 32. Drain Current Peak during Transformer Saturation vs. Junction Temperature 1.7 NCP1079uz 1.6 1.5 ICC1 (mA) BVDSS/BVDSS(25°C) [−] 1.075 NCP1076uz/77uz 1.4 1.3 NCP1075uz 1.2 1.1 1.0 7 8 9 10 11 12 13 14 VCC (V) Figure 33. ICC1 vs. VCC www.onsemi.com 13 15 16 17 140 NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B APPLICATION INFORMATION Introduction Thanks to ON Semiconductor Very High Voltage Integrated Circuit technology, the circuit hosts a high−voltage power MOSFET featuring a 13.5/4.8/2.9 W RDS(ON) – TJ = 25°C. An internal current source delivers the start−up current, necessary to crank the power supply. • Current−mode operation: The controller uses current−mode control architecture. • 700 V Power MOSFET: Thanks to ON Semiconductor Very High Voltage Integrated Circuit technology, the circuit hosts a high−voltage power MOSFET featuring a 4.8 and 2.9 W RDS(ON) – TJ = 25°C. This value lets the designer build a power supply up to 28 W operated on universal mains. An internal current source delivers the start−up current, necessary to crank the power supply. • Dynamic Self−Supply: This device could be used in an application without an auxiliary winding to provide supply voltage via an internal high−voltage current source. • Short−circuit protection: By permanently monitoring the feedback line activity, the IC is able to detect the presence of a short−circuit, immediately reducing the output power for a total system protection. A tSCP timer is started as soon as the feedback current is below threshold, IFB(fault), which indicates a maximum peak current condition. If at the end of this timer the fault is still present, then the device enters a safe, auto−recovery burst mode, affected by a fixed timer recurrence, trecovery. Once the short has disappeared, the controller resumes and goes back to normal operation. • Built−in VCC Over−Voltage Protection: When the auxiliary winding is used to bias the VCC pin (no DSS), an internal comparator is connected to VCC pin. In case the voltage on the pin exceeds the VOVP level (18 V typically), the controller immediately stops switching and awaits a full timer period (trecovery) before attempting to re−start. If the fault is gone, the controller resumes operation. If the fault is still there, e.g. in the case of a broken opto−coupler, the controller protects the load through a safe burst mode. • Line detection: An internal comparator monitors the drain voltage. If the drain voltage is lower than the internal threshold (VHV(EN)), the internal power switch • • • • • • • is inhibited. This avoids operating at too low an ac input. Line detection is active, when BO/AC_OVP pin is grounded. Brown−out detection and AC line Over−Voltage Protection: The BO/AC_OVP input monitors bulk voltage level via resistive divider and thus assures that the application is working only for designed bulk voltage. When BO/AC_OVP pin is connected to ground, Line detection is inhibited. Internal OPP: An internal function using the bulk voltage to program the maximum current reduction for a given input voltage. Internal OPP is active when BO/AC_OVP pin is connected via resistive divider to the bulk voltage. 2nd LEB (NCP107xuA only): Second level of current protection. If peak current is 150% max peak current limit, then the controller stops switching after three pulses and waits for an auto−recovery period (trecovery) before attempting to re−start. Frequency jittering: An internal low−frequency modulation signal varies the pace at which the oscillator frequency is modulated. This helps spreading out energy in conducted noise analysis. To improve the EMI signature at low power levels, the jittering remains active in frequency foldback mode. Soft−Start: A 10 ms soft−start ensures a smooth start−up sequence, reducing output overshoots. Frequency foldback capability: A continuous flow of pulses is not compatible with no−load/light−load standby power requirements. To excel in this domain, the controller observes the feedback current information and when it reaches a level of IFBfold, the oscillator then starts to reduce its switching frequency as the feedback current continues to increase (the power demand continues to reduce). It can go down to 27 kHz (typical) reached for a feedback level of IFBfold(END) (100 mA roughly). At this point, if the power continues to drop, the controller enters classical skip−cycle mode. Skip: If SMPS naturally exhibits a good efficiency at nominal load, they begin to be less efficient when the output power demand diminishes. By skipping un−needed switching cycles, the NCP107xuz drastically reduces the power wasted during light load conditions. www.onsemi.com 14 NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B Start−up Sequence V BULK When the power supply is first powered from the mains outlet, the internal current source (typically 9.2 mA) is biased and charges up the VCC capacitor from the drain pin. Once the voltage on this VCC capacitor reaches the VCC(ON) level (typically 8.4 V), the current source turns off and pulses are delivered by the output stage: the circuit is awake and activates the power MOSFET if the bulk voltage is above VHV(EN) level (Brown−in protection) or voltage on BO/AC_OVP pin is above VBO(ON) level (Brown−out protection). Figure 34 details the simplified internal circuitry. Being loaded by the circuit consumption, the voltage on the VCC capacitor goes down. When VCC is below VCC(MIN) level (7 V typically), it activates the internal current source to bring VCC toward VCC(ON) level and stops again: a cycle takes place whose low frequency depends on the VCC capacitor and the IC consumption. A 1.5 V ripple takes place on the VCC pin whose average value equals (VCC(ON) + VCC(MIN))/2. Figure 35 portrays a typical operation of the DSS. I1 R limit Istart 1 VCC DRAIN ICC 1 I2 V CC (ON ) V CC (MIN ) C VCC GND V OVP Figure 34. The Internal Arrangement of the Start−up Circuitry 9 8.4 V 8 7 6.9 V 6 VCC V [V] 5 Device Internal Pulses 4 3 VCC(TH) 2 1 0 0 1 2 3 Startup Duration 4 5 6 time [ms] Figure 35. The Charge / Discharge Cycle Over a 1 mF VCC Capacitor www.onsemi.com 15 7 8 NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B controller includes a novel circuitry made of two start−up levels, Istart1 and Istart2. At power−up, as long as VCC is below a 1.6 V level, the source delivers Istart2 (around 500 mA typical), then, when VCC reaches 1.6 V, the source smoothly transitions to Istart1 and delivers its nominal value. As a result, in case of short−circuit between VCC and GND, the power dissipation will drop to 370 x 500 x 10−6 = 185 mW. Figure 35 portrays this particular behavior. The first start−up period is calculated by the formula C x V = I x t, which implies a 1 x 10−6 x 1.6 6 / (500 x 10− ) = 3.2 ms start−up time for the first sequence. The second sequence is obtained by toggling the source to 8.9 mA with a ΔV of VCC(ON) − VCC(TH) = 8.4 V – 1.6 V = 6.8 V, which finally leads to a second start−up time of 1 x 10−6 x 6.8 / (8.9 x 10−3) = 0.76 ms. The total start−up time becomes 3.2 ms + 0.76 ms = 3.96 ms. Please note that this calculation is approximated by the presence of the knee in the vicinity of the transition. As one can see, even if there is auxiliary winding to provide energy for VCC, it happens that the device is still biased by DSS during start−up time or some fault mode when the voltage on auxiliary winding is not ready yet. The VCC capacitor shall be dimensioned to avoid VCC crosses VCC(OFF) level, which stops operation. The ΔV between VCC(MIN) and VCC(OFF) is 0.5 V. There is no current source to charge VCC capacitor when driver is on, i.e. drain voltage is close to zero. Hence the VCC capacitor can be calculated using C VCC w I CC1 @ D MAX f OSC @ DV (eq. 1) Take the 65 kHz device as an example. CVCC should be above −3 C VCC + 1.45 @ 10 3 @ 0.73 + 36 nF 59 @ 10 @ 0.5 A margin that covers the temperature drift and the voltage drop due to switching inside FET should be considered, and thus a capacitor above 0.1 mF is appropriate. The VCC capacitor has only a supply role and its value does not impact other parameters such as fault duration or the frequency sweep period for instance. As one can see on Figure 34, an internal OVP comparator protects the switcher against lethal VCC runaways. This situation can occur if the feedback loop opto−coupler fails, for instance, and you would like to protect the converter against an over−voltage event. In that case, the over−voltage protection (OVP) circuit immediately stops the output pulses for trecovery duration (420 ms typically). Then a new start−up attempt takes place to check whether the fault has disappeared or not. The OVP paragraph gives more design details on this particular section. Fault Condition – Output Short−circuit As soon as VCC reaches VCC(ON), drive pulses are internally enabled. If everything is correct, the auxiliary winding increases the voltage on the VCC pin as the output voltage rises. During the start−sequence, the controller smoothly ramps up the peak drain current to maximum setting, i.e. IPK, which is reached after a typical period of 10 ms. When the output voltage is not regulated, the current coming through FB pin is below IFBfault level (35 mA typically), which is not only during the start−up period but also anytime an overload occurs, an internal error flag is asserted, IpFlag, indicating that the system has reached its maximum current limit set−point. The assertion of this flag triggers a fault counter tSCP (48 ms typically). If at counter completion, IpFlag remains asserted, all driving pulses are stopped and the part stays off in trecovery duration (about 420 ms). A new attempt to re−start occurs and will last 48 ms providing the fault is still present. If the fault still affects the output, a safe burst mode is entered, affected by a low duty−cycle operation (11%). When the fault disappears, the power supply quickly resumes operation. Figure 36 depicts this particular mode: Fault Condition – Short−circuit on VCC In some fault situations, a short−circuit can purposely occur between VCC and GND. In high line conditions (VHV = 370 V dc) the current delivered by the start−up device will seriously increase the junction temperature. For instance, since Istart1 equals 4.9 mA (the min corresponds to the highest TJ), the device would dissipate 370 x 4.9 x 10−3 = 1.81 W. To avoid this situation, the www.onsemi.com 16 NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B VCC(ON) VCC(MIN) VCC IpFlag Open loop FB VFB 48 ms typ. Fault level Timer 420 ms typ. DRV internal Figure 36. In Case of Short−circuit or Overload, the NCP107xuz Protects Itself and the Power Supply Via a Low Frequency Burst Mode. The VCC is Maintained by the Current Source and Self−supplies the Controller. Auto−recovery Over−voltage Protection is also recommended to filter out the VCC line to avoid undesired OVP activations. Rlimit should be carefully selected to suppress false−triggers of the OVP as we discussed, but also to avoid disturbing the VCC in low / light load conditions. Self−supplying controllers in extremely low−standby applications often puzzles the designer. Actually, if a SMPS operated at nominal load can deliver an auxiliary voltage of an arbitrary 16 V (Vnom), this voltage can drop below 10 V (Vstby) when entering standby. This is because the recurrence of the switching pulses expands so much that the low frequency re−fueling rate of the VCC capacitor is not enough to keep a proper auxiliary voltage. The particular NCP107xuz arrangement offers a simple way to prevent output voltage runaway when the opto−coupler fails. As Figure 37 shows, a comparator monitors the VCC pin. If the auxiliary winding delivers too much voltage to the CVCC capacitor, then the controller considers an OVP situation and stops the internal drivers. When an OVP occurs, all switching pulses are permanently disabled. After trecovery delay, the circuit resumes operations. If the failure symptom still exists, e.g. feedback opto−coupler fails, the device keeps the auto−recovery OVP mode. We recommend the insertion of a resistor (Rlimit) between the auxiliary dc level and the VCC pin to protect the IC against high voltage spikes, which can damage the IC. It DRAIN V CC (ON ) = 8.4 V V CC (MIN ) = 6.9 V Istart 1 VCC Shut down Internal DRV CVCC 80 ms filter D1 Rlimit CAUX GND V OVP Figure 37. A More Detailed View of the NCP107xuz Offers Better Insight on How to Properly Wire an Auxiliary Winding www.onsemi.com 17 N AUX NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B VOVP VCC(ON) VCC(MIN) VCC I FB 48 ms typ. Fault level Timer 420 ms typ. DRV internal Figure 38. Describes the Main Signal Variations When the Part Operates in Auto−recovery OVP Soft−start OVP, TSD, Brown−out, etc. Figure 39 shows a typical operating waveform. The NCP107xuz features a novel patented structure which offers a better soft−start ramp, almost ignoring the start−up pedestal inherent to traditional current−mode supplies: The NCP107xuz features a 10 ms soft−start which reduces the power−on stress but also contributes to lower the output overshoot. Soft−start is running every time when IC starts switching. It means a first start, a new start after VCC VCC(ON) 0V (fresh PON) Max IPK DRAIN current 10 ms Figure 39. The 10 ms Soft−start Sequence www.onsemi.com 18 NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B Jittering Frequency jittering is a method used to soften the EMI signature by spreading the energy in the vicinity of the main switching component. The NCP107xuz offers a ±6% deviation of the nominal switching frequency. The sweeping sawtooth is internally generated and modulates the clock up and down with a fixed frequency of 300 Hz. Figure 40 shows the relationship between the jitter ramp and the frequency deviation. It is not possible to externally disable the jitter. Jitter ramp 68.9 kHz 65 kHz Internal sawtooth 61.1 kHz adjustable Figure 40. Modulation Effects on the Clock Signal by the Jittering Sawtooth Line Detection If the drain voltage is lower than the internal threshold VHV(EN) (91 V dc typically), the internal power switch is inhibited. This avoids operating at too low ac input. When BO/AC_OVP pin is grounded (voltage on this pin is below VBO(EN)) Figure 2, then an internal comparator monitors the drain voltage as recovering from one of the following situations: • Short−Circuit Protection, • VCC OVP is Confirmed, • UVLO • TSD Brown−out Function, Ac Line Over−voltage Protection The Brown−out circuitry offers a way to protect the application from operation under too low an input voltage. Below a given level, the controller blocks the output pulses, above it, it authorizes them. The internal circuitry, depicted by Figure 41, offers a way to observe the high−voltage (HV) rail. VBULK RUPPER RLOWER BO/AC_OVP 20μs filter CBO Line detection disable VBO(EN) 20μs filter tBO VBO(ON) 20μs filter AC OVP VAC(OVP) Figure 41. The Internal Brown−out Configuration www.onsemi.com 19 BO enable NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B higher than VBO(ON), switcher starts pulsing. If voltage falls down under VBO(OFF) − level VBO(ON) minus VBO(HYST), the switcher waits 50 ms and then stops pulsing, depicted by Figure 42. Bulk voltage at which IC starts switching is set by resistive divider. A resistive divider made of RUPPER and RLOWER, brings a portion of the HV rail on BO/AC_OVP pin. Below the VBO(EN) = 50 mV is the Brown−out function disabled, over the VBO(EN) Brown−out function is enable and against Line detection is inhibited. If voltage on BO/AC_OVP pin is VCC(ON) VCC(MIN) VCC VBO(ON) V BO(OFF) V BO/AC_OVP 50 ms Timer DRV internal Figure 42. Brown−out Input Functionality with 50 ms Timer www.onsemi.com 20 50 ms NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B The IC also includes over−voltage protection. If the voltage on BO/AC_OVP pin exceed VACOVP(ON), the switcher immediately stops pulsing until the voltage on BO/AC_OVP pin drops under VACOVP(OFF), depicted by Figure 43. VCC(ON) VCC(MIN) VCC VACOVP(ON) VAVOVP(OFF) VBO(ON) VBO(OFF) VBO/AC_OVP DRV internal Figure 43. Brown−out Input Functionality with Ac Line OVP Function Calculation of the resistive divider: V BO(ON) R LOWER + R UPPER V BULK * V BO(ON) (eq. 2) If we decide to start pulsing at VBULK(ON) = 113 V dc (80 V rms at ac mains): V BO(ON) R LOWER 0.8 + + [ 7.1 m 113 * 0.8 R UPPER V BULK(ON) * V BO(ON) We choose RLOWER = 100 kW 3 R UPPER + 100 @ 10−3 + 14 MW 7.1 @ 10 Then power losses on resistive divider for worst case (VBULK = 409 V dc) 2 U2 409 2 P+U@I+U + + + 12 mW R R UPPER ) R LOWER 14 @ 10 6 ) 100 @ 10 3 (eq. 3) For VBULK(ON) = 113 V dc will be over−voltage protection (voltage when the switcher stops pulsing): V BULK(OVP) + V ACOVP(ON) @ V BULK(ON) R LOWER ) R UPPER + V ACOVP(ON) @ + 29 @ 113 + 409 Vdc + 290 Vrms (eq. 4) 0.8 R LOWER V BO(ON) www.onsemi.com 21 NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B VCC(ON) VCC(MIN) VCC VBO(ON) VBO(OFF) VBO/AC_OVP 50 ms Timer Soft−start Soft−start Drain current Figure 44. Brown−out Functionality in Soft−start around 68 mA. At this point, the oscillator enters frequency foldback and reduces its switching frequency. The internal peak current set−point is following the feedback current information until its level reaches the minimal freezing level point of Ifreeze. Below this value, the peak current set−point is frozen to 30% of the IPK(0). The only way to further reduce the transmitted power is to diminish the operating frequency down to fMIN (27 kHz typically). This value is reached at a feedback current level of IFBfold(END) (100 mA typically). Below this point, if the output power continues to decrease, the part enters skip cycle for the best noise−free performance in no−load conditions. Figures 45 and 46 depict the adopted scheme for the part. If voltage on VCC pin is higher than VCC(ON) and voltage on BO/AC_OVP pin is higher than VBO(ON) then IC starts pulsing, drain current is increasing for 10 ms (Soft−start). Brown−out is inhibited during Soft−start, when Soft−start ended, Brown−out checked if is voltage on BO/AC_OVP pin higher than VBO(OFF). If the voltage is lower, timer count 50 ms and if the voltage don’t increase over VBO(OFF) then IC stops switching as one can see on Figure 44. Frequency Foldback The reduction of no−load standby power associated with the need for improving the efficiency, requires to change the traditional fixed−frequency type of operation. This device implements a switching frequency folback when the feedback current passes above a certain level, IFBfold, set www.onsemi.com 22 NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B 140 130 kHz Frequency [kHz] 120 100 kHz 100 65 kHz 80 60 40 20 0 50 60 70 80 90 100 IFB [mA] Figure 45. By Observing the Current on the FB pin, the Controller Reduces its Switching Frequency for an Improved Performance at Light Load Current set point [mA] 1400 NCP1079uz 1200 NCP1077uz 1000 NCP1076uz NCP1075uz 800 600 400 200 0 40 50 60 70 80 90 100 110 IFB [mA] Figure 46. IPK Set−point is Frozen at Lower Power Demand Feedback and Skip The FB pin operates linearly as the absolute value of feedback current (IFB) is above 40 mA. In this linear operating range, the dynamic resistance is 19.5 kW typically (RFB(UP)) and the effective pull up voltage is 3.3 V typically (VFB(REF)). When IFB is decreased, the FB voltage will increase to 3.3 V. www.onsemi.com 23 NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B Figure 47 depicts the skip mode block diagram. When the FB current information reaches IFB(skip), the internal clock to set the flip−flop is blanked and the internal consumption of the controller is decreased. The hysteresis of internal skip Jittering comparator is minimized to lower the ripple of the auxiliary voltage for VCC pin and VOUT of power supply during skip mode. It easies the design of VCC overload range. OSC V FB (REF ) S Foldback Q DRV stage R R FB (UP ) IFB (skip ) SKIP CS comparator FB Figure 47. Skip Cycle Schematic Over−power Protection This function lets you limit the maximum dc output current regardless of the operating input voltage. For a correct operation, the BO/AC_OVP pin must be connected via a resistive divider to observe the bulk voltage. OSC S Q MOSFET R Vramp + Vsense VBULK IFB IFB to CS setpoint RUPPER Ifreeze BO/AC_OVP IPK(0) IPK (0) IPK (OPP ) VBO (ON ) 2.65 V RLOWER Figure 48. The OPP Circuity Affects the Maximum Peak Current Set−point in Relationship to the Input Voltage. www.onsemi.com 24 NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B 1300 Max current set-point [mA] 1200 1100 1000 900 NCP1079uz 800 NCP1077uz 700 NCP1076uz 600 NCP1075uz 500 400 300 0 0.5 1.0 1.5 2.0 2.5 3.0 VBO/ACOVP [V] Figure 49. Current Set−point Dependence on BO/AC_OVP Pin Voltage There are several known ways to implement Over−power Protection (OPP), all suffering from particular problems. These problems range from the added consumption burden on the converter or the skip−cycle disturbance brought by the current−sense offset. In this case is added consumption due to resistive divider (Equation 2). Maximum peak current is reduced internally according to bulk voltage. When VBO(OPP) is maximum, the peak current set−point is reduced by 10%. Bulk voltage at which will be maximum current peak reduced by 20% (10% in NCP1075uz): (eq. 5) ) R UPPER R 3 6 V BULK(OPP) + V BO(OPP) @ + V BO(OPP) @ LOWER + 2.65 @ 100 @ 10 ) 143 @ 10 + 375 Vdc + 265 Vrms V BO(ON) R LOWER 100 @ 10 V BULK(ON) www.onsemi.com 25 NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B Second LEB – Peak Current Protection (NCP107xuA only) Slope Compensation and IPK Set−point In order to let the NCP107xuz operate in CCM with a duty−cycle above 50%, a fixed slope compensation is internally applied to the current−mode control. Below appears a table of the slope compensation level, the initial current set−point, and the final current set−point of different versions of switcher. There is a second level of current protection with 100 ns propagation delay to prevent IC against high peak current. If peak current is 150% max peak current limit, then the controller stops switching after three pulses and waits for an auto−recovery period (trecovery) before attempting to re−start. NCP1075uz fSW [kHz] 65 Sa [mA/µs] 9 NCP1076uz 100 130 65 14 18 15 NCP1077uz 100 130 65 23 30 18 NCP1079uz 100 130 65 28 36 24 100 130 37 46 IPK (Duty−cycle = 50%) [mA] 400 600 800 1050 IPK(0) [mA] 470 765 940 1230 Figure 50 depicts the variation of IPK set−point vs. the power switcher duty ratio, which is caused by the internal ramp compensation. 1400 IIPK set-point [mA] 1200 1000 800 NCP1079uz 600 NCP1077uz NCP1076uz 400 NCP1075uz 200 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 Duty Ratio [%] Figure 50. IPK Set−point varies with Power Switch On Time, which is Caused by the Ramp Compensation www.onsemi.com 26 NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B Design Procedure maximum voltage that can be reflected during tF As a result, the flyback voltage which is reflected on the drain at the switch opening cannot be larger than the input voltage. When selecting components, you thus must adopt a turn ratio which adheres to the following equation: The design of an SMPS around a monolithic device does not differ from that of a standard circuit using a controller and a MOSFET. However, one needs to be aware of certain characteristics specific of monolithic devices. Let us follow the steps: VIN,MIN = 90 V rms or 127 V dc once rectified, assuming a low bulk ripple VIN,MAX = 265 V rms or 375 V dc VOUT = 12 V POUT = 10 W Operating mode is CCM η = 0.8 1. The lateral MOSFET body−diode shall never be forward biased, either during start−up (because of a large leakage inductance) or in normal operation, depicted by Figure 51. This condition sets the N @ ǒV OUT ) V FǓ t V IN,MIN (eq. 6) 2. In our case, since we operate from a 127 V dc rail while delivering 12 V, we can select a reflected voltage of 120 V dc maximum. Therefore, the turn ratio Np:Ns must be smaller than V reflect + 120 + 9.6 or Np : Ns t 9.6 12 ) 0.5 V OUT ) V F Here we choose N = 8 in this case. We will see later on how it affects the calculation. Figure 51. The Drain−Source Wave Shall Always be Positive 3. Lateral MOSFETs have a poorly doped body−diode which naturally limits their ability to sustain the avalanche. A traditional RCD clamping network shall thus be installed to protect the MOSFET. In some low power applications, a simple capacitor can also be used since IL IPEAK ILavg DIL IVALLEY V DRAIN,MAX + V IN ) N @ ǒV OUT ) V FǓ ) I PEAK @ L F (eq. 7) C TOT where LF is the leakage inductance, CTOT the total capacitance at the drain node (which is increased by the capacitor you will wire between drain and source), N the NP:NS turn ratio, VOUT the output voltage, VF the secondary diode forward drop and finally, IPEAK the maximum peak current. Worse case occurs when the SMPS is very close to regulation, e.g. the VOUT target is almost reached and IPEAK is still pushed to the maximum. For this Iavg t DTsw Ǹ Tsw Figure 52. Primary Inductance Current Evolution in CCM www.onsemi.com 27 NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B design, we have selected our maximum voltage around 650 V (at VIN = 375 V dc). This voltage is given by the RCD clamp installed from the drain to the bulk voltage. We will see how to calculate it later on. 4. Calculate the maximum operating duty−cycle for this flyback converter operated in CCM: D MAX + N @ ǒV OUT ) V FǓ N @ ǒV OUT ) V FǓ ) V IN,MIN 1 VIN,MIN 1) + 5. To obtain the primary inductance, we have the choice between two equations: L+ where (eq. 8) • + 0.44 N@(VOUT)VF) • ǒV IN @ DǓ 2 f SW @ K @ P IN K+ DI L I Lavg (eq. 9) (eq. 10) and defines the amount of ripple we want in CCM, depicted by Figure 51. Small K: deep CCM, implying a large primary inductance, a low bandwidth and a large leakage inductance. Large K: approaching DCM where the conduction losses are worse, but smaller inductance, leading to a better leakage inductance. From Equation 9, a K factor of 1 (50% ripple), gives an inductance of: 2 L+ (127 @ 0.44) + 3.8 mH 65 k @ 1 @ 12.75 DI L + V IN @ D 127 @ 0.44 + + 223 mA L @ f SW 3.8 @ 10 −3 @ 65 @ 10 3 (eq. 11) peak−to−peak The peak current can be evaluated to be: I PEAK + I avg DI L −3 −3 ) + 98 @ 10 ) 223 @ 10 + 335 mA 2 0.44 2 D (eq. 12) On IL, ILavg can also be calculated I Lavg + I PEAK * DI L −3 + 335 @ 10 −3 * 223 @ 10 + 223 mA 2 2 (eq. 13) 6. Based on the above numbers, we can now evaluate the conduction losses: I D,RMS + Ǹǒ D I PEAK 2 * I PEAK @ DI L ) Ǔ Ǹ DI L 2 + 3 ǒ 0.44 0.335 2 * 0.335 @ 0.223 ) 0.223 3 2 Ǔ + 154 mA (eq. 14) If we take the maximum RDS(ON) for a 125°C junction temperature, i.e. 10.1 W, then conduction losses worse case are: P COND + I D,RMS 2 @ R DS(ON) + ǒ154 @ 10 −3Ǔ @ 13.6 + 323 mW 2 (eq. 15) 7. Off−time and on−time switching losses can be estimated based on the following calculations: P OFF + I PEAK @ (V BULK ) V CLAMP) @ t F 0.335 @ (127 ) 120 @ 2) @ 10 @ 10 −9 + + 40 mW 2 @ T SW 2 @ 15.4 @ 10 −6 (eq. 16) Where, assume the VCLAMP is equal to 2 times of reflected voltage. P ON + I VALLEY @ ǒV BULK ) N @ (V OUT ) V F)Ǔ @ t R 6 @ T SW + 0.112 @ (127 ) 100) @ 20 @ 10 −9 + 5.5 mW 6 @ 15.4 @ 10 −6 (eq. 17) It is noted that the overlap of voltage and current seen on MOSFET during turning on and off duration is dependent on the snubber and parasitic capacitance seen from drain pin. Therefore the tF and tR in Equations 16 and 17 have to be modified after measuring on the bench. 8. The theoretical total power is then P MOSFET + 323 ) 40 ) 5.5 + 368.5 mW 9. If the NCP107xuz operates at DSS mode, then the losses caused by DSS mode should be counted as losses of this device on the following calculation: P DSS + I CC1 @ V IN,MAX + 1.5 @ 10 −3 @ 375 + 563 mW www.onsemi.com 28 (eq. 18) NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B MOSFET Protection As in any flyback design, it is important to limit the drain excursion to a safe value, e.g. below the MOSFET BVDSS which is 700 V. Figure 53 a−b−c present possible implementations: Figure 53. Different Options to Clamp the Leakage Spike Figure 53a: the simple capacitor limits the voltage according to the lateral MOSFET body−diode shall never be forward biased, either during start−up (because of a large leakage inductance) or in normal operation as shown by Figure 51. This condition sets the maximum voltage that can be reflected during tF. As a result, the flyback voltage which is reflected on the drain at the switch opening cannot be larger than the input voltage. When selecting components, you must adopt a turn ratio which adheres to the following Equation 6. This option is only valid for low power applications, e.g. below 5 W, otherwise chances exist to destroy the MOSFET. After evaluating the leakage inductance, you can compute C with (Equation 7). Typical values are between 100 pF and up to 470 pF. Large capacitors increase capacitive losses... Figure 53b: the most standard circuitry is called the RCD network. You calculate RCLAMP and CCLAMP using the following formulae: R CLAMP + C CLAMP + and a MUR160 represents a good choice. One major drawback of the RCD network lies in its dependency upon the peak current. Worse case occurs when IPEAK and VIN are maximum and VOUT is close to reach the steady−state value. Figure 53c: this option is probably the most expensive of all three but it offers the best protection degree. If you need a very precise clamping level, you must implement a Zener diode or a TVS. There are little technology differences behind a standard Zener diode and a TVS. However, the die area is far bigger for a transient suppressor than that of Zener. A 5 W Zener diode like the 1N5388B will accept 180 W peak power if it lasts less than 8.3 ms. If the peak current in the worse case (e.g. when the PWM circuit maximum current limit works) multiplied by the nominal zener voltage exceeds these 180 W, then the diode will be destroyed when the supply experiences overloads. A transient suppressor like the P6KE200 still dissipates 5 W of continuous power but is able to accept surges up to 600 W @ 1 ms. Select the Zener or TVS clamping level between 40 to 80 volts above the reflected output voltage when the supply is heavily loaded. As a good design practice, it is recommended to implement one of this protection to ensure a maximum drain pin voltage below 650 V (to have some margin between drain pin voltage and BVDSS) during most stringent operating conditions (high VIN and peak power condition). 2 @ V CLAMP ǒV CLAMP ) (V OUT ) V F) @ NǓ L LEAK @ I LEAK 2 @ f SW V CLAMP V RIPPLE @ f SW @ R CLAMP (eq. 19) (eq. 20) VCLAMP is usually selected 50−80 V above the reflected value N x (VOUT + VF ). The diode needs to be a fast one www.onsemi.com 29 NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B Power Dissipation and Heatsinking The NCP107xuz welcomes two dissipating terms, the DSS current−source (when active) and the MOSFET. Thus, PTOT = PDSS + PMOSFET. It is mandatory to properly manage the heat generated by losses. If no precaution is taken, risks exist to trigger the internal thermal shutdown (TSD). To help dissipating the heat, the PCB designer must foresee large copper areas around the package. Take the PDIP−7 package as an example, when surrounded by a surface approximately 200 mm2 of 35 mm copper, the maximum power the device can thus evacuate is: P MAX + T J(max) * T AMB(max) R qJA (eq. 21) which gives around 1300 mW for an ambient of 50°C and a maximum junction of 150°C. If the surface is not large enough, the RqJA is growing and the maximum power the device can evacuate decreases. Figure 54 gives a possible layout to help drop the thermal resistance. Figure 54. A Possible PCB Arrangement to Reduce the Thermal Resistance Junction−to−Ambient Bill of Material: C1 C2, R1, D1 C3 OK1 www.onsemi.com 30 Bulk capacitor, input dc voltage is connected to the capacitor Clamping elements VCC capacitor Opto−coupler NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B ORDERING INFORMATION Device Frequency [kHz] RDS(ON) [W] IPK [mA] 2nd level OCP Package Type NCP1075AAP065G 65 13.5 400 enabled PDIP8 (Less pin#6) NCP1075AAP100G 100 13.5 400 enabled PDIP8 (Less pin#6) NCP1075BAP065G 65 13.5 400 enabled PDIP8 (Less pin#3) NCP1075BAP100G 100 13.5 400 enabled PDIP8 (Less pin#3) NCP1075BAP130G 130 13.5 400 enabled PDIP8 (Less pin#3) NCP1076AAP065G 65 4.8 650 enabled PDIP8 (Less pin#6) NCP1076AAP100G 100 4.8 650 enabled PDIP8 (Less pin#6) NCP1076BAP065G 65 4.8 650 enabled PDIP8 (Less pin#3) NCP1076BAP100G 100 4.8 650 enabled PDIP8 (Less pin#3) NCP1076BAP130G 130 4.8 650 enabled PDIP8 (Less pin#3) NCP1077AAP065G 65 4.8 800 enabled PDIP8 (Less pin#6) NCP1077AAP100G 100 4.8 800 enabled PDIP8 (Less pin#6) NCP1077BAP065G 65 4.8 800 enabled PDIP8 (Less pin#3) NCP1077BAP100G 100 4.8 800 enabled PDIP8 (Less pin#3) NCP1077BAP130G 130 4.8 800 enabled PDIP8 (Less pin#3) NCP1079AAP065G 65 2.9 1050 enabled PDIP8 (Less pin#6) NCP1079AAP100G 100 2.9 1050 enabled PDIP8 (Less pin#6) NCP1079BAP065G 65 2.9 1050 enabled PDIP8 (Less pin#3) NCP1079BAP100G 100 2.9 1050 enabled PDIP8 (Less pin#3) NCP1079BAP130G 130 2.9 1050 enabled PDIP8 (Less pin#3) NCP1075ABP065G 65 13.5 400 disabled PDIP8 (Less pin#6) NCP1075ABP100G 100 13.5 400 disabled PDIP8 (Less pin#6) NCP1075BBP065G 65 13.5 400 disabled PDIP8 (Less pin#3) NCP1075BBP100G 100 13.5 400 disabled PDIP8 (Less pin#3) NCP1075BBP130G 130 13.5 400 disabled PDIP8 (Less pin#3) NCP1076ABP065G 65 4.8 650 disabled PDIP8 (Less pin#6) NCP1076ABP100G 100 4.8 650 disabled PDIP8 (Less pin#6) NCP1076BBP065G 65 4.8 650 disabled PDIP8 (Less pin#3) NCP1076BBP100G 100 4.8 650 disabled PDIP8 (Less pin#3) NCP1076BBP130G 130 4.8 650 disabled PDIP8 (Less pin#3) NCP1077ABP065G 65 4.8 800 disabled PDIP8 (Less pin#6) NCP1077ABP100G 100 4.8 800 disabled PDIP8 (Less pin#6) NCP1077BBP065G 65 4.8 800 disabled PDIP8 (Less pin#3) NCP1077BBP100G 100 4.8 800 disabled PDIP8 (Less pin#3) NCP1077BBP130G 130 4.8 800 disabled PDIP8 (Less pin#3) NCP1079ABP065G 65 2.9 1050 disabled PDIP8 (Less pin#6) NCP1079ABP100G 100 2.9 1050 disabled PDIP8 (Less pin#6) NCP1079BBP065G 65 2.9 1050 disabled PDIP8 (Less pin#3) NCP1079BBP100G 100 2.9 1050 disabled PDIP8 (Less pin#3) NCP1079BBP130G 130 2.9 1050 disabled PDIP8 (Less pin#3) www.onsemi.com 31 Shipping 50 Units / Rail MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS PDIP−7 (PDIP−8 LESS PIN 6) CASE 626A ISSUE C DATE 22 APR 2015 SCALE 1:1 D A E H 8 5 1 4 E1 NOTE 8 b2 c B END VIEW TOP VIEW WITH LEADS CONSTRAINED NOTE 5 A2 A e/2 NOTE 3 L SEATING PLANE A1 C D1 M e 8X SIDE VIEW b 0.010 eB END VIEW M C A M B M NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3. 4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE NOT TO EXCEED 0.10 INCH. 5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR TO DATUM C. 6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE LEADS UNCONSTRAINED. 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE LEADS, WHERE THE LEADS EXIT THE BODY. 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE CORNERS). DIM A A1 A2 b b2 C D D1 E E1 e eB L M INCHES MIN MAX −−−− 0.210 0.015 −−−− 0.115 0.195 0.014 0.022 0.060 TYP 0.008 0.014 0.355 0.400 0.005 −−−− 0.300 0.325 0.240 0.280 0.100 BSC −−−− 0.430 0.115 0.150 −−−− 10 ° MILLIMETERS MIN MAX −−− 5.33 0.38 −−− 2.92 4.95 0.35 0.56 1.52 TYP 0.20 0.36 9.02 10.16 0.13 −−− 7.62 8.26 6.10 7.11 2.54 BSC −−− 10.92 2.92 3.81 −−− 10 ° NOTE 6 GENERIC MARKING DIAGRAM* XXXXXXXXX AWL YYWWG XXXX A WL YY WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. DOCUMENT NUMBER: DESCRIPTION: 98AON11774D Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PDIP−7 (PDIP−8 LESS PIN 6) PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS PDIP8 LESS PIN 3 CASE 626AS ISSUE O DATE 23 OCT 2015 SCALE 1:1 D A 8 E H 5 A3 E1 1 4 NOTE 6 b2 c B END VIEW TOP VIEW WITH LEADS CONSTRAINED NOTE 5 e/2 A NOTE 3 L SEATING PLANE A1 C D1 7X e SIDE VIEW b 0.010 M END VIEW M C A M B M NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3. 4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE NOT TO EXCEED 0.10 INCH. 5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR TO DATUM C. 6. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE CORNERS). DIM A A1 A3 b b2 c D D1 E E1 e L M INCHES MIN MAX 0.155 0.175 0.020 0.040 0.015 BSC 0.015 0.020 0.056 0.064 0.008 0.012 0.365 0.369 0.005 0.080 0.300 0.325 0.244 0.260 0.100 BSC 0.115 0.135 −−−− 10 ° MILLIMETERS MIN MAX 3.94 4.45 0.51 1.02 0.38 BSC 0.38 0.50 1.42 1.63 0.20 0.30 9.27 9.37 0.13 2.03 7.62 8.25 6.20 6.60 2.54 BSC 2.92 3.43 −−− 10 ° GENERIC MARKING DIAGRAM* XXXXXXXXX AWL YYWWG XXXX A WL YY WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. DOCUMENT NUMBER: DESCRIPTION: 98AON06190G PDIP8 LESS PIN 3 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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