NCP1080DER2G

NCP1080 Integrated PoE-PD & DC-DC Converter Controller Introduction The NCP1080 is a member of ON Semiconductor’s Power over Ethernet Powered Device (PoE−PD) product family and represents a robust, flexible and highly integrated solution targeting demanding Ethernet applications. It combines in a single unit an enhanced PoE−PD interface fully supporting the IEEE802.3af specification and a flexible and configurable DC−DC converter controller. The NCP1080’s exceptional capabilities offer new opportunities for the design of products powered directly over Ethernet lines, eliminating the need for local power adaptors or power supplies and drastically reducing the overall installation and maintenance cost. ON Semiconductor’s unique manufacturing process and design enhancements allow the NCP1080 to deliver up to 13 W of regulated power to support PoE applications according to the IEEE802.3af standard. This device leverages the significant cost advantages of PoE−enabled systems to a broad spectrum of products in markets such as VoIP phones, wireless LAN access point, security cameras, point of sales terminals, RFID readers, industrial ethernet devices, etc. The integrated current mode DC−DC controller facilitates isolated and non−isolated fly−back, forward and buck converter topologies. It has all the features necessary for a flexible, robust and highly efficient design including programmable switching frequency, duty cycle up to 80 percent, slope compensation, and soft start−up. The NCP1080 is fabricated in a robust high voltage process and integrates a rugged vertical N−channel DMOS with a low loss current sense technique suitable for the most demanding environments and capable of withstanding harsh environments such as hot swap and cable ESD events. The NCP1080 complements ON Semiconductor’s ASSP portfolio in communications and industrial devices and can be combined with other high−voltage interfacing devices to offer complete solutions to the communication, industrial and security markets. Features Powered Device Interface http://onsemi.com TSSOP−20 EP DE SUFFIX CASE 948AB NCP1080 = Specific Device Code XXXX = Date Code Y = Assembly Location ZZ = Traceability Code ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. • • • • • • • • • Fully supports IEEE802.3af standard Regulated power output up to 13 W Programmable classification current Adjustable under voltage lock out Programmable inrush current limit Programmable operational current limit up to 500 mA Over−temperature protection Industrial temperature range −40°C to 85°C with full operation up to 150°C junction temperature 0.6 ohm hot−swap pass−switch with low loss current sense technique • Vertical N−channel DMOS pass−switch offers the robustness of discrete MOSFETs with integrated temperature control DC−DC Converter Controller • Current mode control • Supports isolated and non−isolated DC−DC converter • • • • applications Internal voltage regulators Wide duty cycle range with internal slope compensation circuitry Programmable oscillator frequency Programmable soft−start time © Semiconductor Components Industries, LLC, 2008 September, 2008 − Rev. 4 1 Publication Order Number: NCP1080/D NCP1080 PIN DIAGRAM VPORTP CLASS UVLO INRUSH ILIM1 VPORTN1 RTN VPORTN2 TEST1 TEST2 1 SS FB COMP VDDL VDDH GATE ARTN NC CS OSC Exposed Pad (Top View) Ordering Information Part Number NCP1080DEG NCP1080DER2G Package TSSOP−20 EP (Pb−Free) TSSOP−20 EP (Pb−Free) Shipping Configuration† 74 units / Tube 2500 / Tape & Reel Temperature Range −40°C to 85°C −40°C to 85°C †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. VPORTP DETECTION INTERNAL SUPPLY & BANDGAP THERMAL SHUT DOWN VDDH VDDH VDDL VDDL CLASS CLASSIFICATION VDDL VDDL 5 mA SS UVLO UVLO VPORT MONITOR DC−DC CONVERTER CONTROL VDDL 5K 1.2 V FB COMP CS INRUSH ILIM1 INRUSH ILIM1 OSC HOT SWAP SWITCH CONTROL & CURRENT LIMIT BLOCKS VDDH OSC GATE NC ARTN VPORTN1,2 RTN Figure 1. NCP1080 Block Diagram http://onsemi.com 2 NCP1080 Simplified Application Diagrams RJ− 45 Rclass VPORTP CLASS VDDH Cvddh Cpd T1 D1 Voutput Z_line DB1 Cline Data Pairs Rinrush INRUSH VDDL NCP1080 Cvddl LD1 Rd1 M1 Rilim1 R1 Cload ILIM1 UVLO GATE CS FB ARTN RTN R2 TEST2 TEST1 VPORTN1 COMP OSC VPORTN2 Css Rslope Rcs R5 OC1 C2 Optocoupler R3 C1 SS Spare Pairs DB2 Rosc Z1 R4 Figure 2. Isolated Fly−back Converter Figure 2 shows the integrated PoE−PD switch and DC−DC controller configured to work in a fully isolated application. The output voltage regulation is accomplished with an external opto−coupler and a shunt regulator (Z1). VPORTP Rclass Cpd RJ− 45 CLASS VDDH T1 Cvddh Voutput Z_line DB1 Cline Data Pairs Rinrush INRUSH VDDL NCP1080 Cvddl LD1 Rd1 M1 R3 Cload Rilim1 R1 ILIM1 UVLO R2 GATE CS FB ARTN RTN COMP OSC SS TEST2 TEST1 VPORTN1 VPORTN2 Rslope R4 Rcs Spare Pairs DB2 Css Rosc C1comp Rcomp C2comp Figure 3. Non−Isolated Fly−back Converter Figure 3 shows the integrated PoE−PD and DC−DC controller configured in a non−isolated fly−back configuration. A compensation network is inserted between the FB and the COMP pin for overall stability of the feedback loop. http://onsemi.com 3 NCP1080 Simplified Application Diagrams D2 T1 RJ− 45 Rclass VPORTP CLASS VDDH R5 D1 Cpd Voutput Z_line DB1 Cline Data Pairs Rinrush INRUSH Cvddh VDDL NCP1080 Cvddl LD1 Rd1 M1 R3 Cload Rilim1 R1 ILIM1 UVLO R2 TEST2 TEST1 COMP VPORTN1 VPORTN2 OSC SS GATE CS FB ARTN RTN Rslope R4 Rcs Spare Pairs DB2 Css Rosc C1comp Rcomp C2comp Figure 4. Non−Isolated Fly−back with Extra Winding Figure 4 shows the same non−isolated fly−back configuration as Figure 3, but adds a 12 V auxiliary bias winding on the transformer to provide power to the NCP1080 DC−DC controller via its VDDH pin. This topology shuts off the current flowing from VPORTP to VDDH and therefore reduces the internal power dissipation of the PD, resulting in higher overall power efficiency. D3 Cpd T1 L1 RJ− 45 VPORTP Rclass D1 Voutput CLASS VDDH Cvddh D2 R3 Z_line DB1 Cline Data Pairs Rinrush INRUSH VDDL NCP1080 Cvddl LD1 Cload Rd1 M1 Rilim1 R1 ILIM1 UVLO R2 GATE CS FB ARTN RTN COMP OSC SS TEST2 TEST1 VPORTN1 VPORTN2 Rslope R4 Rcs Spare Pairs DB2 Css Rosc C1comp Rcomp C2comp Figure 5. Non−Isolated Forward Converter Figure 5 shows the NCP1080 used in a non−isolated forward topology. http://onsemi.com 4 NCP1080 Table 1. Pin Descriptions Name VPORTP VPORTN1 VPORTN2 RTN ARTN VDDH Pin No. 1 6,8 7 14 16 Type Supply Ground Ground Ground Supply Description Positive input power. Voltage with respect to VPORTN1,2 Negative input power. Connected to the source of the internal pass−switch. DC−DC controller power return. Connected to the drain of the internal pass−switch. It must be connected to ARTN. This pin is also the drain of the internal pass−switch. DC−DC controller ground pin. Must be connected to RTN as a single point ground connection for improved noise immunity. Output of the 9 V LDO internal regulator. Voltage with respect to ARTN. Supplies the internal gate driver. VDDH must be bypassed to ARTN with a 1 mF or 2.2 mF ceramic capacitor with low ESR. Output of the 3.3 V LDO internal regulator. Voltage with respect to ARTN. This pin can be used to bias an external low−power LED (1 mA max.) connected to ARTN, and can also be used to add extra biasing current in the external opto−coupler. VDDL must be bypassed to ARTN with a 330 nF or 470 nF ceramic capacitor with low ESR. Classification current programming pin. Connect a resistor between CLASS and VPORTN1,2. Inrush current limit programming pin. Connect a resistor between INRUSH and VPORTN1,2. Operational current limit programming pin. Connect a resistor between ILIM1 and VPORTN1,2. DC−DC controller under−voltage lockout input. Voltage with respect to VPORTN1,2. Connect a resistor−divider from VPORTP to UVLO to VPORTN1,2 to set an external UVLO threshold. DC−DC controller gate driver output pin. Internal oscillator frequency programming pin. Connect a resistor between OSC and ARTN. No connect pin, must not be connected. I/O Output of the internal error amplifier of the DC−DC controller. COMP is pulled−up internally to VDDL with a 5 kW resistor. In isolated applications, COMP is connected to the collector of the opto−coupler. Voltage with respect to ARTN. DC−DC controller inverting input of the internal error amplifier. In isolated applications, the pin should be strapped to ARTN to disable the internal error amplifier. Current−sense input for the DC−DC controller. Voltage with respect to ARTN. Soft−start input for the DC−DC controller. A capacitor between SS and ARTN determines the soft−start timing. Digital test pin must always be connected to VPORTN1,2. Digital test pin must always be connected to VPORTN1,2. Exposed pad. Connected to VPORTN1,2 ground. VDDL 17 Supply CLASS INRUSH ILIM1 UVLO GATE OSC NC COMP 2 4 5 3 15 11 13 18 Input Input Input Input Output Input FB CS SS TEST1 TEST2 EP 19 12 20 9 10 Input Input Input Input Input http://onsemi.com 5 NCP1080 Table 2. Absolute Maximum Ratings Symbol VPORTP RTN ARTN VDDH VDDL CLASS INRUSH ILIM1 UVLO OSC COMP FB CS SS NC TEST1 TEST2 Ta Tj Tj−TSD Tstg TθJA ESD−HBM ESD−CDM ESD−MM LU ESD−SYS Parameter Input power supply Analog ground supply 2 Internal regulator output Internal regulator output Analog output Analog output Analog output Analog input Analog output Analog input / output Analog input Analog input Analog input Open pin Digital inputs Ambient temperature Junction temperature Junction temperature (Note 1) Storage Temperature Thermal Resistance, Junction to Air (Note 2) Human Body Model Charged Device Model Machine Model Latch−up System ESD (contact/air) (Note 3) 3.5 750 300 ±200 8/15 −0.3 −40 − − −55 3.6 85 150 175 150 37.6 − − − − − V °C °C °C °C °C/W kV V V mA kV per JEDEC Standard JESD78 Exposed pad connected to VPORTN1,2 ground per MIL−STD−883, Method 3015 Thermal shutdown condition Voltage with respect to VPORTN1,2 Min. −0.3 −0.3 −0.3 −0.3 −0.3 −0.3 −0.3 −0.3 −0.3 −0.3 −0.3 −0.3 −0.3 Max. 72 72 17 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 Units V V V V V V V V V V V V V Conditions Voltage with respect to VPORTN1,2 Pass−switch in off−state (Voltage with respect to VPORTN1,2 Voltage with respect to ARTN Voltage with respect to ARTN Voltage with respect to VPORTN1,2 Voltage with respect to VPORTN1,2 Voltage with respect to VPORTN1,2 Voltage with respect to VPORTN1,2 Voltage with respect to ARTN Voltage with respect to ARTN Voltage with respect to ARTN Voltage with respect to ARTN Voltage with respect to ARTN Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Tj−TSD allowed during error conditions only. It is assumed that this maximum temperature condition does not occur more than 1 hour cumulative during the useful life for reliability reasons. 2. Mounted on a 1S2P (3 layer) test board with copper coverage of 25 percent for the signal layers and 90 percent copper coverage for the inner planes at an ambient temperature of 85°C in still air. Refer to JEDEC JESD51−7 for details. 3. Surges per EN61000−4−2, 1999 applied between RJ−45 and output ground and between adapter input and output ground of the evaluation board. The specified values are the test levels and not the failure levels. http://onsemi.com 6 NCP1080 Recommended Operating Conditions Operating conditions define the limits for functional operation and parametric characteristics of the device. Note that the functionality of the device outside the operating conditions described in this section is not warranted. Operating outside the recommended operating conditions for extended periods of time may affect device reliability. All values concerning the DC−DC controller, VDDH and VDDL blocks are with respect to ARTN. All others are with respect to VPORTN1,2 (unless otherwise noted). Table 3. Operating Conditions Symbol INPUT SUPPLY VPORT Input supply voltage 0 57 V VPORT = VPORTP − VPORTN1,2 Parameter Min. Typ. Max. Units Conditions SIGNATURE DETECTION Vsignature Rsignature Offset_current Sleep_current Input supply voltage signature detection range Signature resistance (Note 4) I_VportP + I_Rtn I_VportP + I_Rtn 1.4 23.75 − − 1.8 15 9.5 26.25 5 25 V kW mA mA VPORTP = RTN = 1.4 V VPORTP = RTN = 9.5 V CLASSIFICATION Vcl Iclass0 Iclass1 Iclass2 Iclass3 Iclass4 IDCclass UVLO Vuvlo_on Vuvlo_off Vhyst_int Vuvlo_pr Default turn on voltage (VportP rising) Default turn off voltage (VportP falling) UVLO internal hysteresis UVLO external programming range 29.5 − 25 38 32 6 − 40 − − 50 V V V V UVLO pin tied to VPORTN1,2 UVLO pin tied to VPORTN1,2 UVLO pin tied to VPORTN1,2 UVLO pin connected to the resistor divider (R1 & R2). For information only UVLO pin connected to the resistor divider (R1 & R2) Input supply voltage classification range Class 0: Rclass 10 kW (Note 5) Class 1: Rclass 130 W (Note 5) Class 2: Rclass 69.8 W (Note 5) Class 3: Rclass 44.2 W (Note 5) Class 4: Rclass 30.9 W (Note 5) Internal current consumption during classification (Note 6) 13 0 9 17 26 36 − − − − − − 600 20.5 4 12 20 30 44 − V mA mA mA mA mA mA Iclass0 = I_VportP + I_Rdet Iclass1 = I_VportP + I_Rdet Iclass2 = I_VportP + I_Rdet Iclass3 = I_VportP + I_Rdet Iclass4 = I_VportP + I_Rdet For information only Vhyst_ext Uvlo_Filter UVLO external hysteresis UVLO on/off filter time − − 15 90 − − % mS 4. Test done according to the IEEE802.3af 2 Point Measurement. The minimum probe voltages measured at the PoE−PD are 1.4 V and 2.4 V, and the maximum probe voltages are 8.5 V and 9.5 V. 5. Measured with an external Rdet of 25.5 kW between VPORTP and VPORTN1,2, and for 13 V < VPORT < 20.5 V (with VPORT = VPORTP – VPORTN1,2). 6. This typical current excludes the current in the Rclass and Rdet external resistors. http://onsemi.com 7 NCP1080 Table 3. Operating Conditions Symbol Parameter Min. Typ. Max. Units Conditions PASS−SWITCH AND CURRENT LIMITS Ron I_Rinrush1 I_Rinrush2 I_Rilim1 Pass−switch Rds−on Rinrush = 150 kW (Note 7) Rinrush = 57.6 kW (Note 7) Rilim1 = 84.5 kW (Note 7) − 95 260 450 0.6 125 310 510 1.2 155 360 570 ohm mA mA mA Max Ron specified at Tj = 130°C Measured at RTN− VPORTN1,2 = 3 V Measured at RTN− VPORTN1,2 = 3 V Current limit threshold INRUSH AND ILIM1 CURRENT LIMIT TRANSITION Vds_pgood VDS required for power good status 0.8 1 1.2 V RTN−VPORTN1,2 falling; voltage with respect to VPORTN1,2 Voltage with respect to VPORTN1,2 Vds_pgood_hyst VDDH REGULATOR VDDH_reg VDS hysteresis required for power good status − 8.2 − V Regulator output voltage (Notes 8 and 9) Ivddh_load + Ivddl_load < 10 mA with 0 < Ivddl_load < 2.25 mA Regulator turn−off voltage VDDH regulator current limit (Notes 8 and 9) VDDH POR level (rising) VDDH POR level (falling) VDDH over−voltage level (rising) 8.4 9 9.6 V VDDH_Off VDDH_lim VDDH_Por_R VDDH_Por_F VDDH_ovlo VDDL REGULATOR VDDL_reg − 13 7.3 6 16 VDDH_reg + 0.5 V − − − − − 26 8.3 7 18.5 V mA V V V For information only Regulator output voltage (Notes 8 and 9) 0 < lvddl_load < 2.25 mA with lvddh_load + Ivddl_load < 10 mA VDDL POR level (rising) VDDL POR level (falling) 3.05 3.3 3.55 V VDDL_Por_R VDDL_Por_F GATE DRIVER Gate_Tr Gate_Tf VDDL – 0.2 2.5 − − VDDL – 0.02 2.9 V V GATE rise time (10−90%) GATE fall time (90−10%) − − − − 50 50 ns ns Cload = 2 nF, VDDHreg = 9 V Cload = 2 nF, VDDHreg = 9 V PWM COMPARATOR VCOMP COMP control voltage range 1.3 − 3 V For information only 7. The current value corresponds to the PoE−PD input current (the current flowing in the external Rdet and the quiescent current of the device are included). 8. Power dissipation must be considered. Load on VDDH and VDDL must be limited especially if VDDH is not powered by an auxiliary winding. 9. Ivddl_load = current flowing out of the VDDL pin. Ivddh_load = current flowing out of the VDDH pin + current delivered to the Gate Driver (function of the frequency, VDDH voltage & MOSFET gate capacitance). http://onsemi.com 8 NCP1080 Table 3. Operating Conditions Symbol ERROR AMPLIFIER Vbg_fb Av_ol GBW Reference voltage DC open loop gain Error amplifier GBW 1.15 − 1 1.2 80 − 1.25 − − V dB MHz Voltage with respect to ARTN For information only For information only Parameter Min. Typ. Max. Units Conditions SOFT−START Vss Vss_r Iss Soft−start voltage range Soft−start low threshold (rising edge) Soft−start source current − 0.35 3 1.15 0.45 5 − 0.55 7 V V mA mV nS For information only CURRENT LIMIT COMPARATOR CSth Tblank CS threshold voltage Blanking time 324 − 360 100 396 − OSCILLATOR DutyC Frange F_acc Maximum duty cycle Oscillator frequency range Oscillator frequency accuracy − 100 80% − ±25 − 500 kHz % Fixed internally CURRENT CONSUMPTION IvportP1 IvportP2 VPORTP internal current consumption (Note 10) VPORTP internal current consumption (Note 11) − − 2.5 4.7 3.5 6.5 mA mA DC−DC controller off DC−DC controller on THERMAL SHUTDOWN TSD Thyst Thermal shutdown threshold Thermal hysteresis 150 − − 15 − − °C Tj °C Tj Tj = junction temperature Tj = junction temperature THERMAL RATINGS Ta Tj Ambient temperature Junction temperature −40 − − − 85 125 150 °C °C °C Parametric values guaranteed Max 1000 hours 10. Conditions a. No current through the pass−switch b. DC−DC controller inactive (SS shorted to RTN) c. No external load on VDDH and VDDL d. VPORTP = 57 V 11. Conditions a. No current through the pass−switch b. Oscillator frequency = 100 kHz c. No external load on VDDH and VDDL d. Aux winding not used e. 2 nF on GATE, DC−DC controller enabled f. VPORTP = 57 V http://onsemi.com 9 NCP1080 Description of Operation Powered Device Interface Power Mode The PD interface portion of the NCP1080 supports the IEEE802.3af defined operating modes: detection signature, current source classification, inrush and operating current limits. In order to give more flexibility to the user and also to keep control of the power dissipation in the NCP1080, both current limits are configurable. The device enters operation once its programmable Vuvlo_on threshold is reached, and operation ceases when the supplied voltage falls below the Vuvlo_off threshold. Sufficient hysteresis and Uvlo filter time are provided to avoid false power on/off cycles due to transient voltage drops on the cable. Detection When the classification hand−shake is completed, the PSE and PD devices move into the operating mode. Under Voltage Lock Out (UVLO) The NCP1080 incorporates an under voltage lock out (UVLO) circuit which monitors the input voltage and determines when to apply power to the DC−DC controller. To use the default settings for UVLO (see Table 3), the pin UVLO must be connected to VPORTN1,2. In this case the signature resistor has to be placed directly between VPORTP and VPORTN1,2, as shown in Figure 7. VPORTP During the detection phase, the incremental equivalent resistance seen by the PSE through the cable must be in the IEEE802.3af standard specification range (23.75 kW to 26.25 kW) for a PSE voltage from 2.7 V to 10.1 V. In order to compensate for the non−linear effect of the diode bridge and satisfy the specification at low PSE voltage, the NCP1080 presents a suitable impedance in parallel with the 25.5 kW Rdet external resistor. For some types of diodes (especially Schottky diodes), it may be necessary to adjust this external resistor. When the Detection_Off level is detected (typically 11.5 V) on VPORTP, the NCP1080 turns on its internal 3.3 V regulator and biasing circuitry in anticipation of the classification phase as the next step. Classification VPORT Rdet UVLO VPORTN1,2 NCP1080 Figure 7. Default UVLO Settings Once the PSE device has detected the PD device, the classification process begins. In classification, the PD regulates a constant current source that is set by the external resistor RCLASS value on the CLASS pin. Figure 6 shows the schematic overview of the classification block. The current source is defined as: I class + VPORTP To define the UVLO threshold externally, the UVLO pin must be connected to the center of an external resistor divider between VPORTP and VPORTN1,2 as shown in Figure 8. The series resistance value of the external resistors must add to 25.5 kW and replaces the internal signature resistor. VPORTP R1 VPORT UVLO R2 V bg R class , (where V bg is 1.2 V) VDDA1 1.2 V VPORTN1,2 CLASS NCP1080 Figure 8. External UVLO Configuration Rclass For a Vuvlo_on desired turn−on voltage threshold, R1 and R2 can be calculated using the following equations: VPORTN1,2 NCP1080 R1 ) R2 + R det R2 + 1.2 V ulvo_on R det Figure 6. Classification Block Diagram http://onsemi.com 10 NCP1080 When using the external resistor divider, the NCP1080 has an external reference voltage hysteresis of 15 percent typical. Inrush and Operational Current Limitations The inrush current limit and the operational current limit are programmed individually by an external Rinrush and Rilim1 resistors respectively connected between INRUSH and VPORTN1,2, and between ILIM1 and VPORTN1,2 as shown in Figure 9. VDDA1 VDDA1 ILIM1 / INRUSH Vbg1 Ilim_ref VPORTNx NCP1080 Figure 9. Current Limitation Configuration (Inrush & Ilim1 Pins) Inrush Ilim1 0 1 I_pass_switch & VDS_PGOOD Vds_pgood threshold 1 V / 9.2 V VPORTNx Pass Switch NCP1080 RTN VDDA1 Current_limit_ON detector VDDA1 2V VDDA1 Figure 10. Inrush and Ilim1 Selection Mechanism When VPORT reaches the UVLO_on level, the Cpd capacitor is charged with the INRUSH current (in order to limit the internal power dissipation of the pass−switch). Once the Cpd capacitor is fully charged, the current limit switches from the inrush current to the current limit level (ilim1) as shown in Figure 10. This transition occurs when both following conditions are satisfied: 1. The VDS of the pass−switch is below the Vds_pgood low level (1 V typical). 2. The pass−switch is no longer in current limit mode, meaning the gate of the pass−switch is “high” (above 2 V typical). The operational current limit will stay selected as long as Vds_pgood is true (meaning that RTN−VPORTN1,2 is below the high level of Vds_pgood). This mechanism allows a current level transition without any current spike in the pass−switch because the operational current limit (ilim1) is enabled once the pass−switch is not limiting the current anymore, meaning that the Cpd capacitor is fully charged. Thermal Shutdown The NCP1080 includes thermal protection which shuts down the device in case of high power dissipation. Once the thermal shutdown (TSD) threshold is exceeded, following blocks are turned off: • DC−DC controller • Pass−switch • VDDH and VDDL regulators • CLASS regulator When the TSD error disappears and if the input line voltage is still above the UVLO level, the NCP1080 automatically restarts with the current limit set in the inrush state, the DC−DC controller is disabled and the Css http://onsemi.com 11 NCP1080 (soft−start capacitor) discharged. The DC−DC controller becomes operational as soon as RTN−VPORTN1,2 is below the Vds_pgood threshold. DC−DC Converter Controller The NCP1080 implements a current mode DC−DC converter controller which is illustrated in Figure 11. OSC VPORTP VDDL 5 kW Oscillator Reset CLK Set CLK 3.3 V LDO COMP Current Slope Compensation 10 mA 0 PWM comp CS Blanking time VDDL 360 mV 5 mA SS Soft−start 11 kW 1.45 V 2 Current limit comp R ARTN S Q Gate Driver 9 V LDO VDDH VDDL 1.2 V FB GATE Figure 11. DC−DC Controller Block Diagram Internal VDDH and VDDL Regulators and Gate Driver An internal linear regulator steps down the VPORTP voltage to a 9 V output on the VDDH pin. VDDH supplies the internal gate driver circuit which drives the GATE pin and the gate of the external power MOSFET. The NCP1080 gate driver supports an external MOSFET with high Vth and high input gate capacitance. A second LDO regulator steps down the VDDH voltage to a 3.3 V output on VDDL. VDDL powers the analog circuitry of the DC−DC controller. In order to prevent uncontrolled operations, both regulators include power−on−reset (POR) detectors which prevent the DC−DC controller from operating when either VDDH or VDDL is too low. In addition, an over−voltage lockout (OVLO) on the VDDH supply disables the gate driver in case of an open−loop converter with a configuration using the bias winding of the transformer (see Figure 4). Both VDDH and VDDL regulators turn on as soon as VPORT reaches the Vuvlo_on threshold. Error Amplifier In isolated topologies the error amplifier is not used because it is already implemented externally with the shunt regulator on the secondary side of the DC−DC controller (see Figure 2). Therefore the FB pin must be strapped to ARTN and the output transistor of the opto−coupler has to be connected on the COMP pin where an internal 5 kW pull−up resistor is tied to the VDDL supply (see Figure 11). Soft−Start In non−isolated converter topologies, the high gain internal error amplifier of the NCP1080 and the internal 1.2 V reference voltage regulate the DC−DC output voltage. In this configuration, the feedback loop compensation network should be inserted between the FB and COMP pins as shown in Figures 3, 4 and 5. The soft−start function provided by the NCP1080 allows the output voltage to ramp up in a controlled fashion, eliminating output voltage overshoot. This function is programmed by connecting a capacitor Css between the SS and ARTN pins. While the DC−DC controller is in POR, the capacitor Css is fully discharged. After coming out of POR, an internal current source of 5 mA typically starts charging the capacitor Css to initiate soft−start. When the voltage on SS pin has reached 0.45 V (typical), the gate driver is enabled and DC−DC operation starts with a duty cycle limit which increases with the SS pin voltage. The soft−start function is finished when the SS pin voltage goes above 1.6 V for which the duty cycle limit reaches its maximum value of 80 percent Soft−start can be programmed by using the following equation: tss(ms) + 0.23 Css(nf) http://onsemi.com 12 NCP1080 Current Limit Comparator The NCP1080 current limit block behind the CS pin senses the current flowing in the external MOSFET for current mode control and cycle−by−cycle current limit. This is performed by the current limit comparator which, on the CS pin, senses the voltage across the external Rcs resistor located between the source of the MOSFET and the ARTN pin. The NCP1080 also provides a blanking time function on CS pin which ensures that the current limit and PWM comparators are not prematurely trigged by the current spike that occurs when the switching MOSFET turns on. Slope Compensation Circuitry conduction mode (CCM) and when the duty cycle is close or above 50 percent, the NCP1080 integrates a current slope compensation circuit. The amplitude of the added slope compensation is typically 110 mV over one cycle. As an example, for an operating switching frequency of 250 kHz, the internal slope provided by the NCP1080 is 27.5 mV/ mA typically. DC−DC Controller Oscillator The frequency is configured with the Rosc resistor inserted between OSC and ARTN, and is defined by the following equation: R OSC(kW) + 38600 F OSC(kHz) To overcome sub−harmonic oscillations and instability problems that exist with converters running in continuous The duty cycle limit is fixed internally at 80 percent. http://onsemi.com 13 NCP1080 PACKAGE DIMENSIONS TSSOP−20 EP CASE 948AB−01 ISSUE O D B 20 B DETAIL B 11 0.20 C A-B D 2X 10 TIPS e/2 DETAIL B E1 E b b1 D 10 20X PIN 1 REFERENCE c c1 1 e A b 0.10 M SECTION B−B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.07 IN EXCESS OF THE LEAD WIDTH AT MMC. DAMBAR CANNOT BE LOACTED ON THE LOWER RADIUS OR THE FOOT OF THE LEAD. 4. DIMENSIONS b, b1, c, c1 TO BE MEASURED BETWEEN 0.10 AND 0.25 FROM LEAD TIP. 5. DATUMS A AND B ARE ARE DETERMINED AT DATUM H. DATUM H IS LOACTED AT THE MOLD PARTING LINE AND COINCIDENT WITH LEAD WHERE THE LEAD EXITS THE PLASTIC BODY. 6. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.15 PER SIDE. D AND E1 ARE DETERMINED AT DATUM H. DIM A A1 A2 b b1 c c1 D E E1 e L L2 M P P1 MILLIMETERS MAX MIN --1.10 0.05 0.15 0.85 0.95 0.19 0.30 0.19 0.25 0.09 0.20 0.09 0.16 6.40 6.60 6.40 BSC 4.30 4.50 0.65 BSC 0.50 0.70 0.25 BSC 0_ 8_ --4.20 --3.00 TOP VIEW 0.05 C C A-B D B A2 A B C SEATING PLANE 0.08 C 20X SIDE VIEW P A1 H L2 GAUGE PLANE SEATING PLANE P1 BOTTOM VIEW *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. The product described herein may be covered by one or more US patents pending. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone : 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 14 ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ L DETAIL A 6.76 20X ÉÉÉ ÉÉÉ ÉÉÉ M DETAIL A END VIEW C SOLDERING FOOTPRINT* 4.30 3.10 0.98 0.65 PITCH 0.35 DIMENSIONS: MILLIMETERS 20X NCP1080/D