NCP1092DBRG

NCP1090, NCP1091, NCP1092 Integrated IEEE 802.3af PoE-PD Interface Controller Description The NCP1090, NCP1091 and NCP1092 are members of ON Semiconductor’s high power HIPOt Power over Ethernet Powered Device (PoE−PD) product family and integrate an IEEE 802.3af PoE−PD interface controller. The 3 variants all incorporate the required functions as such detection, classification, under voltage lockout, inrush and operational current limit. A power good signal has been added to guarantee a good enabling/disabling of the DC−DC controller. In addition, the NCP1091 offers a programmable under−voltage while the NCP1092 provide an auxiliary pin for applications supporting auxiliary supplies. The NCP1090, NCP1091 and NCP1092 are fabricated in a robust high voltage process and integrates a rugged vertical N−channel DMOS suitable for the most demanding environments and capable of withstanding harsh environments such as hot swap and cable ESD events. The NCP1090, NCP1091 and NCP1092 complement ON Semiconductor’s ASSP portfolio in industrial devices and can be combined with stepper motor drivers, CAN bus drivers and other high−voltage interfacing devices to offer complete solutions to the industrial and security market. http://onsemi.com SOIC−8 S SUFFIX CASE 751AZ PIN CONFIGURATION INRUSH • • • • Fully Supports IEEE 802.3af Specifications Programmable Classification Current Adjustable Under Voltage Lock Out (NCP1091 Only) Open−Drain Power Good Indicator 130 mA Inrush Current Limit 500 mA Operational Current Limit Pass Switch Disabling Input for Rear Auxiliary Supply Operation (NCP1092 Only) Over−temperature Protection Industrial Temperature Range −40°C to 85°C with Full Operation up to 125°C Junction Temperature 0.5 W Hot−swap Pass−switch Vertical N−channel DMOS Pass−switch Offers the Robustness of Discrete MOSFETs 1 VPORTP * CLASS PGOOD DET VPORTN RTN (Top View) * NCP1090 = NC NCP1091 = UVLO NCP1092 = AUX Features • • • • • • • TSSOP−8 T SUFFIX CASE 948S 8 XXXXX AYWWG G 1 XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package ORDERING INFORMATION Device Package Shipping† NCP109xxxx SOIC−8 (Pb−Free) 2500/Tape & Reel NCP109xxxx TSSOP−8 (Pb−Free) 2500/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2011 February, 2011 − Rev. 2 1 Publication Order Number: NCP1090/D NCP1090, NCP1091, NCP1092 VPORTP DETECTION DET INTERNAL SUPPLY & VOLTAGE REFERENCE THERMAL SHUTDOWN UVLO EXTERNAL SELECTION UVLO NCP1091 only CLASS CLASSIFICATION VPORT MONITOR IEEE Interface Shutdown (AUX supply priority) AUX NCP1092 only HOT SWAP SWITCH INRUSH INRUSH & OPERATIONAL CURRENT LIMIT CONTROL & CURRENT POWER GOOD INDICATOR PGOOD LIMIT BLOCKS RTN VPORTN Figure 1. NCP1090/91/92 Functional Block Diagram http://onsemi.com 2 NCP1090, NCP1091, NCP1092 Simplified Application Diagrams RJ−45 VPORTP Rdet DB1 DET Cline Z_line Rclass Rinrush PGOOD CLASS To DC−DC Converter Cpd Data Pairs NCP1090 INRUSH RTN DB2 Spare Pairs NC VPORTN Figure 2. Typical Application Circuit using the NCP1090 RJ−45 VPORTP Rdet DB1 DET Cline Z_line Rclass Rinrush PGOOD CLASS NCP1091 INRUSH Ruvlo1 Spare Pairs Cpd Data Pairs RTN DB2 UVLO Ruvlo2 VPORTN Figure 3. Typical Application Circuit using the NCP1091 with External UVLO Setting http://onsemi.com 3 To DC−DC Converter NCP1090, NCP1091, NCP1092 Table 1. PIN DESCRIPTION Pin No. Name NCP1090 NCP1091 NCP1092 Type INRUSH 1 1 1 Output Current limit programming pin. Connect a resistor between INRUSH and VPORTN. CLASS 2 2 2 Output Classification current programming pin. Connect a resistor between CLASS and VPORTN. DET 3 3 3 Output, Open Drain Detection pin. Connect a 24.9 kW resistor between DET and VPORTP for a valid PD detection signature. VPORTN 4 4 4 Ground Negative input power. Connected to the source of the internal pass−switch RTN 5 5 5 Ground DC−DC controller power return. Connected to the drain of the internal pass−switch PGOOD 6 6 6 Output, Open Drain NC 7 − − − UVLO − 7 − Input Under−voltage lockout input. Voltage with respect to VPORTN. Connect a resistor−divider from VPORTP to UVLO to VPORTNx to set an external UVLO threshold. AUX − − 7 Input Auxiliary Pin. When this pin is pulled up, the Pass Switch is disabled and allows a supply transition from PSE to the rear auxiliary supply connected between VPORTP and RTN. VPORTP 8 8 8 Input Positive input power. Voltage with respect to VPORTN. Description Open Drain Power Good Indicator. Pin is in HZ mode when the power good signal is active. No connection Operating Conditions Table 2. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Min Max Units Conditions VPORTP Input power supply −0.3 72 V Voltage with respect to VPORTN RTN Analog ground supply 2 −0.3 72 V Pass−switch in off−state (voltage with respect to VPORTN) CLASS Analog output −0.3 72 V Voltage with respect to VPORTN INRUSH Analog output −0.3 3.6 V Voltage with respect to VPORTN AUX Analog input −0.3 72 V Voltage with respect to VPORTN UVLO Analog input −0.3 3.6 V Voltage with respect to VPORTN PGOOD Analog output −0.3 72 V Voltage with respect to RTN Ta Ambient temperature −40 85 °C Tj Junction temperature − 125 °C Tj−TSD Junction temperature (Note 1) − 175 °C Tstg Storage Temperature −55 150 °C TθJA Thermal Resistance, Junction to Air (Note 2) 150 160 240 260 °C/W ESD−HBM Human Body Model 2 kV per EIA−JESD22−A114 standard ESD−CDM Charged Device Model 500 V per ESD−STM5.3.1 standard ESD−MM Machine Model 200 V per EIA−JESD22−A115−A standard LU Latch−up ±100 mA Thermal shutdown condition SOIC−8 TSSOP−8 per JEDEC Standard JESD78 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Tj−TSD allowed during error conditions only. It is assumed that this maximum temperature condition does not occur more than 1 hour cumulative during the useful life for reliability reasons. 2. Low qJA is obtained with 2S2P test board (2 signal − 2 plane). High qJA is obtained with double sideboard with minimum pad area and natural convection. Refer to Jedec JESD51 for details. http://onsemi.com 4 NCP1090, NCP1091, NCP1092 Recommended Operating Conditions Operating conditions define the limits for functional operation and parametric characteristics of the device. Note that the functionality of the device outside the operating conditions described in this section is not warranted. Operating outside the recommended operating conditions for extended periods of time may affect device reliability. Table 3. OPERATING CONDITIONS (All values are with respect to VPORTN unless otherwise noted.) Symbol Parameter Min Typ Max Units Conditions 57 V VPORT = VPORTP – VPORTN INPUT SUPPLY VPORT Input supply voltage 0 SIGNATURE DETECTION Offset_det1 I(VPORTP) + I(RTN) 2 5 mA VPORTP = RTN = 1.9 V Rdet = 24.9 KW Sleep_det1 I(VPORTP) + I(RTN) 15 21 mA VPORTP = RTN = 9.8 V Rdet = 24.9 KW Offset_det2 I(VPORTP) + I(RTN) + I(DET) 73 77 81 mA VPORTP = RTN = 1.9 V Rdet = 24.9 KW Sleep_det2 I(VPORTP) + I(RTN) + I(DET) 390 400 412 mA VPORTP = RTN = 9.8 V Rdet = 24.9 KW Vcl_on Classification current turn−on lower threshold 9.8 11.3 13 V VPORTP rising Vcl_off Classification current turn−off upper threshold 21 24 V VPORTP rising Vclass_reg Classification buffer output voltage 9.8 V 13 V < VPORTP < 21 V Icl_bias I(vportp) quiescent current during classification 600 mA I(class) excluded 13 V < VPORTP < 21 V Iclass0 Class 0: Rclass 4420 W (Note 3) 0 − 4 mA 13 V < VPORTP < 21 V Iclass1 Class 1: Rclass 953 W (Note 3) 9 − 12 mA 13 V < VPORTP < 21 V Iclass2 Class 2: Rclass 549 W (Note 3) 17 − 20 mA 13 V < VPORTP < 21 V Iclass3 Class 3: Rclass 357 W (Note 3) 26 − 30 mA 13 V < VPORTP < 21 V Iclass4 Class 4: Rclass 255 W (Note 3) 36 − 44 mA 13 V < VPORTP < 21 V CLASSIFICATION UVLO − INTERNAL SETTING − NCP1090/91/92 Vuvlo_on Default turn on voltage − 37 40 V VPORTP rising Vuvlo_off Default turn off voltage 29.6 31 − V VPORTP falling Vhyst_int UVLO internal hysteresis − 6 − V Uvlo_filter UVLO On / Off filter time − 100 − mS For information only VPORTP rising UVLO − EXTERNAL SETTING – NCP1091 ONLY 25 − 50 V Vuvlo_on2 Vuvlo_pr External UVLO turn on voltage 1.14 1.2 1.26 V Vhyst_off2 External UVLO turn off voltage 0.95 1 1.05 V − 2.5 − mA Uvlo_ipd UVLO external programming range UVLO internal pull down current AUXILIARY SUPPLY SETTING – NCP1092 ONLY Aux_h AUX input high level voltage 3.1 − Aux_l AUX input low level voltage − − 0.6 V 100 − − KW Aux_pd AUX internal pull down resistor 3. A tolerance of 1% on the Rclass resistor is included in the min/max values. http://onsemi.com 5 V For information only NCP1090, NCP1091, NCP1092 Table 3. OPERATING CONDITIONS (All values are with respect to VPORTN unless otherwise noted.) Symbol Parameter Min Typ Max Units Conditions Pass−switch Rds−on − 0.5 1 W I_inrush Inrush current with Rinrush = 178 kW 75 120 170 mA Measured at RTN−VPORTN = 3 V I_ilim Operating current limit with Rinrush = 178 kW 425 500 575 mA Current limit threshold PASS−SWITCH AND CURRENT LIMITING Ron Measured with I(RTN) = 200 mA POWER GOOD INDICATOR Vds_pgood_on RTN−VPORTN threshold voltage required for power good status 0.8 1 1.2 V RTN−VPORTN falling Vds_pgood_off RTN−VPORTN latchoff threshold voltage 9 10 11 V RTN−VPORTN rising mS Rising and falling / for information only Pgood_filter PGOOD filter time 100 Ipgood I(PGOOD) sinking current − − 5 mA Vpgood_low PGOOD voltage output low − 0.2 0.5 V Voltage with respect to RTN − 600 900 mA VPORTP = 48 V 150 − − °C Tj Tj = junction temperature − 15 − °C Tj Tj = junction temperature CURRENT CONSUMPTION IvportP I(VPORTP) internal current consumption THERMAL SHUTDOWN TSD Thermal shutdown threshold Thyst Thermal hysteresis THERMAL RATINGS Ta Ambient temperature −40 − 85 °C Tj Junction temperature − − 125 °C 3. A tolerance of 1% on the Rclass resistor is included in the min/max values. http://onsemi.com 6 NCP1090, NCP1091, NCP1092 Description of Operation Under Voltage Lock Out (UVLO) The NCP1090/91/92 incorporate a fixed under voltage lock out (ULVO) circuit which monitors the input voltage and determines when to turn on the pass switch and charge the dc−dc converter input capacitor before the power up of the application. The NCP1091 offers a fixed or adjustable Vuvlo_on threshold depending if the UVLO pin is used or not. In Figure 5, the UVLO pin is strapped to ground and the Vuvlo_on threshold is defined by the internal level. Powered Device Interface The integrated PD interface supports the IEEE 802.3af defined operating modes: detection signature, current source classification, undervoltage lockout, inrush and operating current limits. The following sections give an overview of these previous processes. Detection During the detection phase, the incremental equivalent resistance seen by the PSE through the cable must be in the IEEE 802.3af standard specification range (23.70 kW to 26.30 kW) for a PSE voltage from 2.7 V to 10.1 V. In order to compensate for the non−linear effect of the diode bridge and satisfy the specification at low PSE voltage, the NCP1090/91/92 present a suitable impedance in parallel with the 24.9 kW Rdet external resistor. For some types of diodes (especially Schottky diodes), it may be necessary to adjust this external resistor. The Rdet resistor has to be inserted between VPORTP and DET pins. During the detection phase, the DET pin is pulled to ground and goes in high impedance mode (open−drain) once the device exit this mode, reducing thus the current consumption on the cable. VPORTP VPORTN1,2 Figure 5. Default Internal UVLO Configuration (NCP1091 only) To define the UVLO threshold externally, the ULVO pin must be connected to the center of an external resistor divider between VPORTP and VPORTN as shown in Figure 6. In order to guarantee the detection signature, the equivalent input resistor made of the Ruvlo1, Ruvlo2 and Rdet should be equal to 24.9 kW. Classification Once the PSE device has detected the PD device, the classification process begins. In classification, the PD regulates a constant current source that is set by the external resistor RCLASS value on the CLASS pin. Figure 4 shows the schematic overview of the classification block. The current source is defined as: Iclass + UVLO VPORT 9.8 V Rclass VPORTP Ruvlo1 Class_enable VPORTP DET VPORT VPORTP EN Rdet 1.2 V UVLO Ruvlo2 VPORTN1,2 CLASS NCP1091 9.8 V Figure 6. Default Internal UVLO Configuration (NCP1091 only) For a Vuvlo_on desired turn−on voltage threshold, Ruvlo1 and Ruvlo2 can be calculated using the following equations: VPORTN Ruvlo + Figure 4. Classification Block Diagram Power Mode When the classification hand−shake is completed, the PSE and PD devices move into the operating mode. 24.9 k @ Rdet Rdet * 24.9 k with Ruvlo1 ) Ruvlo2 + Ruvlo and Ruvlo2 + 1.2 @ Ruvlo Vuvlo_on With: Vuvlo_on: Desired Turn−On voltage threshold http://onsemi.com 7 NCP1090, NCP1091, NCP1092 Example for a Targeted Uvlo_on of 35 V: and the PD application against excessive transient current and failure on the dc−dc converter output. Once the input supply reached the Vulvo_on level, the charge of Cpd capacitor starts with a current limitation set to to the INRUSH level. When this capacitor is fully charged, the current limit switches without any spikes from the inrush current to the operational current level and the power good indicator on PGOOD pin is turned on. The capacitor is considered to be fully charged once the following conditions are satisfied: 1. The drain−source voltage of the Pass Switch has decreased below the Vds_pgood_on level (typical 1 V) 2. The gate−source voltage of the Pass Switch is sufficiently high (above 2 V typical) which means the current in the pass switch has decreased below the current limit. This mechanism is depicted in the following Figure 7. Let’s start with a Rdet of 30.1 kΩ. This gives a Ruvlo of 144 kΩ made with a Ruvlo2 of 4.99 kΩ and a Ruvlo1 of 140 kΩ (closest values from E96 series). Note that there is a pull down current of 2.5 mA typ on the UVLO. Assuming the previous example, this pull down current will create a (non critical) systematic offset of 350 mV on the Uvlon_on level of 35 V. The external UVLO hysteresis on the NCP1091 is about 15 percent typical. Inrush and Operational Current Limitations Both inrush and operational current limit are defined by an external Rinrush resistor connected between INRUSH and VPORTN. The low inrush current limit allows smooth charge of large dc−dc converter input capacitor by limiting the power dissipation over the internal pass switch. In power mode, the operational current limit protects the pass switch PGOOD Pgood_on Inrush current limit 0 Operational current limit 1 Pgood_on Delay 100 mS & detector VDDA1 VDDA1 1 V / 10 V VDDA1 2V RTN Vds_pgood comparator Vgs_pgood comparator RTN VPORTNx Sense Resistor Pass Switch Figure 7. Inrush and Operational Current Limitation Selection Mechanism PGOOD Indicator The operational current limit and the power good indicator stays active as long as RTN voltage stays below the vds_pgood_off threshold (10 V typical) and the input supply stay above the Vulvo_off level. Therefore, fast and large voltage step lower than 10 V are tolerated on the input without interruption of the converter controller. Higher input transient will not affect the behavior if RTN does not exceed 10 V for more than 100 mS. Such input voltage steps may be introduced by a PSE which is switched to a higher power supply. In case RTN is still above 10 V after this delay, the power good is turned off and the pass switch current limit falls back to the inrush level. The NCP1090/91/92 integrate a Power Good indicator circuitry indicating the end of the dc−dc converter input capacitor charge, and the enabling of the operational current limit. This indicator is implemented on the PGOOD pin which goes in open drain state when active and which is pulled to ground during turn off. A possible usage of this PGOOD pin is illustrated in Figure 8. During the inrush phase, the converter controller is forced in standby mode due to the PGOOD pin forcing low the under voltage lock out pin of the controller. Once the Cpd capacitor is fully charged, PGOOD goes in open drain state, allowing the start up sequence of the converter controller. http://onsemi.com 8 NCP1090, NCP1091, NCP1092 VPORTP VDD Rdet DET Rclass Rinrush UVLO NCP103x DC−DC Converter Controller PGOOD Cpd CLASS OVLO NCP1090 GATE VSS INRUSH RTN VPORTN Figure 8. Power GOOD Implementation Auxiliary Supply To support application connected to non−PoE enabled networks and minimize the bill of materials, the NCP1093 supports drawing power from an external supply and allows simplified designs with PoE or auxiliary supply priorities. In most of the cases, the auxiliary supply is connected between VPORTP and RTN with a serial diode between VPORTP and VAUX, as shown in Figure 9. RJ−45 VAUX (+) VPORTP Rdet DB1 DET Cline Z_line Rclass Rinrush PGOOD CLASS Cpd Data Pairs To DC−DC Converter NCP1092 INRUSH RTN Spare Pairs DB2 AUX VPORTN VAUX (−) Figure 9. Auxiliary Supply Dominant PD Interface The NCP1092 offers an AUX input pin which turns off the pass switch when pulled high. This feature is useful for PD applications where the auxiliary supply has to be dominant over the PoE supply. When the auxiliary supply is inserted on a POE powered application, the pass switch disconnection will move the current path from the PSE to the rear auxiliary supply. Since the current delivered by the PSE will goes below the DC MPS level (specified in IEEE 802.3 af/at standard), the PSE will disconnect the PoE−PD and the application will remain supplied by the auxiliary supply. The transition will happens without any power conversion interruption since the PGOOD indicator stays active (high impedance state). Next Figure 10 depicts an other PD application where the POE supply is dominant over the VAUX supply. A diode D1 has been added in order to not corrupt the PD detection signature when the dc−dc converter is supplied by VAUX. http://onsemi.com 9 NCP1090, NCP1091, NCP1092 VAUX (+) RJ−45 D1 VPORTP Rdet DB1 DET Rinrush PGOOD CLASS Cpd Rclass Cline Z_line Data Pairs NCP1092 To DC−DC Converter INRUSH RTN Spare Pairs DB2 AUX VPORTN VAUX (−) Figure 10. PoE Supply Dominant PD Interface Thermal Shutdown Company or Product Inquiries The NCP1090/91/92 include a thermal shutdown which protect the device in case of high junction temperature. Once the thermal shutdown (TSD) threshold is exceeded, the classification block, the pass switch and the PGOOD indicator are disabled. The NCP109X returns automatically to normal operation once the die temperature has fallen below the TSD low limit. For more information about ON Semiconductor’s Power over Ethernet products visit our Web site at http://www.onsemi.com. All brand names and product names appearing in this document are registered trademarks or trademarks of their respective holders. http://onsemi.com 10 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 CASE 751AZ ISSUE B 8 1 SCALE 1:1 NOTES 4&5 0.10 C D 45 5 CHAMFER D h NOTE 6 D A 8 DATE 18 MAY 2015 H 2X 5 0.10 C D E E1 NOTES 4&5 L2 1 0.20 C D 4 8X B NOTE 6 TOP VIEW b 0.25 M L C DETAIL A C A-B D NOTES 3&7 NOTE 7 c 0.10 C e A1 C SIDE VIEW NOTE 8 DIM A A1 A2 b c D E E1 e h L L2 DETAIL A A2 A SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.004 mm IN EXCESS OF MAXIMUM MATERIAL CONDITION. 4. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006 mm PER SIDE. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.010 mm PER SIDE. 5. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOT­ TOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE OUTER­ MOST EXTREMES OF THE PLASTIC BODY AT DATUM H. 6. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM H. 7. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 TO 0.25 FROM THE LEAD TIP. 8. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. SEATING PLANE END VIEW RECOMMENDED SOLDERING FOOTPRINT* MILLIMETERS MIN MAX --1.75 0.10 0.25 1.25 --0.31 0.51 0.10 0.25 4.90 BSC 6.00 BSC 3.90 BSC 1.27 BSC 0.25 0.41 0.40 1.27 0.25 BSC GENERIC MARKING DIAGRAM* 8X 0.76 8 8X 1.52 1 7.00 XXXXX A L Y W G 1 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON34918E SOIC−8 XXXXX ALYWX G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G”, may or not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP−8 CASE 948S−01 ISSUE C DATE 20 JUN 2008 SCALE 2:1 8x 0.20 (0.008) T U K REF 0.10 (0.004) S 2X L/2 8 0.20 (0.008) T U T U B −U− 1 J J1 4 V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. S ÉÉÉÉ ÉÉÉÉ ÇÇÇÇ ÉÉÉÉ ÇÇÇÇ K1 K A −V− S S 5 L PIN 1 IDENT M SECTION N−N −W− C 0.076 (0.003) D −T− SEATING DETAIL E G PLANE 0.25 (0.010) N M DIM A B C D F G J J1 K K1 L M N F MILLIMETERS MIN MAX 2.90 3.10 4.30 4.50 --1.10 0.05 0.15 0.50 0.70 0.65 BSC 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.114 0.122 0.169 0.177 --0.043 0.002 0.006 0.020 0.028 0.026 BSC 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ GENERIC MARKING DIAGRAM* XXX YWW AG G DETAIL E XXX A Y WW G = Specific Device Code = Assembly Location = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. DOCUMENT NUMBER: DESCRIPTION: 98AON00697D TSSOP−8 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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