NCP10970A1DR2G

High-Voltage Switcher with Linearly Regulated Output NCP10970 The NCP10970 includes a high−voltage switcher, linear regulator and a dedicated comparator circuitry. The switcher is suitable for building output voltage up to 16 V (adjustable by resistor divider on FB pin) protected against short−circuit. Dedicated internal circuitry prevents continuous conduction mode (CCM) operation improves the surge robustness, efficiency and EMI. In no−load/light−load conditions, the part enters skip cycle operation and ensures low standby power consumption. A proprietary technique ensures high efficiency in the down−conversion process from output switcher voltage rail to raw sub voltage rail supplying a linear regulator. A dedicated comparator circuitry provides a means to instruct the control section that an over−temperature point has been reached. The comparator input is biased by a precise constant current source and output is an open−drain type. To ensure the very low no−load standby power, the device is equipped with a very effective standby mode with a low wake−up time for return to the normal operation mode. Features • Built−in 670 V, 18 W RDS(on) Lateral MOSFET • High−voltage Start−up Current Source • Fixed−frequency DCM Current−mode Control Scheme • End of Demagnetization Detection Ensures DCM Operation only • Short−circuit Protected Switcher Output with Auto−recovery Function • 4 ms Soft Start • Internal Linear Regulator with Short−circuit Protected Output • Internal Comparator with Open Drain Output • Internal Thermal Shutdown • 16−pin SO Package with Creepage Distance • These are Pb−Free Devices Typical Applications • Power Management for Smart Lighting Application • Power Management for White Goods, IoT Application, etc. www.onsemi.com SOIC−16 NB, LESS PIN 15 CASE 752AC MARKING DIAGRAM 16 1097xyyG ON AWLYWW 1 1097xyy = Specific Device Code (x = 0, yy = A1, B1) A = Assembly Location WL = Wafer Lot Y = Year WW = Work Week G = Pb−Free Package PIN CONNECTIONS SOURCE 1 16 DRAIN VCC 2 DMG 3 14 GND FB 4 13 CMPIN COMP 5 12 VRAW NC 6 11 LDOOUT INT 7 10 STBY VCCLV 8 9 CMPOUT ORDERING INFORMATION See detailed ordering and shipping information on page 22 of this data sheet. © Semiconductor Components Industries, LLC, 2020 March, 2020 − Rev. 0 1 Publication Order Number: NCP10970/D NCP10970 Figure 1. Application Schematic PIN FUNCTION DESCRIPTION Pin No. Pin Name Function Description 1 SOURCE The switcher ground This pin is connected to the buck source/inductor junction and grounds the switcher circuitry. The dissipated heat of the transistor is conducted out through this pin. 2 VCC Supplies the switcher section 3 DMG Demagnetization detection 4 FB Feedback pin 5 COMP Loop compensation 6 NC Not connected pin 7 INT The intermediate buck point 8 VCCLV Supplies the low−voltage section 9 CMPOUT Comparator output Open−drain output pin of internal comparator. This pin is pulled low when the CMPIN passes above 1 V. 10 STBY Standby pin This pin affects the speed of comparator and IC consumption. Standby mode (grounded pin) – slow comparator. Active mode (> 3 V on pin) – fast comparator. 11 LDOOUT LDO output A short−circuit protected 3.3 V or 5 V rail. 12 VRAW The intermediate bus rail 13 CMPIN Comparator input 14 GND The ground of low−voltage section 15 – – 16 DRAIN Drain connection The switcher VCC voltage up to 20 V. This pin monitors the inductor magnetic activity. This pin senses the output voltage through a resistive divider. The error amplifier output is available on this pin. The network connected between this pin and ground adjusts the control loop bandwidth. Not connected pin for better isolation between high voltage and low voltage pins. This is the input to generate the raw dc voltage. The VCCLV voltage biases the MOSFET driver, Comparator and LDO circuitry. This is the raw voltage driving the LDO. Input of the internal comparator, internally biased by a 120 mA current source. – Creepage distance. The connection to the lateral MOSFET drain. www.onsemi.com 2 NCP10970 Switcher output HV voltage DRAIN SOURCE + + PWM VCC UVLO FB VREF GND error voltage + _ COMP CMPOUT SWCMP DMG VDMG (th) dmg + VCCLV _ Rint Iref 1 + _ Vstop NC CMPIN Comparator STBY Standby circuit INT VRAW SWINT VCCLV raw dc voltage LDO input _ + VSW(INT),L VCCLV VCCLV LDOOUT SWVCCLV IN RegLin OUT GROUND VCCLV _ + VSW(VCCLV ),L Figure 2. Simplified Block Diagram www.onsemi.com 3 Regulated dc voltage LDO output OTD flag Low when fault NCP10970 MAXIMUM RATINGS Symbol Rating Value Unit Drain voltage −0.3 to 670 V Power Supply voltage pin, continuous voltage −0.3 to 20 V Voltage on FB, COMP and DMG pins −0.3 to 10 V −2 / 3 mA Power Supply voltage pins, continuous voltage −0.3 to 20 V Voltage on CMPIN, STBY and LDOOUT pins, continuous voltage −0.3 to 5.5 V −0.3 to VCC + 0.3 V 150 °C −60 to +150 °C SWITCHER PINS – VOLTAGE ON PINS RELATED TO SOURCE PIN BVDSS VCC VFB, VCOMP, VDMG IDMG,clamp Maximum current of clamped DMG pin (voltage on pin is clamped to −0.7 V / 10 V) LOW VOLTAGE PINS – VOLTAGE ON PINS RELATED TO GND PIN VCCLV, VINT VCMPIN, VLDOOUT, VSTBY VCMPOUT, VRAW Voltage on CMPOUT, VRAW pins, continuous voltage COMMON PARAMETERS TJ,max Maximum Junction Temperature Tstorage Storage Temperature Range ESDHBM ESD Capability, Human Body Model 2 kV ESDCDM ESD Capability, Charged−Device Model 1 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. This device series incorporates ESD protection and is tested by the following methods: • ESD Human Body Model tested per JEDEC Standard JESD22−A114F • ESD Charged−Device Model tested per JEDEC Standard JESD22−C101F • Latch−up protection and exceeds 100 mA per JEDEC standard JESD78 THERMAL CHARACTERISTICS Symbol Rating Value Unit RθJ−ASW Thermal Resistance Junction−to−Air – switcher section only 150 °C/W RθJ−ALV Thermal Resistance Junction−to−Air – low−voltage section only 150 °C/W ELECTRICAL CHARACTERISTICS − HIGH−VOLTAGE SWITCHER (VCC = VCCLV = 12 V unless otherwise noted, for typical values TJ = 25°C, for min/max values TJ = −40°C to 125°C) Parameter Symbol Test Conditions Min Typ Max Unit SUPPLY SECTION AND VCC MANAGEMENT VCC(on) VCC increasing level at which the switcher starts operation 8.4 9.0 9.5 V VCC(min) VCC decreasing level at which the HV current source restarts 7.0 7.4 7.8 V VCC(off) VCC decreasing level at which the switcher stops operation (UVLO) 6.7 7.0 7.2 V ICC1 Internal IC consumption fSW = 65 kHz − 1 − mA ICCskip Internal IC consumption VCOMP = 0 V (No switching MOSFET) − 340 − mA − − 18 33 23 38 W 670 − − V POWER SWITCH CIRCUIT RDS(on) Power Switch Circuit on−state resistance ID = 50 mA, TJ = 25°C ID = 50 mA, TJ = 125°C BVDSS Power Switch Circuit & Startup breakdown voltage ID(off) = 120 mA, TJ = 25°C Figure 9 shows the temp. dependency IDSS(off) Power Switch & Startup off−state leakage current TJ = 125 °C, VDS = 670 V TJ = 125 °C, VDS = 400 V − − 5 2 − − mA Turn−on time (90% − 10%) RL = 50 W, VDS set for Idrain = 0.7 x IPK − 35 − ns tr www.onsemi.com 4 NCP10970 ELECTRICAL CHARACTERISTICS − HIGH−VOLTAGE SWITCHER (continued) (VCC = VCCLV = 12 V unless otherwise noted, for typical values TJ = 25°C, for min/max values TJ = −40°C to 125°C) Symbol Parameter Test Conditions Min Typ Max Unit Turn−off time (10% − 90%) − 10 − ns Minimum on time − 300 − ns POWER SWITCH CIRCUIT tf ton(min) INTERNAL START−UP CURRENT SOURCE Istart1 High−voltage current source VCC = VCC(on) – 200 mV 4 8 12 mA Istart2 High−voltage current source VCC = 0 V − 0.4 − mA − 1.3 − V − − 22 V 325 350 375 mA − 370 − mA VCC(th) VCC transient level for Istart1 to Istart2 toggling point VHV(min) Minimum startup voltage VCC = VCC(on) – 200 mV CURRENT COMPARATOR IPK Maximum internal current setpoint (Note 2) TJ = 25°C IPK(SW) Final switch current with a primary slope of 320 mA/ms fsw = 65 kHz tSS Soft−start duration − 4 − ms tprop Propagation delay from current detection to drain OFF state − 70 − ns tLEB Leading Edge Blanking Duration − 130 − ns 59 65 71 kHz 62 66 72 % INTERNAL OSCILLATOR fOSC Oscillation frequency (Note 3) Dmax Maximum duty ratio TJ = 25°C DEMAGNETIZATION DETECTION BLOCK VDMG(th) VDMG(th,H) Input threshold Voltage is decreasing 15 50 85 mV Hysteresis Voltage is increasing − 25 − mV − 70 − ns 0.5 1.0 − ms − 40 − kW − 10 − pF 3.2 3.3 3.4 V − 1 − mA − 2 − mS − ±150 − mA 0.7 1.3 1.7 V tdem Demag propagation delay tblank Blanking time after turn off the switcher transistor Rint DMG pin internal resistance Cint DMG pin internal capacitance Step from negative voltage value (equal to −1 mA) to positive voltage 1 V Guaranteed by design ERROR AMPLIFIER SECTION VREF Error amplifier reference voltage IFB Input Bias Current GM Transconductance IOTAlim OTA maximum current capability VOTAen FB voltage to disable OTA VFB = 3.3 V VFB > VOTAen COMPENSATION SECTION ICOMPfault COMP current for which fault is detected − −40 − mA ICOMP100% COMP current for which internal current set−point is 100% (IPK) − −44 − mA ICOMPfreeze COMP current for which internal current setpoint is IFreeze − −80 − mA ICOMPskip The COMP pin current level to enter skip mode − −120 − mA − 2.7 − V VCOMP(REF) Equivalent pull−up voltage in linear regulation range Guaranteed by design www.onsemi.com 5 NCP10970 ELECTRICAL CHARACTERISTICS − HIGH−VOLTAGE SWITCHER (continued) (VCC = VCCLV = 12 V unless otherwise noted, for typical values TJ = 25°C, for min/max values TJ = −40°C to 125°C) Symbol Parameter Test Conditions Min Typ Max Unit COMPENSATION SECTION RCOMP(up) IFreeze Equivalent feedback resistor in linear regulation range Guaranteed by design − 17.7 − kW Internal minimum current setpoint ICOMP < ICOMPFreeze − 110 − mA ICOMP > ICOMPfault 35 48 − ms PROTECTIONS tSCP trecovery Fault validation before error flag is asserted OFF phase in fault mode VOVP VCC voltage at which the switcher stops pulsing tOVP Filter of VCC OVP comparator − 400 − ms 17.0 18.0 18.8 V − 80 − ms TEMPERATURE MANAGEMENT TSD Temperature shutdown Guaranteed by design 150 160 − °C TSDHYST Hysteresis in shutdown Guaranteed by design − 20 − °C Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. There is no compensation ramp in this switcher as CCM operation is prevented by the demagnetization detector. 3. Oscillator frequency is measured with grounded DMG pin. The frequency fOSC doesn’t have to be observed in application due to active Demagnetization Detection Block. ELECTRICAL CHARACTERISTICS − LOW VOLTAGE SECTION (VCC = VCCLV = 12 V unless otherwise noted, for typical values TJ = 25°C, for min/max values TJ = −40°C to 125°C) Parameter Symbol Test Conditions Min Typ Max Unit − 8.4 − V SUPPLY SECTION VCCLV(on) VCCLV(Hyst) VCCLV increasing level for activation the internal switches SWINT and SWVCCLV − 4.7 − V ICCLV1 VCCLV hysteresis for deactivation Internal IC consumption in standby (grounded pin STBY) Low voltage section is biased, no switching of internal MOSFETs SWINT and SWVCCLV, no Iref1 − 270 360 mA ICCLV4 Internal IC consumption in active mode (pin STBY in High state) Low voltage section is biased, no switching of internal MOSFETs SWINT and SWVCCLV, no Iref1 − 350 − mA IDS = 200 mA, TJ = 25°C IDS = 200 mA, TJ = 125°C − − 5 − 7 10 W RDS(on),VCCLV RDS(on) of internal MOSFET SWVCCLV IDS = 50 mA, TJ = 25°C IDS = 50 mA, TJ = 125°C − − 15 − 20 30 W VSW(VCCLV),L voltage is decreasing, TJ = 25°C 3.56 5.25 3.60 5.30 3.64 5.35 − − 3.65 5.35 − − − − 3.80 5.50 − − − − 3.85 5.55 − − − 1.5 − RAW VOLTAGE GENERTION RDS(on),INT RDS(on) of internal MOSFET SWINT Voltage for turn−on the switch SWVCCLV · A version (3.3 V) · B version (5 V) VSW(VCCLV),H Voltage for turn−off the switch SWVCCLV · A version (3.3 V) · B version (5 V) voltage is increasing VSW(INT),L Voltage for turn−on the switch SWINT · A version (3.3 V) · B version (5 V) voltage is decreasing VSW(INT),H Voltage for turn−off the switch SWINT · A version (3.3 V) · B version (5 V) voltage is increasing Propagation delay of switches INT and VCCLV voltage is decreasing/increasing tdel(SW) www.onsemi.com 6 V V V V ms NCP10970 ELECTRICAL CHARACTERISTICS − LOW VOLTAGE SECTION (continued) (VCC = VCCLV = 12 V unless otherwise noted, for typical values TJ = 25°C, for min/max values TJ = −40°C to 125°C) Symbol Parameter Test Conditions Min Typ Max Unit − 100 − mA 130 260 420 mA 3.267 4.95 3.300 5.00 3.333 5.05 LOW DROPOUT REGULATOR (Input capacitances CRAW = 22 mF, Output capacitances COUT = 10 mF) ILDOOUT(max) ICL Output current capability (Note 4) Maximum limitation of output current Figure 27 shows the temp. dependency Output voltage accuracy · A version (3.3 V) · B version (5 V) IOUT = 1.0 mA, TJ = 25°C (Note 5) Dropout voltage · A version (3.3 V) · B version (5 V) IOUT = 100 mA − 150 250 mV RegLINE Line regulation A version: 3.6 V < VIN < 4 V, IOUT = 1 mA B version: 5.4 V < VIN < 6 V, IOUT = 1 mA − − 10 mV RegLOAD Load regulation IOUT = 1.0 to 60 mA IOUT = 1.0 to 100 mA − − 5 9 15 20 mV TranLOAD Load transient response IOUT = 3.0 to 30 mA, trise = tfall = 1 ms IOUT = 50 to 100 mA, trise = tfall = 1 ms − − 35 40 − − mV PSRR Power Supply Rejection Ratio VIN = 3.7 V for A version VIN = 5.5 V for B version VIN(pk−pk) = 0.1 V, f = 1 kHz, IOUT = 60 mA (Guaranteed by design) Figure 31 shows the freq. dependency 60 − − dB VNOISE Output noise IOUT = 60 mA, f = 100 Hz to 100 kHz Figure 32 shows the freq. dependency − 300 − mVrms − 4.4 − V VLDOOUT VDO V COMPARATOR VCMP(on) VCMP(Hyst) VCCLV increasing level for activation the comparator − 0.6 − V Vstop Voltage above which the COMPOUT pin is pulled down 0.95 1 1.06 V Vrestart Voltage below which the COMPOUT pin is in high impedance state 0.75 0.8 0.85 V Current source biasing the CMPIN pin 114 120 126 mA Iref1 Rdrain ICMPOUT VCCLV hysteresis for deactivation Internal MOSFET RDS(on) Current capability of internal MOSFET – current flowing into COMPOUT pin Guaranteed by design − 10 20 W 10 − − mA tdel1 Debouncing time constant on the comparator output from High to Low − 0 − ms tdel2 Debouncing time constant on the comparator output from Low to High − 0 − ms tdel Comparator propagation delay − active mode − standby mode − − 60 220 105 − Step 0.5 V to 1.2 V ns TEMPERATURE SHUTDOWN TSD(LV) Temperature shutdown Guaranteed by design 150 160 − °C TSD(LV)HYST Hysteresis in shutdown Guaranteed by design − 20 − °C Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. The accuracy of output voltage is guaranteed up to output current value specified by ILDOOUT(max). For higher output current value, the accuracy can be improved by using a higher capacitances CRAW/COUT. 5. The output voltage VLDOOUT of LDO is guaranteed for 25°C only. The temperature dependency graph shows the temperature dependency for −40°C to 125°C. www.onsemi.com 7 NCP10970 TYPICAL CHARACTERISTICS − HIGH VOLTAGE SWITCHER 9.10 7.48 7.46 9.05 7.44 7.42 VCC(min) [V] VCC(on) [V] 9.00 8.95 8.90 7.38 7.36 7.34 8.85 7.32 8.80 −40 −20 0 20 40 60 80 Temperature [°C] 7.30 −40 −20 100 120 Figure 3. VCC(on) vs. Temperature 6.98 1.00 6.96 0.99 6.94 0.98 6.92 0.97 6.90 0.95 6.86 0.94 0 20 40 60 80 Temperature [°C] 0.93 −40 −20 100 120 400 40 380 35 360 30 340 320 280 10 40 60 80 20 40 60 80 Temperature [°C] 100 120 20 15 20 0 25 300 0 100 120 Figure 6. ICC1 vs. Temperature RDS(on) [W] ICCskip [mA] Figure 5. VCC(off) vs. Temperature 260 −40 −20 20 40 60 80 Temperature [°C] 0.96 6.88 6.84 −40 −20 0 Figure 4. VCC(min) vs. Temperature ICC1 [mA] VCC(off) [V] 7.40 5 −40 −20 100 120 Temperature [°C] 0 20 40 60 80 100 120 Temperature [°C] Figure 7. ICCskip vs. Temperature Figure 8. RDS(on) vs. Temperature www.onsemi.com 8 NCP10970 TYPICAL CHARACTERISTICS − HIGH VOLTAGE SWITCHER 820 5 Vds = 400 V 800 4 IDSS(off) [mA] BVDSS [V] 780 760 740 Vds = 670 V 3 2 1 720 700 −40 −20 0 20 40 60 80 Temperature [°C] 0 −40 −20 100 120 Figure 9. Breakdown voltage vs. Temperature 0 20 40 60 80 Temperature [°C] 100 120 Figure 10. IDSS(off) vs. Temperature 107 355 106 105 345 IFreeze [mA] IPK [mA] 350 340 104 103 102 101 335 100 330 −40 −20 0 20 40 60 80 Temperature [°C] 99 −40 −20 100 120 Figure 11. IPK vs. Temperature 0 20 40 60 80 Temperature [°C] 100 120 Figure 12. IFreeze vs. Temperature 12 21.0 11 20.0 9 VHV(min) [V] Istart1 [mA] 10 8 7 6 19.0 18.0 17.0 5 4 −40 −20 0 20 40 60 80 16.0 −40 −20 100 120 Temperature [°C] 0 20 40 60 80 100 120 Temperature [°C] Figure 13. Istart1 vs. Temperature Figure 14. VHV(min) vs. Temperature www.onsemi.com 9 NCP10970 TYPICAL CHARACTERISTICS − LOW VOLTAGE SECTION 8.46 340 320 8.45 VCCLV1 [V] ICCLV1 [mA] 300 280 260 8.44 8.43 240 220 −40 −20 0 20 40 60 80 Temperature [°C] 8.42 −40 −20 100 120 9 22 8 20 7 18 6 5 4 3 2 −40 −20 20 40 60 80 Temperature [°C] 100 120 Figure 16. VCCLV(on) vs. Temperature RDS(on),VCCLV [W] RDS(on),INT [W] Figure 15. ICCLV1 vs. Temperature 0 16 14 12 10 0 20 40 60 80 8 −40 −20 100 120 Temperature [°C] 0 20 40 60 80 100 120 Temperature [°C] Figure 17. RDS(on),INT vs. Temperature Figure 18. RDS(on),VCCLV vs. Temperature www.onsemi.com 10 NCP10970 3.62 3.67 3.61 3.66 VSW(VCCLV),H [V] VSW(VCCLV),L [V] TYPICAL CHARACTERISTICS − RAW VOLTAGE GENERATION FOR A1 VERSION (3.3 V OUTPUT) 3.60 3.59 −40 −20 0 20 40 60 80 Temperature [°C] 3.64 −40 −20 100 120 Figure 19. VSW(VCCLV),L vs. Temperature 3.82 3.87 3.81 3.86 3.80 3.79 −40 −20 0 20 40 60 80 0 20 40 60 80 Temperature [°C] 100 120 Figure 20. VSW(VCCLV),H vs. Temperature VSW(INT),H [V] VSW(INT),L [V] 3.65 3.85 3.84 −40 −20 100 120 Temperature [°C] 0 20 40 60 80 100 120 Temperature [°C] Figure 21. VSW(INT),L vs. Temperature Figure 22. VSW(INT),H vs. Temperature www.onsemi.com 11 NCP10970 TYPICAL CHARACTERISTICS − RAW VOLTAGE GENERATION FOR B1 VERSION (5 V OUTPUT) 5.33 5.40 5.32 VSW(VCCLV),H [V] VSW(VCCLV),L [V] 5.39 5.31 5.38 5.37 5.36 5.30 −40 −20 0 20 40 60 80 5.35 −40 −20 100 120 0 Temperature [°C] 40 60 80 100 120 Figure 24. VSW(VCCLV),H vs. Temperature 5.53 5.59 5.52 5.58 VSW(INT),H [V] VSW(INT),L [V] Figure 23. VSW(VCCLV),L vs. Temperature 5.51 5.50 5.49 −40 −20 20 Temperature [°C] 5.57 5.56 0 20 40 60 80 5.55 −40 −20 100 120 Temperature [°C] 0 20 40 60 80 100 120 Temperature [°C] Figure 25. VSW(INT),L vs. Temperature Figure 26. VSW(INT),H vs. Temperature www.onsemi.com 12 NCP10970 TYPICAL CHARACTERISTICS − LOW DROPOUT REGULATOR 310 3.32 300 290 VLDDOOUT [V] ICL [mA] 280 270 260 3.31 3.30 250 240 230 −40 −20 0 20 40 60 80 Temperature [°C] 3.29 −40 −20 100 120 Figure 27. ICL vs. Temperature 100 120 1.8 1.7 5.01 VDO [V] 1.6 5.00 1.5 4.99 1.4 4.98 −40 −20 0 20 40 60 80 1.3 100 120 −40 −20 0 Temperature [°C] 20 40 60 80 100 120 Temperature [°C] Figure 29. VLDOOUT vs. Temperature (B Version) Figure 30. VDO vs. Temperature 80 6 Noise Spectral Density [mVrms/√Hz] 70 60 PSRR [dB] 20 40 60 80 Temperature [°C] Figure 28. VLDOOUT vs. Temperature (A Version) 5.02 VLDOOUT [V] 0 50 40 Cout = 1 mF Cout = 2.2 mF Cout = 4.7 mF Cout = 10 mF 30 20 10 0 1E−2 1E−1 1E+0 1E+1 1E+2 Frequency [kHz] 1E+3 Cout = 1 mF Cout = 2.2 mF Cout = 4.7 mF 5 4 3 2 1 0 1.E−02 1E+4 Figure 31. PSRR vs. Frequency 1.E−01 1.E+00 1.E+01 Frequency [kHz] 1.E+02 Figure 32. Noise vs. Frequency www.onsemi.com 13 1.E+03 NCP10970 4.70 0.85 4.65 0.80 4.60 0.75 4.55 0.70 VCMP(Hyst) [V] VCMP(on) [V] TYPICAL CHARACTERISTICS − COMPARATOR 4.50 4.45 0.60 4.40 0.55 4.35 0.50 4.30 −40 −20 0 20 40 60 80 Temperature [°C] 0.45 −40 −20 100 120 Figure 33. VCMP(on) vs. Temperature 0 20 40 60 80 Temperature [°C] 100 120 Figure 34. VCMP(Hyst) vs. Temperature 1.03 0.83 1.02 0.82 Vrestart [V] Vstop [V] 0.65 1.01 1.00 0.81 0.80 0.99 −40 −20 0 20 40 60 80 Temperature [°C] 0.79 −40 −20 100 120 Figure 35. Vstop vs. Temperature 0 20 40 60 80 Temperature [°C] 100 120 Figure 36. Vrestart vs. Temperature 120.6 75 120.4 70 120.2 65 tdel [ns] Iref1 [mA] 120.0 119.8 119.6 60 55 119.4 50 119.2 119.0 −40 −20 0 20 40 60 80 Temperature [°C] 45 −40 −20 100 120 Figure 37. Iref1 vs. Temperature 0 20 40 60 80 Temperature [°C] Figure 38. tdel vs. Temperature www.onsemi.com 14 100 120 NCP10970 APPLICATIONS INFORMATION pin and control the current peak value. The switching frequency is setup to its maximum and keep based on the load condition by DMG control. Skip operation ensures a good efficiency when the output power demand diminishes. By skipping un−needed switching cycles, the NCP10970 drastically reduces the power wasted during light load conditions. Integrated linear regulator provides a 3.3 V or 5 V (based on chosen version) of output voltage on short−circuit protected output. Supplied by a raw dc voltage derived from the high−voltage buck in a proprietary way, it maintains a good efficiency while offering low quiescent current. Comparator circuitry can be used for over−temperature detection. The input pin of comparator – CMPIN pin – is permanently biased by a precise constant current source. By connecting a pull−down PTC thermistor to this pin, the circuit can deliver a low signal in case a temperature runaway is sensed. The low signal is present on output pin of comparator – CMPOUT pin – that is an open drain type. Standby circuit affects the speed of the Comparator tdel and also the current consumption of the Low Voltage part – ICCLV1 vs ICCLV4. If the STBY pin is suddenly grounded (or after startup of the IC), the IC goes to the standby mode after 20 ms. When the IC is in standby mode and STBY pin goes to High State (>3 V on pin, pin max rating is 5.5 V), the IC goes to active mode after 4 ms max – it is called as wake−up time from standby mode to active mode. This NCP10970 integrated circuit associates a high−voltage switcher configured to drive a buck topology with a low−voltage die hosting a linear regulator and dedicated comparator circuitry. The buck circuit delivers output voltage up to 16 V (adjustable by resistor divider on FB pin) from universal mains input and using a proprietary downstream converter technique creates 3.3 V or 5 V in an effective way. Current−mode operation with detection end of demagnetization: the high−voltage switcher uses fixed−frequency current−mode control architecture. A dedicated pin DMG permanently monitors the magnetic activity in the inductor and prevents from entering the continuous conduction mode (CCM). The DMG pin has to be connected through proper resistor value to the end of the inductor. 670 V MOSFET: the switcher contains a high−voltage low−power MOSFET with a 18 W RDS(on) @ TJ = 25°C. The dissipated heat of the power transistor is conducted out through the SOURCE pin. Dynamic Self−Supply contains an internal high−voltage start−up current source. This device can be used in applications in which no auxiliary winding provides a supply voltage or in application with low output voltage, for example 5 V. For power dissipation concerns but also for best stand−by power performance, we recommend to disable DSS operation by providing a self−supply to the switcher. Short circuit protection is permanently monitoring the COMP pin activity. The controller is able to detect the short−circuit condition and immediately reduce the output power for a total system protection. A fault timer is started as soon as the COMP current is below a threshold, ICOMPfault, which indicates the maximum peak current. If the fault is still present at the end of this timer, then the device enters a safe, auto−recovery burst mode, affected by a fixed timer recurrence, trecovery. Once the short has disappeared, the controller resumes operations. Built−in VCC Over Voltage Protection is monitoring the voltage on the VCC pin. When the voltage exceeds a level of VOVP (18 V typically), the controller immediately stops switching and waits for a time period given by a trecovery before attempting to restart. If the fault is gone, the controller resumes operation. If the fault is still there, the controller is again in protection mode and waits another time period trecovery before attempting to restart. Soft−Start: a 4 ms soft−start ramp ensures a smooth startup sequence and reduces output overshoots. Current control ensures a good efficiency for changing output power demands. The controller observes the COMP Start−up Sequence of Switcher During start−up sequence of NCP10970, the supply voltage for switcher (VCC pin) is created by an internal high−voltage start−up current source. This startup−up current source can be used as a DSS (Dynamic self−supply) in case that supply voltage is not present or doesn’t reach the necessary voltage value. The internal HV start−up current source is active when the voltage on DRAIN pin is above VHV(min) level. This start−up current source can charges up the CVCC capacitor connected to VCC pin by typical current value Istart1. In case of damaged or missing CVCC capacitor, the device is protected against self−destruction by limiting the start−up current to Istart2 value till the voltage on VCC pin is higher than VCC(th) value. If the VCC voltage touches the VCC(on) level, the current source is turned off and the internal DRV pulses of switcher transistor are authorized. If the VCC voltage decreases below the VCC(min) level, the current source is turned on again till the VCC voltage increase to VCC(on) level, than the current source is turned off again. Figure 39 shows the internal start−up logic for control the high−voltage start−up current source. www.onsemi.com 15 NCP10970 HV voltage DRAIN SOURCE + VDRV VCC(min) _ Istart 1 Istart 2 VCC Q S Q R + _ Toggle Istart 1 / Istart 2 + CBulk VCC(on) + _ VCCth + CVCC Figure 39. Internal Control Logic of HV Start−up Current Source Soft−start The NCP10970 features 4 ms soft−start ramp which reduces the power−on stress but also contributes to lower overshoot of output voltage. Figure 40 shows a typical operating waveform. Soft−start ramp is applied during first start of application and upon every restart, i.e. auto−recovery restart of application after fault state. vCC (t) VCC(on) VCCth t vDRV (t) Internal signal t iPK (t) vOUT (t) Switcher output voltage IPK(max) 4 ms soft−start ramp t t Figure 40. The 4 ms Soft−start Ramp during Start−up Sequence Demagnetization Detection switching period came as first. Therefore, the demagnetization detection block doesn’t authorize new switching cycle till the inductor demagnetization phase is not finished. The end of demagnetization is sensed by threshold voltage level VDMG(th) which is valid for decreasing voltage. The new DRV pulse is present after propagation delay tdem of the demagnetization detection block. The unwanted demagnetization detection is secured by a hysteresis on demagnetization threshold level and blanking time. To avoid the CCM operation during heavy load conditions, the switcher in NCP10970 is equipped by demagnetization detection block. Demagnetization detection block affects the switching frequency of the switcher as it shown in Figure 41. Switching frequency is determined by a frequency oscillator when on−time plus off−time are shorter than switching period time. Otherwise, the switcher is forced to wait for the end of the inductor demagnetization although the end of the www.onsemi.com 16 NCP10970 tblank iPK (t) vDMG (t) tdem VDMG (th) vDRV (t) t TSW = 15.4 µs t Figure 41. Switching Waveforms with Demagnetization Detection during Light and Heavy Load Operation demagnetization detection. Resistance of external resistor R1 has to be chosen based on maximum current value IDMG,clamp flowing through the clamp diode. Recommended connection of DMG pin shows Figure 42. External resistor R1 and internal resistor Rint create resistor divider. The divider ratio should be chosen with respect to VDMG(th) value, which is important for proper end of SOURCE R1 + VDMG(th) DMG _ Cint Clamp diode Rint Figure 42. Recommended Connection of DMG Pin Current and Switching Frequency Control The current peak control mechanism is clearly described in Figure 43. The switching frequency control is based on interrupting of the switching in Skip mode. Out of the Skip mode, the full switching frequency is setup, but with limiting by the demagnetization detection block. It means, the switching frequency is determined by the application, not by a device itself. The improvement of the efficiency during light load and reduction of no−load standby power requires change of the switching frequency and current peak setpoint depending on the state of the load. Therefore, this device implements a current and switching frequency control when the COMP current passes a certain levels. Ipk [mA] IPk Full peak IFreeze Skip mode 350 mA Frozen peak 110 mA ICOMP100% −44 mA ICOMPfreeze −80 mA ICOMPskip −120 mA ICOMP [mA] Figure 43. By Observing the Current on the COMP Pin, the Controller Changes its Current Peak Setpoint and Switching Frequency to Improved Performance at Light Load Conditions COMP Pin this linear operating range, the dynamic resistance is 17.7 kW typically (RCOMP(up)) and the effective pull−up voltage is 2.7 V typically (VCOMP(REF)). When ICOMP is decreases, the COMP voltage is increased to 3.2 V. Figure 44 depicts the relationship between COMP pin voltage and current. The COMP pin operates linearly as the absolute value of COMP current (ICOMP) is above 40 mA. In www.onsemi.com 17 NCP10970 4,0 3,5 VCOMP [V] 3,0 2,5 2,0 1,5 1,0 0,5 0,0 0 20 40 60 80 100 120 140 160 ICOMP [mA] Figure 44. COMP Pin Voltage vs. COMP Current FB Pin Function Auto−recovery Over−Voltage Protection The portion of the output voltage is connected into the pin. The pin voltage is compared with internal VREF (3.3 V) using Operation Transconductance Amplifier (Figure 45). The OTAs output is connected to COMP pin. The compensation resistor network is connected to the COMP pin. The current capability of OTA is limited to −150 mA typically. The positive current is defined by internal RCOMP(up) resistor and VCOMP(ref) voltage. If FB path loop is broken (i.e. the FB pin is disconnected), an internal current IFB (1 mA typ.) will pull up the FB pin and the IC stops switching to avoid uncontrolled output voltage increasing. The particular switcher of NCP10970 arrangement offers a simple way to prevent output voltage runaway when the compensation network fails. Therefore, a comparator monitors the VCC pin. If there is an over−voltage condition on the CVCC capacitor, the controller considers it as an OVP situation. To avoid some unwanted OVP situation, there is implemented filter with time constant tOVP. If fault is present for whole tOVP time, the fault is confirmed and the internal pulses are immediately stopped. The controller enters to auto−recovery protection mode, and normal operation will be resumed after trecovery time constant. If the fault condition still exists, the device enters to the protection mode again. IFB VCC OTA out = 0 A if FB = 0 V FB Shut down Internal DRV OTA VCOMP (REF) RCOMP (up) VREF 80 ms filter IOTAlim ICOMP CVCC VOVP Source COMP Figure 45. FB Pin Connection Schematic Figure 46. Realization of OVP Protection on VCC Pin VOVP VCC(on) VCC(min) VCC ICOMP 48 ms typ. Fault level TIMER 400 ms typ. DRV internal Figure 47. The Switcher Auto−recovers to Normal Operation after Over−voltage on VCC Pin www.onsemi.com 18 NCP10970 Auto−recovery Short−Circuit Protection reached its maximum current limit setpoint. The assertion of this Ipflag triggers a fault counter tSCP (48 ms typically). If Ipflag remains asserted when the tSCP counter elapses, all driving pulses are stopped and in trecovery duration (about 400 ms). A new attempt to re−start occurs and will last 48 ms providing the fault is still present. When the fault disappears, the power supply quickly resumes operation. Figure 48 depicts this particular mode. As soon as VCC reaches VCC(on), drive pulses are internally enabled. If everything is correct, the output voltage rises and starts to supply the VCC capacitor. When the output voltage is not regulated, the current coming through COMP pin is below ICOMPfault level (40 mA typically), which is not only during the startup period but also anytime an overload situation occurs, an internal error flag is asserted, Ipflag is indicating that the system has VCC (on) VCC V (min) CC IpFlag Open loop FB VCOMP Fault 48 ms typ. Timer 400 ms typ. DRV internal Figure 48. In Case of Short*circuit or Overload, the Switcher of NCP10970 Protects Itself and the Power Supply via a Low Frequency Burst Mode. The VCC is Maintained by the DSS Function of the Start−up Current Source Start−up Sequence of Low Voltage Section voltage to its nominal value given by a VSW(INT),H. During this start−up sequence is active the switch SWINT only, i.e. the switch SWVCCLV is blocked until the VRAW voltage reaches the VSW(INT),H voltage level. The LDO output voltage is ramping−up after the VRAW reaches its nominal value to achieve smooth and linear rise ramp of this voltage. Figure 49 shows the operation during start−up sequence. The switcher starts switching when the supply voltage VCC reaches VCC(on) level and therefore the output voltage of the switcher is ramping−up. The supply pin VCCLV of the low voltage section is connected to the switcher output voltage. When the VCCLV voltage reaches the VCCLV(on) level, the switch SWINT is active to ramp−up the VRAW www.onsemi.com 19 NCP10970 vCCLV (t) vCC (t) Switcher starts operate VCC(on) VCC – supply voltage for switcher die VCCLV – output voltage of a switcher and supply voltage for Low Voltage die VCCLV(on) VCCth SW(INT) Internal DRV pulses SW(VCCLV) Internal DRV pulses vRAW (t) vLDOOUT (t) Switch is OFF Switch is ON t t Switch SWVCCLV is blocked t VSW(INT),H VSW(INT),L VSW(VCCLV ),H VSW(VCCLV ),L VLDOOUT VRAW – LDO input voltage VLDOOUT – LDO output voltage t Figure 49. Startup Waveforms of the Switcher and Low Voltage Section with LDO Steady−state and Transient Operation of Switcher and LDO transient states. Figure 50 shows the behavior of the switches during steady state and transient state, when the LDO output rail is heavy loaded. Both switches are turned−on when the VRAW voltage touches the turn−on voltage reference, i.e. VSW(INT),L and VSW(VCCLV),L, and turned−off when the VRAW voltage touches turn−off voltage reference VSW(VCCLV),H and VSW(INT),H. During steady−state operation, the switch SWINT is switching to supply the LDO. If this energy delivering is not enough, there is a switch SWVCCLV, which can supply the LDO from the output capacitor connected to switcher output rail. The switch SWVCCLV is turned−on especially during Steady−state operation Heavy load on LDO output rail Drop on switcher output rail force the switcher to deliver more energy vSWOUT (t) Switcher output rail VSW(INT),H vRAW (t) t VSW(INT),L VSW(VCCLV),H VSW(VCCLV),L t SW(INT) Internal DRV pulses SW(VCCLV) Internal DRV pulses t Switch Switch is OFF is ON Figure 50. Steady State Waveforms of the Switcher and Low Voltage Section with LDO Power−down Operation of Switcher and LDO cannot be ensured through INT switch, so the energy is transferred from capacitor on switcher output voltage rail through VCCLV switch. Figure 51 shows the behavior of the switches during power−down. This operation mode is showing the behavior of the controller when the input HV voltage is unplugged. When the input voltage is no longer present, the energy for LDO www.onsemi.com 20 NCP10970 HV inut voltage Unplugged vHV (t) Switcher off due to VCC = UVLO t vSWOUT (t) Switcher output rail t vDRV (t) Switcher DRV pulses t VSW(INT),H vRAW (t) VSW(INT),L VSW(VCCLV),H VSW(VCCLV),L t SW(INT) Internal DRV pulses Switch is ON SW(VCCLV) Internal DRV pulses t Switch is OFF t Figure 51. Power−down Behavior of the Switcher and Low Voltage Section with LDO Linear Regulator grounded. Standby mode affects the propagation delay tdel of the comparator. Over−temperature detection is based on pull−down PTC thermistor connected to CMPIN pin. Internal current source force the current value Iref1 = 120 mA through the PTC. If the over−temperature condition appears, the resistance of the PTC thermistor increases, i.e. the sensed voltage reaches the value Vstop = 1 V and the comparator turned−on the internal MOSFET, which force the CMPOUT pin to the Low state. The de−bouncing time constants tdel1 = 50 ms and tdel2 = 10 ms on comparator output can be implemented as an option. The CMPOUT pin goes back to High Z state, when the sensed voltage on PTC decreases below the value Vrestart = 0.8 V. Figure 52 shows the comparator operation with/without de−bouncing filter based on input voltage on CMPIN pin. The integrated LDO regulator is an NMOS type for better output stability. The output voltage is fixed 3.3 V or 5 V based on chosen version (see ordering information table on page 22) and output current is limited to 260 mA @ TJ = 25°C as a short−circuit protection of LDO output. The input voltage of LDO regulator is VRAW voltage and the LDO is supplied from VCCLV voltage. Comparator The input of this circuitry is CMPIN pin, which is biased by a current source during all operational conditions. Comparator connected to the CMPIN pin turns−on and off the internal MOSFET transistor connected to COMPOUT pin – this pin is open−drain. The Speed of the Comparator is determined by the active or standby of the IC, i.e. the Comparator is in standby mode when the STBY pin is VCMPIN (t) Vstop = 1 V Vrestart = 0.8 V VCMPOUT (t) t Without debouncing filter With debouncing filter t tdel2 tdel1 tdel2 tdel1 t Figure 52. Over−temperature/Over−current Detection with/without De−bouncing Filter www.onsemi.com 21 NCP10970 above 0.8 V when the VCCLV touches the VCMP(on) level, the CMPOUT pin is forced to low. The internal current source Iref1 has its nominal value when supply voltage VCCLV is above 3.7 V. Figure 53 shows the behavior of the comparator based on supply voltage VCCLV. The CMPOUT pin is forced low during startup independently of voltage on CMPIN pin when the supply voltage is between 2.5 V and VCMP(on) = 4.4 V. When the supply voltage VCCLV touches the VCMP(on) = 4.4 V level, the CMPOUT pin is forced low or keep in High Z state based on input voltage on CMPIN pin. If the CMPIN voltage is VCCLV (t) 2.5 V 3.7 V 4.4 V 3.7 V 2.5 V t Iref1 (t) 120 mA t VCMPIN (t) Green line for VCMPIN > 0.8 V Blue line for VCMPIN < 0.8 V t VCMPOUT (t) High Z Low state High Z Low state Green line for VCMPIN > 0.8 V t VCMPOUT (t) High Z Blue line for VCMPIN < 0.8 V t Figure 53. Operational Condition of the Comparator Based on Supply Voltage Thermal Shutdown over−temperature detection are disabled. The CMPOUT pin is set to Low state as an indication of the over−temperature condition. All components are enabled again when the silicon temperature fall by 20°C. Internal TSD protects the silicon against self−destruction due to high temperature. If the temperature on silicon reaches 160°C typically, LDO output and input of ORDERING INFORMATION VCCLV Switch INT Switch References Device Maximum Peak Current VCCLV (on) NCP10970A1DR2G 350 mA 8.4 V 3.60 V / 3.65 V 3.80 V / 3.85 V NCP10970B1DR2G 350 mA 8.4 V 5.30 V / 5.35 V 5.50 V / 5.55 V LDO Output Voltage Package Shipping† 3.3 V SOIC−16NB (Pb−Free) 2500 / Tape & Reel 5V SOIC−16NB (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 22 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−16 NB, LESS PIN 15 CASE 752AC−01 ISSUE O DATE 28 JAN 2011 SCALE 1:1 D 16 A B 9 E H 0.25 M B M 1 8 e 15X 15X C b 0.25 C L M T A S B DIM A A1 b C D E e H h L M S A1 SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE b DIMENSION AT MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. h x 45 _ A M GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT 16 6.40 15X XXXXXXXXXXXXG XXXXXXXXXXXXX AWLYWW 1.12 1 MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 9.80 10.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_ 16 1 15X 0.58 1.27 PITCH 8 9 XXXXX A WL Y WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G”, may or not be present. DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: DESCRIPTION: 98AON55422E SOIC−16 NB, LESS PIN 15 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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