NCP1124, NCP1126,
NCP1129
High Voltage Switcher for
Offline Power Supplies
The NCP112x products integrates a fixed−frequency peak current
mode controller with a low on−resistance, 650 V MOSFET. Available
in a PDIP−7 package, the NCP112x offers a high level of integration,
including soft−start, frequency−jittering, short−circuit protection,
thermal shutdown protection, frequency foldback mode and
skip−cycle to reduce power consumption in light load condition, peak
current mode control with adjustable internal ramp compensation and
adjustable peak current set point.
During nominal load operation, the part switches at one of the
available frequencies (65 or 100 kHz). When the output power
demand diminishes, the IC automatically enters frequency foldback
mode and provides excellent efficiency at light loads. When the power
demand reduces further, it enters into a skip mode to reduce the
standby consumption down to no load condition.
Protection features include: a timer to detect an overload or a
short−circuit event with auto−recovery or latch protection, and a
built−in VCC overvoltage protection.
The switcher also provides a jittered 65 kHz or 100 kHz switching
frequency to improve the EMI.
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PDIP−7
P SUFFIX
CASE 626B
MARKING DIAGRAMS
112xyPzzz
AWL
YYWWG
1
x
y
Features
•
•
•
•
•
•
•
•
•
•
•
Built−in 650 V, 1 A MOSFET with RDS(on) of 8.6 W for NCP1124
Built−in 650 V, 1.8 A MOSFET with RDS(on) of 5.4 W for NCP1126
Built−in 650 V, 5.5 A MOSFET with RDS(on) of 2.1 W for NCP1129
Fixed−Frequency 65 or 100 kHz Current Mode Control with
Adjustable Internal Ramp Compensation
Adjustable Current Limit with External Resistor
Frequency Foldback Down to 26 kHz and Skip−Cycle for Light Load
Efficiency
Frequency Jittering for EMI Improvement
Less than 100 mW Standby Power @ High Line
EPS 2.0 Compliant
7−Pin Package Provides Creepage Distance
These are Pb−Free Devices
zzz
A
WL
YY
WW
G
= Specific Device Code
4 = NCP1124
6 = NCP1126
9 = NCP1129
= A or B
A = Latch
B = Auto−recovery
= Frequency
65 = 65 kHz
100 = 100 kHz
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information on page 17 of
this data sheet.
Table 1. OUTPUT POWER TABLE (Note 1)
230 Vac + 15% (Note 4)
Adapter (Note 2)
Peak or Open Frame (Note 3)
Adapter (Note 2)
Peak or Open Frame (Note 3)
NCP1124
12 W
27 W
6W
14 W
NCP1126
15 W
32 W
10 W
17 W
NCP1129
28 W
43 W
20 W
26.5 W
Product
1.
2.
3.
4.
85 − 265 Vac
12 V output voltage with 135 V reflected output voltage
Typical continuous power in a non-ventilated enclosed adaptor measured at 50°C ambient temperature.
Maximum practical continuous power in an open-frame design at 50°C ambient temperature
230 VAC or 115 VAC with voltage doubler.
© Semiconductor Components Industries, LLC, 2015
March, 2015 − Rev. 3
1
Publication Order Number:
NCP1126/D
NCP1124, NCP1126, NCP1129
Figure 1. Typical Application
Table 2. PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
1
VCC
Pin Description
This pin is connected to an external auxiliary voltage and supplies the controller. When above a certain
level, the part fully latches off.
2
FB
Feedback input. Hooking an optocoupler collector to this pin will allow regulation.
3
CS
This pin monitors the primary peak current but also offers a means to introduce ramp compensation.
4
Source
Source of the internal MOSFET. This pin is typically connected to the source of a grounded sense resistor.
5
Drain
6
Drain
The drain of the internal MOSFET. These pins connect to the transformer terminal and can withstand up to
650 V.
7
−
8
GND
Removed for creepage distance.
Ground reference.
Table 3. OPTIONS
Switcher
Package
Frequency
Short−Circuit Protection
NCP1124AP65G
PDIP−7
65 kHz
Latch
NCP1124BP65G
PDIP−7
65 kHz
Auto−Recovery
NCP1124AP100G
PDIP−7
100 kHz
Latch
NCP1124BP100G
PDIP−7
100 kHz
Auto−Recovery
NCP1126AP65G
PDIP−7
65 kHz
Latch
NCP1126BP65G
PDIP−7
65 kHz
Auto−Recovery
NCP1126AP100G
PDIP−7
100 kHz
Latch
NCP1126BP100G
PDIP−7
100 kHz
Auto−Recovery
NCP1129AP65G
PDIP−7
65 kHz
Latch
NCP1129BP65G
PDIP−7
65 kHz
Auto−Recovery
NCP1129AP100G
PDIP−7
100 kHz
Latch
NCP1129BP100G
PDIP−7
100 kHz
Auto−Recovery
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2
NCP1124, NCP1126, NCP1129
UVLO
VCC and logic
management
double hiccup
VDD
Vcc
Ipflag
−
+
Power
On Reset
S Q
Q
VOVP
R
VDD
+
−
Drain
4 kW
Power
on reset
Clamp
RLIM
Source
65/100 kHz
clock
Frequency
Modulation
+
S
−
Q
Q
+
R
Frequency
foldback
Slope
Compensation
Vfold
− +
− V
skip
+
+
RFB
FB
The soft start is activated
− startup process
− auto recovery
Rramp
/4
+
−
−
VDD
4 ms 5 s
250 mV Peak
Current Freeze
VILIM
Ipflag
CS
LEB
Figure 2. Functional Block Diagram
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3
GND
NCP1124, NCP1126, NCP1129
Table 4. MAXIMUM RATINGS (Note 5)
Rating
Symbol
Value
Unit
Drain Input Voltage (Referenced to Source Terminal)
NCP112x
VDrain
−0.3 to 650
V
Drain Maximum Pulsed Current
(10 ms Single Pulse, TJ = 25°C)
NCP1129
NCP1126
NCP1124
IDM
27
11
7
A
Single Pulse Avalanche Energy
NCP1126, NCP1129
NCP1124
EAS
96
60
mJ
VCC(MAX)
−0.3 to 35
V
Current Sense Input Voltage
VCS
−0.3 to 10
V
Feedback Input Voltage
VFB
−0.3 to 10
V
TJ
−40 to 150
_C
TSTG
–60 to 150
_C
PD
1.5
W
Supply Input Voltage
Operating Junction Temperature
Storage Temperature Range
Power Dissipation (TA = 25_C, 2 Oz Cu, 600
mm2 Printed
Circuit Copper Clad)
Thermal Resistance, Junction to Ambient 2 Oz Cu Printed Circuit Copper Clad
Low Conductivity (Note 6)
High Conductivity (Note 7)
ESD Capability (Note 8)
Human Body Model ESD Capability per JEDEC JESD22−A114F.
Machine Model ESD Capability per JEDEC JESD22−A115C.
Charged−Device Model ESD Capability per JEDEC JESD22−C101E.
RθJA
_C/W
128
78
V
2000
200
500
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
5. This device contains Latch−Up protection and exceeds ±100 mA per JEDEC Standard JESD78.
6. Low Conductivity Board. As mounted on 40 x 40 x 1.5 mm FR4 substrate with a single layer of 50 mm2 of 2 oz copper trances and heat
spreading area. As specified for a JEDEC 51 low conductivity test PCB. Test conditions were under natural convection of zero air flow.
7. High Conductivity Board. As mounted on 40 x 40 x 1.5 mm FR4 substrate with a single layer of 600 mm2 of 2 oz copper trances and heat
spreading area. As specified for a JEDEC 51 high conductivity test PCB. Test conditions were under natural convection of zero air flow.
8. The Drain pins (5 and 6), are rated to the maximum voltage of the device, or 650 V.
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4
NCP1124, NCP1126, NCP1129
Table 5. ELECTRICAL CHARACTERISTICS
(VCC = 12 V, for typical values TJ = 25_C, for min/max values, TJ is –40_C to 125_C, unless otherwise noted)
Characteristics
Conditions
Symbol
Min
Typ
Max
Unit
VCC increasing
VCC decreasing
VCC(on) − VCC(off)
VCC(on)
VCC(off)
VCC(HYS)
15.75
7.75
6.0
17
8.5
–
20
9.25
–
VCC Overvoltage Protection Threshold
VCC(OVP)
26.3
28
29.3
V
VCC Overvoltage Protection Filter Delay
tOVP(delay)
–
26
–
ms
VZENER
5
6.2
7.15
STARTUP AND SUPPLY CIRCUITS
Supply Voltage
Startup Threshold
Minimum Operating Voltage
Operating Hysteresis
V
VCC Clamp Voltage in Latch Mode
Supply Current
Startup Current
Skip Current
Operating Current at 65 kHz
Operating Current at 100 kHz
ICC = 500 mA
V
mA
VCC = VCC(on) – 0.5 V
VFB = Vskip − 0.1 V
IFB = 50 mA, fSW = 65 kHz
IFB = 50 mA, fSW = 100 kHz
ICC1
ICC2
ICC3
ICC4
–
–
–
–
–
700
1900
3300
15
900
3100
4000
TJ = –40_C to 125_C
ICC(latch)
42
–
–
mA
TJ = 125_C, VDrain = 650 V
IDrain(off)
–
–
20
mA
TJ = 25_C, IDrain = 250 mA, VFB = 0 V
VBR(DSS)
650
–
–
V
IDrain = 100 mA
VCC = 10 V, TJ = 25_C
VCC = 10 V, TJ = 125_C
VCC = 10 V, TJ = 25_C
VCC = 10 V, TJ = 125_C
VCC = 10 V, TJ = 25_C
VCC = 10 V, TJ = 125_C
RDS(on)
−
−
−
−
−
−
2.1
−
5.4
−
9.0
−
2.75
5.0
7.7
13.1
13.2
23.5
NCP1129
NCP1126
NCP1124
VDS = 25 V, VCC = 0 V, f = 1 MHz
VDS = 25 V, VCC = 0 V, f = 1 MHz
VDS = 25 V, VCC = 0 V, f = 1 MHz
COSS
–
−
−
67.3
29.2
16.5
–
–
−
Rise Time
Fall Time
Rise Time
Fall Time
Rise Time
Fall Time
(VDS = 325 V, IDrain = 1 A,
VGS = 10 V, Rg = 4.7 W)
(VDS = 325 V, IDrain = 1.8 A,
VGS = 10 V, Rg = 4.7 W)
(VDS = 325 V, IDrain = 5.5 A,
VGS = 10 V, Rg = 4.7 W)
tr
tf
tr
tf
tr
tf
−
−
−
−
−
−
4.25
9.32
7.44
5.94
7.54
5.94
−
−
−
−
−
−
VCS increasing, TJ = 25_C
VCS increasing
VILIM1
VILIM2
730
720
785
800
840
880
VCS dv/dt = 1 V/ms, measured from
VILIM1 to DRV falling edge
tCS(delay)
Current Consumption in Latch Mode
POWER SWITCH CIRCUIT
Off−State Leakage Current
Breakdown Voltage
ON State Resistance
NCP1129
NCP1126
NCP1124
Output Capacitance
Switching Characteristics
NCP1124
NCP1126
NCP1129
W
pF
ns
CURRENT SENSE
Current Sense Voltage Threshold
Cycle by Cycle Current Sense
Propagation Delay
NCP1129
NCP1126
NCP1124
Cycle by Cycle Leading Edge Blanking
Duration
mV
ns
–
−
−
100
50
50
150
150
150
tCS(LEB)
–
320
400
ns
fOSC1
fOSC2
61
92
65
100
71
108
kHz
DMAX
78
80
82
%
fjitter
–
±5
–
%
INTERNAL OSCILLATOR
Oscillation Frequency
65 kHz Version
100 kHz Version
Maximum Duty Ratio
Frequency Jittering in Percentage of fOSC
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5
NCP1124, NCP1126, NCP1129
Table 5. ELECTRICAL CHARACTERISTICS
(VCC = 12 V, for typical values TJ = 25_C, for min/max values, TJ is –40_C to 125_C, unless otherwise noted)
Characteristics
Conditions
Symbol
Min
Typ
Max
Unit
Internal Pull−up Resistor
Rup
–
13
–
kW
Equivalent ac resistor from FB to GND
Req
–
15
–
kW
VFB to Internal Current Setpoint
Division Ratio
Iratio
–
4
–
–
VFB(freeze)
0.85
1
1.15
V
VFB(fold)
1.35
1.5
1.78
V
ftrans
22
26
30
kHz
VFB(fold,end)
410
450
490
mV
FEEDBACK SECTION
Feedback Voltage Below Which the
Peak Current is Frozen
FREQUENCY FOLDBACK
Frequency Foldback Level on the FB
47% of maximum peak current
Transition Frequency Below Which
Skip−Cycle occurs
Feedback voltage level when
Frequency Foldback ends
fSW = fMIN
Skip−Cycle Level Voltage on The FB pin
Vskip
360
400
440
mV
Vskip(HYS)
–
40
–
mV
Measured from 1st drive pulse to
VCS = VILIM
tSSTART
–
4.0
–
ms
VCS = VILIM
tOVLD
35
50
65
ms
(Note 9)
TSD
130
−
–
_C
–
20
–
_C
Hysteresis on The Skip Comparator
FAULT PROTECTION
Soft−Start Period
Overload Fault Timer
TEMPERATURE MANAGEMENT
Temperature Shutdown
Hysteresis
Guaranteed by Design
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
9. The value is not subjected to production test − verified by design/characterization. The thermal shutdown temperature refers to the junction
temperature of the controller.
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6
NCP1124, NCP1126, NCP1129
TYPICAL CHARACTERISTICS
725
2.2
100 kHz
720
2.15
2.1
100 kHz
710
ICC3 (mA)
ICC2 (mA)
715
65 kHz
705
700
2.05
2
65 kHz
695
1.95
690
685
−50
−25
0
25
50
75
100
1.9
−50
125
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 3. NCP1124 ICC2 vs. Junction
Temperature
Figure 4. NCP1124 ICC3 vs. Junction
Temperature
730
2.6
720
2.5
125
100 kHz
710
2.4
ICC3 (mA)
65 kHz
ICC2 (mA)
−25
700
100 kHz
690
2.3
2.2
680
65 kHz
2.1
670
660
2.0
−40
0
25
85
125
−40
0
25
85
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 5. NCP1126 ICC2 vs. Junction
Temperature
Figure 6. NCP1126 ICC3 vs. Junction
Temperature
725
3.8
720
3.6
715
3.4
ICC3 (mA)
ICC2 (mA)
100 kHz
710
65 kHz
100 kHz
705
3.2
3.0
700
2.8
695
2.6
690
65 kHz
2.4
−40
−25
0
25
85
100
125
−40
−25
0
25
85
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. NCP1129 ICC2 vs. Junction
Temperature
Figure 8. NCP1129 ICC3 vs. Junction
Temperature
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7
125
NCP1124, NCP1126, NCP1129
TYPICAL CHARACTERISTICS
40
0.795
0.790
65 kHz
65 kHz
0.785
100 kHz
VILIM (V)
ICC(latch) (mA)
30
20
100 kHz
0.780
0.775
0.770
10
0.765
0
−50
−25
0
25
50
75
100
0.760
−50
125
0
25
50
75
100
TEMPERATURE (°C)
Figure 9. NCP1124 ICC(latch) vs. Junction
Temperature
Figure 10. NCP1124 VILIM vs. Junction
Temperature
125
0.795
40
100 kHz
0.790
65 kHz
30
0.785
VILIM (V)
ICC(latch) (mA)
−25
TEMPERATURE (°C)
20
65 kHz
0.780
0.775
100 kHz
0.770
10
0.765
0.760
0
−40
0
25
85
−40
125
25
85
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. NCP1126 ICC(latch) vs. Junction
Temperature
Figure 12. NCP1126 VILIM vs. Junction
Temperature
40
0.795
65 kHz
35
0.790
100 kHz
100 kHz
30
VILIM (V)
ICC(latch) (mA)
0
25
20
0.785
65 kHz
0.780
0.775
15
0.770
−40
−25
0
25
85
100
125
−40
−25
0
25
85
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. NCP1129 ICC(latch) vs. Junction
Temperature
Figure 14. NCP1129 VILIM vs. Junction
Temperature
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8
125
NCP1124, NCP1126, NCP1129
TYPICAL CHARACTERISTICS
1.035
1.7
65 kHz
1.03
1.025
1.65
100 kHz
1.015
Vfold (V)
Vfreeze (V)
1.02
1.01
1.005
1.6
65 kHz
1.55
1
100 kHz
0.995
1.5
0.99
0.985
−50
−25
0
25
50
75
100
125
1.45
−50
−25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 15. NCP1124 Vfreeze vs. Junction
Temperature
Figure 16. NCP1124 Vfold vs. Junction
Temperature
125
1.65
1.015
65 kHz
1.010
1.60
100 kHz
1.000
Vfold (V)
Vfreeze (V)
1.005
100 kHz
1.55
65 kHz
1.50
0.995
1.45
0.990
1.40
0.985
−40
0
25
85
−40
125
0
25
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. NCP1126 Vfreeze vs. Junction
Temperature
Figure 18. NCP1126 Vfold vs. Junction
Temperature
1.015
1.65
65 kHz
1.60
1.010
100 kHz
Vfold (V)
100 kHz
Vfreeze (V)
85
1.005
1.000
1.55
65 kHz
1.50
1.45
0.995
1.40
−40
−25
0
25
85
100
125
−40
−25
0
25
85
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 19. NCP1129 Vfreeze vs. Junction
Temperature
Figure 20. NCP1129 Vfold vs. Junction
Temperature
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9
125
NCP1124, NCP1126, NCP1129
TYPICAL CHARACTERISTICS
120
27.85
100 kHz
27.8
VCC(OVP) (V)
100
fOSC (kHz)
80
65 kHz
60
27.75
100 kHz
27.7
40
27.65
20
27.6
65 kHz
0
−50
−25
0
25
50
75
100
27.55
−50
125
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 21. NCP1124 fOSC vs. Junction
Temperature
Figure 22. NCP1124 VCC(OVP) vs. Junction
Temperature
120
27.85
100 kHz
27.8
VCC(OVP) (V)
100
80
fOSC (kHz)
−25
TEMPERATURE (°C)
65 kHz
60
27.75
65 kHz
27.7
40
27.65
20
27.6
0
−40
0
25
85
100 kHz
27.55
−50
125
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 23. NCP1126 fOSC vs. Junction
Temperature
Figure 24. NCP1126 VCC(OVP) vs. Junction
Temperature
110
28.45
100 kHz
100
65 kHz
28.40
VCC(OVP) (V)
fOSC (kHz)
90
80
70
65 kHz
60
28.35
28.30
100 kHz
28.25
28.20
50
40
28.15
−40
−25
0
25
85
100
125
−40
−25
0
25
85
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 25. NCP1129 fOSC vs. Junction
Temperature
Figure 26. NCP1129 VCC(OVP) vs. Junction
Temperature
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NCP1124, NCP1126, NCP1129
TYPICAL CHARACTERISTICS
780
20
18
760
14
720
12
RDS(on)
VBR(DSS) (V)
16
740
700
8
6
680
4
660
640
−50
10
2
−25
0
25
50
75
100
0
−50
125
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 27. NCP1124 VBR(DSS) vs. Junction
Temperature
Figure 28. NCP 1124 RDS(on) vs. Junction
Temperature
12
800
10
8
RDS(on)
VBR(DSS) (V)
750
700
6
4
650
2
600
−50
−25
0
25
50
75
100
0
−50
125
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 29. NCP1126 VBR(DSS) vs. Junction
Temperature
Figure 30. NCP 1126 RDS(on) vs. Junction
Temperature
4.5
800
4.0
750
700
3.0
RDS(on)
VBR(DSS) (V)
3.5
650
600
2.5
2.0
1.5
1.0
550
500
−50
0.5
0
−25
0
25
50
75
100
125
−40
−25
0
25
85
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 31. NCP1129 VBR(DSS) vs. Junction
Temperature
Figure 32. NCP 1129 RDS(on) vs. Junction
Temperature
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NCP1124, NCP1126, NCP1129
TYPICAL CHARACTERISTICS
2
350
1.5
VGS = 5.5 V
VGS = 5 V
1
VGS = 4.5 V
0.5
3
6
9
12
15
18
21
24
27
100
Coss
0
30
50
100
150
200
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 33. NCP1124 − Drain Current vs.
Drain−to−Source Voltage
Figure 34. NCP1124 − Capacitance Variation
250
600
2.5
2
VGS = 5.5 V
1.5
VGS = 5 V
1
VGS = 4.5 V
0.5
VGS = 0 V
TJ = 25°C
f = 1 MHz
500
VGS = 6 − 8.5 V
C, CAPACITANCE (pF)
ID, DRAIN CURRENT (A)
150
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
3
400
300
200
100
VGS = 4 V
Coss
0
0
3
6
9
12
15
18
21
24
27
30
0
50
100
150
200
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 35. NCP1126 − Drain Current vs.
Drain−to−Source Voltage
Figure 36. NCP1126 − Capacitance Variation
250
1600
10
9
VGS = 0 V
TJ = 25°C
f = 1 MHz
1200
8
C, CAPACITANCE (pF)
ID, DRAIN CURRENT (A)
200
0
0
3.5
0
250
50
VGS = 4 V
0
VGS = 0 V
TJ = 25°C
f = 1 MHz
300
C, CAPACITANCE (pF)
ID, DRAIN CURRENT (A)
VGS = 6 − 8.5 V
VGS = 6 − 8.5 V
7
6
5
VGS = 5.5 V
4
VGS = 5 V
3
2
VGS = 4.5 V
1
VGS = 4 V
1000
800
600
400
200
Coss
0
0
0
3
6
9
12
15
18
21
24
27
30
0
50
100
150
200
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 37. NCP1129 − Drain Current vs.
Drain−to−Source Voltage
Figure 38. NCP1129 − Capacitance Variation
www.onsemi.com
12
250
NCP1124, NCP1126, NCP1129
APPLICATION INFORMATION
Introduction
Start−up Sequence
The NCP112x family integrates a high−performance
current−mode controller with a 650 V MOSFET, which
considerably simplifies the design of a compact and reliable
switch mode power supply (SMPS). This component
represents the ideal candidate where low part−count and cost
effectiveness are the key parameters. The NCP112x brings
most necessary functions needed in today’s modern power
supply designs, with several enhancements such as VCC
OVP, adjustable slope compensation, frequency jittering,
frequency foldback, skip cycle, etc.
• Current−mode operation with adjustable internal
ramp compensation: Sub−harmonic oscillations in
peak current mode control can be eliminated by the
adjustable internal ramp compensation when the duty
ratio is larger than 0.5.
• Frequency foldback capability: When the load
current drops, the controller responds by reducing the
primary peak current. When the peak current reaches
the skip peak current level, the NCP112x enter skip
operation to reduce the power consumption.
• Internal soft−start: a soft−start precludes the main
power switch from being stressed upon start−up. In this
switcher, the soft−start is internally fixed to 4 ms.
Soft−start is activated when a new startup sequence
occurs or during an auto−recovery hiccup.
• Latched OVP on VCC: When the VCC exceeds 28 V
typical, the drive signal is disabled and the part latches
off. When the user cycles the VCC down, the circuit is
reset and the part enters a new start up sequence.
• Short−circuit protection: short−circuit and especially
over−load protections are difficult to implement when a
strong leakage inductance between the auxiliary and the
power windings affects the transformer (the aux
winding level does not properly collapse in presence of
an output short). Every time the internal 0.8 V
maximum peak current limit is activated, an error flag
is asserted and an internal timer starts. When the fault is
validated, the switcher will either be latched or enter
the auto−recovery mode. As soon as the fault
disappears, the SMPS resumes operation.
• EMI jittering: an internal low−frequency 240 Hz
modulation signal varies the pace at which the
oscillator frequency is modulated. This helps spread out
the energy in a conducted noise analysis. To improve
the EMI signature at low power levels, the jittering will
not be disabled in frequency foldback mode (light load
conditions).
The NCP112x need an external startup circuit to provide
the initial energy to the switcher. As is shown in Figure 39,
the startup circuit consists of Rstart and VCC capacitor CCC,
connected to the main input, i.e. half−wave connection. The
auxiliary winding will take over the RC circuit after the
output voltage is built up.
D3
D1
VCC
Main
Input
Cbulk
D2
D4
Rstart
D
Auxiliary
winding
CCC
Figure 39. Startup Circuit for NCP112x
(half−wave connection)
The startup process can be well explained by Figure 40. At
power on, when the VCC capacitor is fully discharged, the
switcher current consumption is zero and does not deliver
any driving pulses. The VCC capacitor CCC is going to be
charged by the main input via Rstart. As VCC increases, the
switcher consumed current remains below a guaranteed
limit until the voltage on the capacitor reaches VCC(on), at
which point the switcher starts to deliver pulses to the power
MOSFET. The switcher current consumption suddenly
increases, and the capacitor depletes since it is the only
energy reservoir. Its voltage falls until the auxiliary winding
takes over and supply the VCC pin.
t1: 5−20 ms
VCC
VCC(on)
margin
VCC(off)
Drive
time
Figure 40. Startup Process for NCP112x
The start−up current of the switcher is extremely low,
below 15 mA. The start−up resistor can be connected to the
bulk capacitor or directly the mains input voltage for further
power dissipation reduction. The switcher begins switching
when VCC reaches VCC(on), typically 17 V for NCP1126/9.
From Figure 41, it can be seen that the startup resistor Rstart
and VCC capacitor are about to be determined.
www.onsemi.com
13
NCP1124, NCP1126, NCP1129
VCC Capacitor
offered in Figure 41 elegantly solves this potential issue by
adding an extra capacitor CCC,aux on the auxiliary winding.
However, this component is separated from the VCC pin by
a simple diode. You therefore have the ability to grow this
capacitor as you need to ensure the self−supply of the
switcher without affecting the start−up time and standby
power.
The supply capacitor, CCC, provides power to the switcher
during power up. The capacitor must be large enough such
that a VCC voltage greater than VCC(off) is maintained while
the auxiliary supply voltage is building up. Otherwise, VCC
will collapse and the switcher will turn off. Assuming this
time t1 is equal to 10 ms, Equation 1 is used to calculate the
required VCC capacitor.
C CC w
I CCt 1
V CC(on) * V CC(off)
(eq. 1)
D1
In order to determine the startup resistor, the VCC
capacitor charging current is calculated first to ensure that
the charging time for the VCC capacitor from 0 V to its
operating voltage meets the startup time requirement.
Equation 2 gives the first constraints for the Rstart selection.
V CC(on)C CC
t startup
V 2 ac,peak
4R start
D4
CCC
CCC,aux
Auxiliary
winding
Frequency Foldback
The reduction of no−load standby power associated with
the need for improving the efficiency, requires a change in
the traditional type of fixed−frequency operation. NCP112x
implement a switching frequency foldback function when
the feedback voltage is below VFB(fold). At this point, the
oscillator turns into a Voltage−Controlled Oscillator and
reduces its switching frequency. The peak current setpoint
follows the feedback pin until its level reaches VFB(freeze).
Below this value, the peak current freezes to VFB(freeze) / 4.
The operating frequency is down to ftrans when the feedback
voltage reaches VFB(fold,end). Below this point, if the output
power continues to decrease, the part enters skip mode for
the best noise−free performance in no−load conditions.
Figure 6 depicts the adopted scheme for the part.
(eq. 3)
(eq. 4)
Note that this calculation is purely theoretical, considering
a constant charging current. In reality, the take over time can
be shorter (or longer!) and it can lead to a reduction of the
VCC capacitor. This brings a decrease in the charging current
and an increase of the start−up resistor, for the benefit of
standby power. The dissipated power at high line amounts
to:
P diss +
D5
Figure 41. Startup Circuit for NCP112x (half−wave
connection), Considering Light Load Condition
(eq. 2)
which gives the minimum value for the Rstartup,
V ac,rmsǸ2
* V CC(on)
p
R start−up v
I c,min
D4
Cbulk
D2
For NCP1126/9, during startup process, from 0 to t1, the
current that flow inside the switcher is ICC1, therefore the
total charging current from the main input is going to be IC
= Icharge + ICC1. Consider the half−wave connection start−up
network to the mains as is shown in Figure 41, the average
current flowing into this start−up resistor will be the smallest
when VCC reaches the VCC(on) of the switcher:
Vac,rmsǸ2
* V CC(on)
p
I c,min +
R start−up
Rstart
Vcc
Main
Input
Startup Resistor Rstart
I charge w
D3
Over−voltage Protection
The latched−state of the NCP112x is maintained via an
internal thyristor (SCR). When the voltage on pin 1 exceeds
the latch voltage for four consecutive clock cycles, the SCR
is fired and immediately stops the output pulses. The same
SCR is fired when an OVP is sensed on the VCC pin. When
this happens, all pulses are stopped and VCC is discharged
to a fix level of 7 V typically: the circuit is latched and the
converter no longer delivers pulses. To maintain the
latched−state, a permanent current must be injected in the
part. If too low of a current, the part de−latches and the
converter resumes operation. This current is characterized to
32 mA as a minimum but we recommend including a design
margin and select a value around 60 mA. The test is to latch
the part and reduce the input voltage until it de−latches. If
you de−latch at Vin = 70 Vrms for a minimum voltage of
85 Vrms, you are fine.
(eq. 5)
The above derivation is based on the case when the power
supply is not at light load. VCC capacitor selection should
ensure that does not disappear in no−load conditions. In light
load condition, the skip−cycle can be so deep that refreshing
pulses are likely to be widely spaced, inducing a large ripple
on the VCC capacitor. If this ripple is too large, chances exist
to hit the VCC(off) and reset the switcher into a new start−up
sequence. A solution is to grow this capacitor but it will
obviously be detrimental to the start−up time. The option
www.onsemi.com
14
NCP1124, NCP1126, NCP1129
VCS
max
VILIM
VCS(fold)
min
VCS(freeze)
3.2 V
VFB(fold)
VFB(freeze)
Frequency
FSW
Figure 43. The Full−wave Connection Ensures Latch
Current Continuity as Well as a X2−Discharge Path
max
fOSC
ftrans
VFB
In this case, the current is no longer made of 5 ms “holes”
and the part can be maintained at a low input voltage.
Experiments show that these 2−MW resistor help to maintain
the latch down to less than 50 V rms, giving an excellent
design margin. Standby power with this approach was also
improved compared to Figure 39 solution. Please note that
these resistors also ensure the discharge of the X2−capacitor
up to a 0.47 mF type.
The de−latch of the SCR occurs when a) the injected
current in the VCC pin falls below the minimum stated in the
data−sheet (32 mA at room temp) or when the part senses a
brown−out recovery.
min
VFB(fold,end) VFB(fold) 3.2 V
VFB
Figure 42. Frequency Foldback Architecture
If it precociously recovers, you will have to increase the
start−up current, unfortunately to the detriment of standby
power.
The most sensitive configuration is actually that of the
half−wave connection proposed in Figure 39. As the current
disappears 5 ms for a 10 ms period (50 Hz input source), the
latch can potentially open at low line. If you really reduce the
start−up current for a low standby power design, you must
ensure enough current in the SCR in case of a faulty event.
An alternate connection to the above is shown in Figure 43:
Auto−Recovery Short−Circuit Protection
In case of output short−circuit or severe overload
situation, an internal error flag is raised and starts a
countdown timer. If the flag is asserted longer than tOVLD,
the driving pulses are stopped and VCC falls down as the
auxiliary pulses are missing. When it hits VCC(off), the
switcher consumption is down to a few mA and the VCC
slowly builds up again by the startup network Rstart, CCC.
When VCC reaches VCC(on), the switcher purposely ignores
the re−start and waits for another VCC cycle: this is the
so−called double hiccup. Illustration of such principle
appears in Figure 13. Please note that soft−start is activated
upon re−start attempt.
VCC(on)
VCC
VCC(off)
drive
time
Figure 44. Auto−Recovery Double Hiccup Sequence
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15
NCP1124, NCP1126, NCP1129
Adjustable Ramp Compensation
In the NCP112x switchers, the oscillator ramp exhibits a
Vramp 2.5 V swing reached at its maximum duty−ratio. If the
clock operates at a 65−kHz frequency, then the slope of the
ramp is equal to:
The NCP112x also include an internal ramp
compensation signal. This is the buffered oscillator clock
delivered during the on time only. Its amplitude Vramp is
around 2.5 V at maximum duty−cycle. Ramp compensation
is a well−known method used to eliminate the sub−harmonic
oscillations in CCM peak current mode converters. These
oscillations take place at half the switching frequency and
occur only during Continuous Conduction Mode (CCM)
with a duty−ratio greater than 50%. To lower the current
loop gain, one usually mixes between 50% and 100% of the
inductor downslope with the current−sense signal.
Figure 45 depicts how internally the ramp is generated. Note
that the ramp signal will be disconnected from the CS pin,
during the off−time.
S ramp +
V ramp
D maxT sw
(eq. 6)
The off−time primary current slope Sp is thus given by
Equation 7:
Sp +
ǒVout ) VfǓ NNp
s
Lp
(eq. 7)
Given a sense resistor Rsense the above current ramp turns
into a voltage ramp of the following amplitude:
S sense + S pR sense
(eq. 8)
The slope of compensation ramp is chosen to be the same
as the downslope of the sensing ramp for better transient
response. The internal resistor connected to the
compensation ramp is 20 kW. The series compensation
resistor value is therefore:
R comp + R ramp
S sense
S ramp
(eq. 9)
A resistor of the above value will then be inserted from the
sense resistor to the current sense pin. A100 pF capacitor is
recommended to be added to the current sense pin to the
switcher ground for improved noise immunity with the
current sensing components located very close to the
switcher.
Figure 45. Internal Adjustable Ramp
Compensation Architecture
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16
NCP1124, NCP1126, NCP1129
VCC
FB
CS
Source
1
8
2
3
6
4
5
GND
Drain
Drain
(Top View)
Figure 46. Pin Connections
ORDERING INFORMATION
Device
Package
Shipping
NCP1124AP65G
PDIP−7
(Pb−Free)
50 Units / Rail
NCP1124BP65G
PDIP−7
(Pb−Free)
50 Units / Rail
NCP1124AP100G
PDIP−7
(Pb−Free)
50 Units / Rail
NCP1124BP100G
PDIP−7
(Pb−Free)
50 Units / Rail
NCP1126AP65G
PDIP−7
(Pb−Free)
50 Units / Rail
NCP1126BP65G
PDIP−7
(Pb−Free)
50 Units / Rail
NCP1126AP100G
PDIP−7
(Pb−Free)
50 Units / Rail
NCP1126BP100G
PDIP−7
(Pb−Free)
50 Units / Rail
NCP1129AP65G
PDIP−7
(Pb−Free)
50 Units / Rail
NCP1129BP65G
PDIP−7
(Pb−Free)
50 Units / Rail
NCP1129AP100G
PDIP−7
(Pb−Free)
50 Units / Rail
NCP1129BP100G
PDIP−7
(Pb−Free)
50 Units / Rail
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17
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−7 (PDIP−8 LESS PIN 7)
CASE 626B
ISSUE D
DATE 22 APR 2015
SCALE 1:1
D
A
E
H
8
5
E1
1
4
NOTE 8
b2
c
B
END VIEW
TOP VIEW
WITH LEADS CONSTRAINED
NOTE 5
A2
A
e/2
NOTE 3
L
SEATING
PLANE
A1
C
D1
M
e
8X
SIDE VIEW
b
0.010
eB
END VIEW
M
C A
M
B
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.355 0.400
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
9.02
10.16
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
NOTE 6
GENERIC
MARKING DIAGRAM*
STYLE 1:
PIN 1. AC IN
2. DC + IN
3. DC − IN
4. AC IN
5. GROUND
6. OUTPUT
7. NOT USED
8. VCC
XXXXXXXXX
AWL
YYWWG
XXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
98AON12198D
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PDIP−7 (PDIP−8 LESS PIN 7)
PAGE 1 OF 1
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