NCP115ASN330T2G

NCP115 LDO Regulator - High PSRR 300 mA The NCP115 is 300 mA LDO that provides the engineer with a very stable, accurate voltage with low noise suitable for space constrained, noise sensitive applications. In order to optimize performance for battery operated portable applications, the NCP115 employs the dynamic quiescent current adjustment for very low IQ consumption at no−load. www.onsemi.com MARKING DIAGRAMS Features • Operating Input Voltage Range: 1.7 V to 5.5 V • Available in Fixed Voltage Options: 0.8 V to 3.6 V • • • • • • • • • • 1 Contact Factory for Other Voltage Options Very Low Quiescent Current of Typ. 50 mA Soft Start Feature with Two VOUT Slew Rate Speed Standby Current Consumption: Typ. 0.1 mA Low Dropout: 250 mV Typical at 300 mA @ 2.8 V ±1% Accuracy at Room Temperature High Power Supply Ripple Rejection: 70 dB at 1 kHz Thermal Shutdown and Current Limit Protections Available in XDFN4 and TSOP−5 Packages Stable with a 1 mF Ceramic Output Capacitor These are Pb−Free Devices XX M 1 XX = Specific Device Code M = Date Code 5 TSOP−5 CASE 483 5 1 XX M G G 1 XX = Device Code M = Date Code* G = Pb−Free Package (Note: Microdot may be in either location) *Date Code orientation and/or position may vary depending upon manufacturing location. Typical Applicaitons • • • • XDFN4 CASE 711AJ PIN CONNECTIONS PDAs, Mobile phones, GPS, Smartphones Wireless Handsets, Wireless LAN, Bluetooth®, Zigbee® Portable Medical Equipment Other Battery Powered Applications VIN EN IN 3 4 2 1 VOUT IN CIN EN ON OFF OUT NCP115 GND COUT 1 mF Ceramic GND OUT (Bottom View) Figure 1. Typical Application Schematic IN 1 GND 2 EN 3 5 OUT 4 N/C (Top View) ORDERING INFORMATION See detailed ordering, marking and shipping information on page 15 of this data sheet. © Semiconductor Components Industries, LLC, 2017 September, 2019 − Rev. 4 1 Publication Order Number: NCP115/D NCP115 IN ENABLE LOGIC EN THERMAL SHUTDOWN BANDGAP REFERENCE MOSFET DRIVER WITH CURRENT LIMIT OUT AUTO LOW POWER MODE ACTIVE DISCHARGE* EN GND *Active output discharge function is present only in NCP115A and NCP115C devices. yyy denotes the particular VOUT option. Figure 2. Simplified Schematic Block Diagram PIN FUNCTION DESCRIPTION Pin No. (XDFN4) Pin No. (TSOP5) Pin Name Description 1 5 OUT Regulated output voltage pin. A small ceramic capacitor with minimum value of 1 mF is needed from this pin to ground to assure stability. 2 2 GND Power supply ground. 3 3 EN Driving EN over 0.9 V turns on the regulator. Driving EN below 0.4 V puts the regulator into shutdown mode. 4 1 IN Input pin. A small capacitor is needed from this pin to ground to assure stability. − 4 N/C − − EPAD Not connected. This pin can be tied to ground to improve thermal dissipation. Exposed pad should be connected directly to the GND pin. Soldered to a large ground copper plane allows for effective heat removal. ABSOLUTE MAXIMUM RATINGS Rating Symbol Value Unit VIN −0.3 V to 6 V V Output Voltage VOUT −0.3 V to VIN + 0.3 V or 6 V V Enable Input VEN −0.3 V to 6 V V Input Voltage (Note 1) Output Short Circuit Duration tSC ∞ s TJ(MAX) 150 °C TSTG −55 to 150 °C ESD Capability, Human Body Model (Note 2) ESDHBM 2000 V ESD Capability, Machine Model (Note 2) ESDMM 200 V Maximum Junction Temperature Storage Temperature Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 2. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per EIA/JESD22−A114, ESD Machine Model tested per EIA/JESD22−A115, Latchup Current Maximum Rating tested per JEDEC standard: JESD78. THERMAL CHARACTERISTICS (Note 3) Rating Symbol Value Unit Thermal Characteristics, XDFN4 1x1 mm Thermal Resistance, Junction−to−Air RqJA 208 °C/W Thermal Characteristics, TSOP−5 Thermal Resistance, Junction−to−Air RqJA 162 °C/W 3. Single component mounted on 1 oz, FR 4 PCB with 645 mm2 Cu area. www.onsemi.com 2 NCP115 ELECTRICAL CHARACTERISTICS −40°C ≤ TJ ≤ 85°C; VIN = VOUT(NOM) + 1 V for VOUT options greater than 1.5 V. Otherwise VIN = 2.5 V, whichever is greater; IOUT = 1 mA, CIN = COUT = 1 mF, unless otherwise noted. VEN = 0.9 V. Typical values are at TJ = +25°C. Min./Max. are for TJ = −40°C and TJ = +85°C respectively (Note 4). Parameter Test Conditions Operating Input Voltage Output Voltage Accuracy −40°C ≤ TJ ≤ 85°C VOUT ≤ 2.0 V Symbol Min VIN VOUT VOUT > 2.0 V Line Regulation Load Regulation − XDFN4 package Max Unit 1.7 5.5 V −40 +40 mV +2 % VOUT + 0.5 V ≤ VIN ≤ 5.5 V (VIN ≥ 1.7 V) RegLINE −2 0.01 0.1 %/V IOUT = 1 mA to 300 mA RegLOAD 12 30 mV 28 45 425 560 250 320 215 260 445 580 VOUT = 2.8 V 270 340 VOUT = 3.3 V 235 280 Load Regulation − TSOP−5 package Dropout Voltage − XDFN4 package (Note 5) IOUT = 300 mA Dropout Voltage − TSOP−5 package (Note 5) IOUT = 300 mA VOUT = 1.8 V VDO VOUT = 2.8 V VOUT = 3.3 V Output Current Limit Typ VOUT = 1.8 V VDO ICL Quiescent Current IOUT = 0 mA IQ 50 95 mA Shutdown Current VEN ≤ 0.4 V, VIN = 5.5 V IDIS 0.01 1 mA EN Pin Threshold Voltage High Threshold Low Threshold VEN Voltage increasing VEN Voltage decreasing VEN_HI VEN_LO VOUT = 3.3 V, IOUT = 10 mA Normal (version A and B) VOUT_SR Slow (version C and D) EN Pin Input Current Power Supply Rejection Ratio Output Noise Voltage Thermal Shutdown Temperature Thermal Shutdown Hysteresis Active Output Discharge Resistance VEN = 5.5 V 600 mV VOUT = 90% VOUT(nom) VOUT Slew Rate (Note 6) 300 mV mA V 0.9 0.4 190 mV/ms 20 IEN 0.3 PSRR 70 dB f = 10 Hz to 100 kHz VN 70 mVrms Temperature increasing from TJ = +25°C TSD 160 °C Temperature falling from TSD TSDH 20 °C VEN < 0.4 V, Version A and C only RDIS 100 W VIN = 3.8 V, VOUT = 3.5 V IOUT = 10 mA f = 1 kHz 1.0 mA Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Performance guaranteed over the indicated operating temperature range by design and/or characterization. Production tested at TJ = TA = 25°C. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible. 5. Characterized when VOUT falls 100 mV below the regulated voltage at VIN = VOUT(NOM) + 1 V. 6. Please refer OPN to determine slew rate. NCP115A, NCP115B − Normal speed. NCP115C, NCP115D − slower speed www.onsemi.com 3 NCP115 TYPICAL CHARACTERISTICS 1.815 VOUT, OUTPUT VOLTAGE (V) 1.820 VOUT, OUTPUT VOLTAGE (V) 1.220 1.215 1.210 1.205 IOUT = 10 mA 1.200 1.195 IOUT = 300 mA 1.190 1.180 1.175 VIN = 2.5 V VOUT = 1.2 V CIN = 1 mF COUT = 1 mF 1.170 −40 −30 −20 −10 0 VOUT, OUTPUT VOLTAGE (V) 2.820 2.815 2.810 2.805 10 20 30 40 50 60 70 80 90 IOUT = 10 mA IOUT = 300 mA 2.780 2.775 2.770 −40 −30 −20 −10 0 1.775 1.770 −40 −30 −20 −10 0 10 20 30 40 50 60 70 80 90 3.305 3.300 3.295 10 20 30 40 50 60 70 80 90 VIN = 4.3 V VOUT = 3.3 V CIN = 1 mF COUT = 1 mF IOUT = 10 mA 3.290 3.285 3.280 IOUT = 300 mA 3.275 3.270 3.265 3.260 −40 −30 −20 −10 0 10 20 30 40 50 60 70 80 90 TJ, JUNCTION TEMPERATURE (°C) Figure 5. Output Voltage vs. Temperature − VOUT = 2.8 V − XDFN4 Figure 6. Output Voltage vs. Temperature − VOUT = 3.3 V − XDFN4 REGLOAD, LOAD REGULATION (mV) REGLINE, LINE REGULATION (%/V) 1.780 TJ, JUNCTION TEMPERATURE (°C)) 0.005 0 IOUT = 300 mA 1.785 3.310 VIN = 3.8 V VOUT = 2.8 V CIN = 1 mF COUT = 1 mF 2.785 0.001 1.790 Figure 4. Output Voltage vs. Temperature − VOUT = 1.8 V − XDFN4 2.795 0.002 1.795 Figure 3. Output Voltage vs. Temperature − VOUT = 1.2 V − XDFN4 2.790 0.003 IOUT = 10 mA 1.800 TJ, JUNCTION TEMPERATURE (°C) 2.800 0.004 1.805 TJ, JUNCTION TEMPERATURE (°C) VOUT, OUTPUT VOLTAGE (V) 1.185 1.810 VIN = 2.8 V VOUT = 1.8 V CIN = 1 mF COUT = 1 mF VOUT = 1.2 V VOUT = 1.8 V VOUT = 2.8 V VOUT = 3.3 V −0.001 −0.002 −0.003 −0.004 −0.005 −40 −30 −20 −10 0 VIN = VOUT_NOM + 0.5 to 5.5 V VOUT = 1.8 V CIN = 1 mF COUT = 1 mF 10 20 30 40 50 60 70 80 90 20 18 VOUT = 2.8 V VOUT = 3.3 V 16 14 12 10 8 VOUT = 1.2 V VOUT = 1.8 V 6 V =V IN OUT_NOM + 1 V 4 IOUT = 1 mA to 300 mA CIN = 1 mF 2 COUT = 1 mF 0 −40 −30 −20 −10 0 10 20 30 40 50 60 70 80 90 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 7. Line Regulation vs. Temperature Figure 8. Load Regulation vs. Temperature − XDFN4 www.onsemi.com 4 NCP115 TYPICAL CHARACTERISTICS 70 VIN = VOUT_NOM + 1 V CIN = 1 mF COUT = 1 mF TJ = 25°C 400 TJ = −40°C 300 200 100 0 0.001 500 VDO, DROPOUT VOLTAGE (mV) IQ, QUIESCENT CURRENT (mA) 500 TJ = 85°C 0.01 0.1 1 10 400 350 1000 35 28 VIN = 2.8 V VOUT = 1.8 V IOUT = 0 mA CIN = 1 mF COUT = 1 mF 21 14 7 0 0 350 TJ = 85°C 200 150 TJ = 25°C 100 50 100 150 200 250 300 1 2 3 4 5 6 VOUT = 2.8 V CIN = 1 mF COUT = 1 mF meas for VOUT_NOM − 100 mV 315 280 245 TJ = 85°C 210 175 TJ = −40°C 140 105 TJ = 25°C 70 35 0 0 50 100 150 200 250 300 IOUT, OUTPUT CURRENT (mA) IOUT, OUTPUT CURRENT (mA) Figure 11. Dropout Voltage vs. Load Current − VOUT = 1.8 V Figure 12. Dropout Voltage vs. Load Current − VOUT = 2.8 V 720 300 VOUT = 3.3 V CIN = 1 mF COUT = 1 mF meas for VOUT_NOM − 100 mV 270 240 210 700 TJ = 85°C ICL, CURRENT LIMIT (mA) VDROP, DROPOUT VOLTAGE (mV) TJ = 85°C 42 Figure 10. Quiescent Current vs. Input Voltage VOUT = 1.8 V 250 180 150 TJ = −40°C 120 90 TJ = 25°C 60 30 0 49 Figure 9. Ground Current vs. Load Current TJ = −40°C 0 TJ = −40°C 56 VIN, INPUT VOLTAGE (V) 300 50 0 TJ = 25°C 63 IOUT, OUTPUT CURRENT (mA) VOUT = 1.8 V CIN = 1 mF COUT = 1 mF meas for VOUT_NOM − 100 mV 450 100 VDROP, DROPOUT VOLTAGE (mV) IGND, GROUND CURRENT (mA) 600 0 50 100 150 200 250 680 660 640 620 600 580 560 540 520 −40 −30 −20 −10 0 300 VIN = 4.3 V VOUT = 90% VOUT(nom) CIN = 1 mF COUT = 1 mF 10 20 30 40 50 60 70 80 90 IOUT, OUTPUT CURRENT (mA) TJ, JUNCTION TEMPERATURE (°C) Figure 13. Dropout Voltage vs. Load Current − VOUT = 3.3 V Figure 14. Current Limit vs. Temperature www.onsemi.com 5 NCP115 680 660 640 620 600 580 560 540 520 500 −40 −30 −20 −10 0 VIN = 4.3 V VOUT = 0 V (short) CIN = 1 mF COUT = 1 mF 10 20 30 40 50 60 70 80 90 1.0 0.9 0.8 OFF → ON 0.7 0.6 ON → OFF 0.5 0.4 VIN = 3.8 V VOUT = 2.8 V CIN = 1 mF COUT = 1 mF 0.3 0.2 0.1 0 −40 −30 −20 −10 0 10 20 30 40 50 60 70 80 90 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 15. Short Circuit Current vs. Temperature Figure 16. Enable Thresholds Voltage 250 30 225 27 200 175 150 125 100 VIN = 4.3 V VOUT = 3.3 V CIN = 1 mF COUT = 1 mF 75 50 25 0 −40 −30 −20 −10 0 VIN = 4.3 V VOUT = 0 V CIN = 1 mF COUT = 1 mF VEN = 1 V 24 21 18 15 12 9 6 3 0 −40 −30 −20 −10 0 10 20 30 40 50 60 70 80 90 10 20 30 40 50 60 70 80 90 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 17. Current to Enable Pin vs. Temperature Figure 18. Disable Current vs. Temperature 100 100 90 80 Unstable Operation 70 10 60 ESR (W) RDIS, DISCHARGE RESISTIVITY (W) VEN, ENABLE VOLTAGE THRESHOLD (V) 700 IDIS, DISABLE CURRENT (nA) IEN, ENABLE PIN CURRENT (nA) ISC, SHORT CIRCUIT CURRENT (mA) TYPICAL CHARACTERISTICS 50 40 30 20 10 0 −40 −30 −20 −10 0 1 VIN = 4.3 V VOUT = 3.3 V CIN = 1 mF COUT = 1 mF 0.1 10 20 30 40 50 60 70 80 90 Stable Operation 0 50 100 150 200 250 300 TJ, JUNCTION TEMPERATURE (°C) IOUT, OUTPUT CURRENT (mA) Figure 19. Discharge Resistance vs. Temperature Figure 20. Maximum COUT ESR Value vs. Load Current www.onsemi.com 6 NCP115 NOISE SPECTRAL DENSITY (mV/√Hz) TYPICAL CHARACTERISTICS 10 IOUT = 1 mA IOUT = 10 mA IOUT = 300 mA 1 IOUT 0.1 VIN = 2.5 V VOUT = 1.2 V CIN = 1 mF (MLCC) COUT = 1 mF (MLCC) 0.01 0.001 10 100 1K 10K 100K 1M RMS Output Noise (mVRMS) 10 Hz − 100 kHz 100 Hz − 100 kHz 1 mA 65.6 61.9 10 mA 63.1 59.5 300 mA 62.3 60.3 10M FREQUENCY (Hz) NOISE SPECTRAL DENSITY (mV/√Hz) Figure 21. Output Voltage Noise Spectral Density – VOUT = 1.2 V 10 IOUT = 1 mA IOUT = 10 mA IOUT = 300 mA 1 IOUT 1 mA 0.1 VIN = 3.8 V VOUT = 2.8 V CIN = 1 mF (MLCC) COUT = 1 mF (MLCC) 0.01 0.001 10 100 1K 10K 100K 1M RMS Output Noise (mVRMS) 10 Hz − 100 kHz 100 Hz − 100 kHz 93.4 87.9 10 mA 92.1 86.6 300 mA 119.3 115.6 10M FREQUENCY (Hz) NOISE SPECTRAL DENSITY (mV/√Hz) Figure 22. Output Voltage Noise Spectral Density – VOUT = 2.8 V 10 IOUT = 1 mA IOUT = 10 mA IOUT = 300 mA 1 IOUT 0.1 VIN = 4.3 V VOUT = 3.3 V CIN = 1 mF (MLCC) COUT = 1 mF (MLCC) 0.01 0.001 10 100 1K 10K 100K 1M RMS Output Noise (mVRMS) 10 Hz − 100 kHz 100 Hz − 100 kHz 1 mA 104.0 98.0 10 mA 102.9 96.7 300 mA 131.4 127.0 10M FREQUENCY (Hz) Figure 23. Output Voltage Noise Spectral Density – VOUT = 3.3 V www.onsemi.com 7 NCP115 TYPICAL CHARACTERISTICS 70 RR, RIPPLE REJECTION (dB) 80 60 50 40 30 20 10 0 VIN = 2.5 V + 100 mVpp VOUT = 1.2 V CIN = none COUT = 1 mF (MLCC) 100 1K 10K 100K 1M 10M 40 30 VIN = 2.8 V + 100 mVpp VOUT = 1.8 V CIN = none COUT = 1 mF (MLCC) 20 10 0 100 1K 10K 100 IOUT = 1 mA IOUT = 10 mA IOUT = 150 mA IOUT = 300 mA 60 50 40 VIN = 3.8 V + 100 mVpp VOUT = 2.8 V CIN = none COUT = 1 mF (MLCC) 100 60 50 100K 1M Figure 25. Power Supply Rejection Ratio, VOUT = 1.8 V 70 20 70 Figure 24. Power Supply Rejection Ratio, VOUT = 1.2 V 80 10 0 80 FREQUENCY (Hz) 90 30 IOUT = 1 mA IOUT = 10 mA IOUT = 150 mA IOUT = 300 mA 90 FREQUENCY (Hz) 100 RR, RIPPLE REJECTION (dB) 100 IOUT = 1 mA IOUT = 10 mA IOUT = 150 mA IOUT = 300 mA 90 RR, RIPPLE REJECTION (dB) RR, RIPPLE REJECTION (dB) 100 1K 10K 100K 1M IOUT = 1 mA IOUT = 10 mA IOUT = 150 mA IOUT = 300 mA 90 80 70 60 50 40 30 VIN = 4.3 V + 100 mVpp VOUT = 3.3 V CIN = none COUT = 1 mF (MLCC) 20 10 0 10M 100 1K 10K 100K 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 26. Power Supply Rejection Ratio, VOUT = 2.8 V Figure 27. Power Supply Rejection Ratio, VOUT = 3.3 V www.onsemi.com 8 10M 10M NCP115 100 mA/div 500 mV/div VEN IINPUT IINPUT 500 mV/div VIN = 2.8 V VOUT = 1.8 V COUT = 1 mF (MLCC) VOUT VEN VIN = 2.8 V VOUT = 1.8 V COUT = 1 mF (MLCC) VOUT 200 ms/div Figure 28. Enable Turn−on Response − IOUT = 0 mA, Slow Option − C Figure 29. Enable Turn−on Response − IOUT = 300 mA, Slow Option − C 500 mV/div 200 ms/div VEN C option VIN = 2.8 V VOUT = 1.8 V COUT = 1 mF (MLCC) VOUT IINPUT 500 mV/div A option 50 mA/div IINPUT VEN A option C option VIN = 2.8 V VOUT = 1.8 V COUT = 1 mF (MLCC) VOUT 50 ms/div 100 ms/div Figure 30. VOUT Slew−Rate Comparison A and C option − IOUT = 10 mA Figure 31. VOUT Slew−Rate Comparison A and C option − IOUT = 300 mA tRISE,FALL = 1 ms VIN VOUT 500 mV/div 3.0 V 2.0 V VOUT = 1.2 V CIN = 1 mF (MLCC) COUT = 1 mF (MLCC) 20 mV/div 20 mV/div 500 mV/div 500 mV/div 50 mA/div 500 mV/div 500 mV/div 100 mA/div 500 mV/div TYPICAL CHARACTERISTICS 3.0 V tRISE,FALL = 1 ms VIN 2.0 V VOUT = 1.2 V CIN = 1 mF (MLCC) COUT = 1 mF (MLCC) VOUT 10 ms/div 10 ms/div Figure 32. Line Transient Response − IOUT = 10 mA Figure 33. Line Transient Response − IOUT = 300 mA www.onsemi.com 9 NCP115 tRISE,FALL = 1 ms 3.8 V VOUT = 2.8 V CIN = 1 mF (MLCC) COUT = 1 mF (MLCC) VOUT 20 mV/div VIN 500 mV/div 4.8 V 4.8 V tRISE,FALL = 1 ms VIN 3.8 V VOUT = 2.8 V CIN = 1 mF (MLCC) COUT = 1 mF (MLCC) VOUT 10 ms/div 10 ms/div Figure 34. Line Transient Response − IOUT = 10 mA Figure 35. Line Transient Response − IOUT = 300 mA tRISE = 1 ms IOUT 100 mA/div VIN = 2.5 V VOUT = 1.2 V CIN = 1 mF (MLCC) IOUT = 1 mA to 300 mA VIN = 2.5 V VOUT = 1.2 V CIN = 1 mF (MLCC) IOUT = 1 mA to 300 mA IOUT tFALL = 1 ms COUT = 1 mF 20 mV/div COUT = 1 mF VOUT COUT = 4.7 mF VOUT COUT = 4.7 mF 10 ms/div Figure 36. Load Transient Response − VOUT = 1.2 V Figure 37. Load Transient Response − VOUT = 1.2 V 100 mA/div 5 ms/div tRISE = 1 ms VIN = 3.8 V, VOUT = 2.8 V CIN = 1 mF (MLCC) COUT = 1 mA to 300 mA IOUT IOUT VIN = 3.8 V, VOUT = 2.8 V CIN = 1 mF (MLCC) IOUT = 1 mA to 300 mA tFALL = 1 ms COUT = 1 mF COUT = 1 mF 20 mV/div 20 mV/div 100 mA/div 20 mV/div 100 mA/div 20 mV/div 500 mV/div TYPICAL CHARACTERISTICS VOUT COUT = 4.7 mF VOUT COUT = 4.7 mF 5 ms/div 10 ms/div Figure 38. Load Transient Response − VOUT = 2.8 V Figure 39. Load Transient Response − VOUT = 2.8 V www.onsemi.com 10 NCP115 100 mA/div tRISE = 1 ms VIN = 4.3 V, VOUT = 3.3 V CIN = 1 mF (MLCC) IOUT = 1 mA to 300 mA IOUT VIN = 4.3 V, VOUT = 3.3 V CIN = 1 mF (MLCC) IOUT = 1 mA to 300 mA IOUT tFALL = 1 ms COUT = 1 mF 20 mV/div COUT = 1 mF VOUT COUT = 4.7 mF VOUT COUT = 4.7 mF 5 ms/div 10 ms/div Figure 40. Load Transient Response − VOUT = 3.3 V Figure 41. Load Transient Response − VOUT = 3.3 V VIN VIN VOUT VOUT VIN = 3.8 V VOUT = 2.8 V CIN = 1 mF (MLCC) COUT = 1 mF (MLCC) 500 mV/div VIN = 3.8 V VOUT = 3.3 V CIN = 1 mF (MLCC) COUT = 1 mF (MLCC) 10 ms/div 10 ms/div Figure 42. Turn−on/off − Slow Rising VIN − IOUT = 10 mA Figure 43. Turn−on/off − Slow Rising VIN − IOUT = 300 mA 100 mV/div IOUT VOUT 500 mV/div 500 mV/div 20 mV/div 100 mA/div TYPICAL CHARACTERISTICS TSD On TSD Off VIN = 5.5 V, VOUT = 1.8 V CIN = 1 mF (MLCC), COUT = 1 mF (MLCC) 5 ms/div Figure 44. Overheating Protection − TSD www.onsemi.com 11 NCP115 APPLICATIONS INFORMATION General The NCP115 is a high performance 300 mA Low Dropout Linear Regulator. This device delivers very high PSRR (over 70 dB at 1 kHz) and excellent dynamic performance as load/line transients. In connection with very low quiescent current this device is very suitable for various battery powered applications such as tablets, cellular phones, wireless and many others. The device is fully protected in case of output overload, output short circuit condition and overheating, assuring a very robust design. disable state the device consumes as low as typ. 10 nA from the VIN. If the EN pin voltage >0.9 V the device is guaranteed to be enabled. The NCP115 regulates the output voltage and the active discharge transistor is turned−off. The EN pin has internal pull−down current source with typ. value of 300 nA which assures that the device is turned−off when the EN pin is not connected. In the case where the EN function isn’t required the EN should be tied directly to IN. Input Capacitor Selection (CIN) Output Current Limit It is recommended to connect at least a 1 mF Ceramic X5R or X7R capacitor as close as possible to the IN pin of the device. This capacitor will provide a low impedance path for unwanted AC signals or noise modulated onto constant input voltage. There is no requirement for the min. /max. ESR of the input capacitor but it is recommended to use ceramic capacitors for their low ESR and ESL. A good input capacitor will limit the influence of input trace inductance and source resistance during sudden load current changes. Larger input capacitor may be necessary if fast and large load transients are encountered in the application. Output Current is internally limited within the IC to a typical 600 mA. The NCP115 will source this amount of current measured with a voltage drops on the 90% of the nominal VOUT. If the Output Voltage is directly shorted to ground (VOUT = 0 V), the short circuit protection will limit the output current to 630 mA (typ). The current limit and short circuit protection will work properly over whole temperature range and also input voltage range. There is no limitation for the short circuit duration. Thermal Shutdown When the die temperature exceeds the Thermal Shutdown threshold (TSD − 160°C typical), Thermal Shutdown event is detected and the device is disabled. The IC will remain in this state until the die temperature decreases below the Thermal Shutdown Reset threshold (TSDU − 140°C typical). Once the IC temperature falls below the 140°C the LDO is enabled again. The thermal shutdown feature provides the protection from a catastrophic device failure due to accidental overheating. This protection is not intended to be used as a substitute for proper heat sinking. Output Decoupling (COUT) The NCP115 requires an output capacitor connected as close as possible to the output pin of the regulator. The recommended capacitor value is 1 mF and X7R or X5R dielectric due to its low capacitance variations over the specified temperature range. The NCP115 is designed to remain stable with minimum effective capacitance of 0.47 mF to account for changes with temperature, DC bias and package size. Especially for small package size capacitors such as 0402 the effective capacitance drops rapidly with the applied DC bias. There is no requirement for the minimum value of Equivalent Series Resistance (ESR) for the COUT but the maximum value of ESR should be less than 1.8 W. Larger output capacitors and lower ESR could improve the load transient response or high frequency PSRR. It is not recommended to use tantalum capacitors on the output due to their large ESR. The equivalent series resistance of tantalum capacitors is also strongly dependent on the temperature, increasing at low temperature. Power Dissipation As power dissipated in the NCP115 increases, it might become necessary to provide some thermal relief. The maximum power dissipation supported by the device is dependent upon board design and layout. Mounting pad configuration on the PCB, the board material, and the ambient temperature affect the rate of junction temperature rise for the part. The maximum power dissipation the NCP115 can handle is given by: Enable Operation P D(MAX) + The NCP115 uses the EN pin to enable/disable its device and to deactivate/activate the active discharge function. If the EN pin voltage is VIN. Due to this fact in cases, where the extended reverse current condition can be anticipated the device may require additional external protection. PCB Layout Recommendations Power Supply Rejection Ratio To obtain good transient performance and good regulation characteristics place CIN and COUT capacitors close to the device pins and make the PCB traces wide. In order to minimize the solution size, use 0402 capacitors. Larger copper area connected to the pins will also improve the device thermal resistance. The actual power dissipation can be calculated from the equation above (Equation 2). Expose pad should be tied the shortest path to the GND pin. The NCP115 features very good Power Supply Rejection ratio. If desired the PSRR at higher frequencies in the range 100 kHz − 10 MHz can be tuned by the selection of COUT capacitor and proper PCB layout. Turn−On Time The turn−on time is defined as the time period from EN assertion to the point in which VOUT will reach 98% of its nominal value. This time is dependent on various application conditions such as VOUT(NOM) COUT and TA. www.onsemi.com 14 NCP115 ORDERING INFORMATION − XDFN4 PACKAGE Device Voltage Option Marking NCP115AMX100TCG 1.0 V QN NCP115AMX105TCG 1.05 V QM NCP115AMX110TBG 1.1 V QL 1.2 V QA NCP115AMX150TCG 1.5 V QE NCP115AMX180TBG 1.8 V QC NCP115AMX250TCG 2.5 V QF NCP115AMX280TBG 2.8 V QG NCP115AMX300TCG 3.0 V QK NCP115AMX330TBG 3.3 V QH NCP115AMX360TCG 3.6 V QJ NCP115CMX100TCG 1.0 V RN NCP115CMX105TCG 1.05 V RM NCP115CMX110TBG 1.1 V RF 1.2 V RE NCP115CMX150TCG 1.5 V RG NCP115CMX180TBG 1.8 V RA NCP115CMX250TCG 2.5 V RH NCP115CMX280TBG 2.8 V RC NCP115CMX300TCG 3.0 V RK NCP115CMX330TBG 3.3 V RD 3.6 V RJ Description Package Shipping XDFN4 (Pb−Free) 3000 / Tape & Reel NCP115AMX110TCG NCP115AMX120TBG NCP115AMX120TCG NCP115AMX180TCG 300 mA, Active Discharge, Normal Slew−rate NCP115AMX280TCG NCP115AMX330TCG NCP115CMX110TCG NCP115CMX120TBG NCP115CMX120TCG NCP115CMX180TCG 300 mA, Active Discharge, Slow Slew−rate NCP115CMX280TCG NCP115CMX330TCG NCP115CMX360TCG www.onsemi.com 15 NCP115 ORDERING INFORMATION − TSOP−5 PACKAGE Device Voltage Option Marking NCP115ASN105T1G 1.05 V QAC NCP115ASN110T1G 1.1 V QAD NCP115ASN120T1G 1.2 V QAE NCP115ASN120T2G 1.2 V QAE NCP115ASN150T1G 1.5 V QAF NCP115ASN150T2G 1.5 V QAF NCP115ASN180T1G 1.8 V QAA NCP115ASN180T2G 1.8 V QAA NCP115ASN250T1G 2.5 V QAG NCP115ASN250T2G 2.5 V QAG NCP115ASN280T1G 2.8 V QAH NCP115ASN280T2G 2.8 V QAH NCP115ASN300T1G 3.0 V QAJ NCP115ASN330T1G 3.3 V QAK NCP115ASN330T2G 3.3 V QAK NCP115CSN105T1G 1.05 V QCC NCP115CSN110T1G 1.1 V QCD NCP115CSN120T1G 1.2 V QCE NCP115CSN150T1G 1.5 V QCF NCP115CSN180T1G 1.8 V QCA NCP115CSN250T1G 2.5 V QCG NCP115CSN280T1G 2.8 V QCH NCP115CSN300T1G 3.0 V QCJ NCP115CSN330T1G 3.3 V QCK Description Package Shipping 300 mA, Active Discharge, Normal Slew−rate TSOP−5 (Pb−Free) 3000 / Tape & Reel 300 mA, Active Discharge, Slow Slew−rate TSOP−5 (Pb−Free) 3000 / Tape & Reel Bluetooth is a registered trademark of Bluetooth SIG. ZigBee is a registered trademark of ZigBee Alliance. www.onsemi.com 16 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSOP−5 CASE 483 ISSUE N 5 1 SCALE 2:1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSION A. 5. OPTIONAL CONSTRUCTION: AN ADDITIONAL TRIMMED LEAD IS ALLOWED IN THIS LOCATION. TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2 FROM BODY. D 5X NOTE 5 2X DATE 12 AUG 2020 0.20 C A B 0.10 T M 2X 0.20 T 5 B 1 4 2 B S 3 K DETAIL Z G A A TOP VIEW DIM A B C D G H J K M S DETAIL Z J C 0.05 H C SIDE VIEW SEATING PLANE END VIEW GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 0.95 0.037 MILLIMETERS MIN MAX 2.85 3.15 1.35 1.65 0.90 1.10 0.25 0.50 0.95 BSC 0.01 0.10 0.10 0.26 0.20 0.60 0_ 10 _ 2.50 3.00 1.9 0.074 5 5 XXXAYWG G 1 1 Analog 2.4 0.094 XXX = Specific Device Code A = Assembly Location Y = Year W = Work Week G = Pb−Free Package 1.0 0.039 XXX MG G Discrete/Logic XXX = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) 0.7 0.028 SCALE 10:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98ARB18753C TSOP−5 *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS XDFN4 1.0x1.0, 0.65P CASE 711AJ ISSUE B 1 SCALE 4:1 GENERIC MARKING DIAGRAM* XX M 1 DOCUMENT NUMBER: DESCRIPTION: XX = Specific Device Code M = Date Code 98AON67179E XDFN4, 1.0X1.0, 0.65P DATE 25 JUN 2021 *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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