NCP1201D100R2

NCP1201 PWM Current−Mode Controller for Universal Off−Line Supplies Featuring Low Standby Power with Fault Protection Modes Housed in SOIC−8 or PDIP−8 package, the NCP1201 enhances the previous NCP1200 series by offering a reduced optocoupler current with additional Brownout Detection Protection (BOK). Similarly, the circuit allows the implementation of complete off−line AC−DC adapters, battery chargers or Switchmode Power Supplies (SMPS) where standby power is a key parameter. The NCP1201 features efficient protection circuitry. When in the presence of a fault (e.g. failed optocoupler, overcurrent condition, etc.) the control permanently disables the output pulses to avoid subsequent damage to the system. The IC only restarts when the user cycles the mains power supply. With the low power internal structure, operating at a fixed 60 or 100 kHz, the controller supplies itself from the high−voltage rail, avoiding the need of an auxiliary winding. This feature naturally eases the designer’s task in battery charger applications. Finally, current−mode control provides an excellent audio−susceptibility and inherent pulse−by−pulse control. When the load current falls down to a pre−defined setpoint (VSKIP) value, e.g. the output power demand diminishes, the IC automatically enters the skip cycle mode and can provide excellent efficiency under light load conditions. The skip mode is designed to operate at relatively lower peak current so that acoustic noise that commonly takes place will not happen with NCP1201. Features http://onsemi.com MARKING DIAGRAMS 8 8 1 SOIC−8 D SUFFIX CASE 751 1 8 PDIP−8 P SUFFIX CASE 626 1 1 1201Py0 AWL YYWWG 201Dx ALYW G 8 x y y xx A L Y, YY W, WW G or G = Device Code: 6 for 60 kHz 1 for 100 kHz = Device Code: 6 for 60 kHz 10 for 100 kHz = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package • • • • • • • • • • • • • AC Line Brownout Detect Protection, BOK Function Latchoff Mode Fault Protection No Auxiliary Winding Operation Internal Output Short−Circuit Protection Extremely Low No−Load Standby Power Current−Mode with Skip−Cycle Capability Internal Overtemperature Shutdown Internal Leading Edge Blanking 250 mA Gate Peak Current Driving Capability Internally Fixed Switching Frequency at 60 or 100 kHz Built−in Frequency Jittering for EMI Reduction Direct Optocoupler Connection Pb−Free Packages are Available PIN CONNECTIONS BOK FB CS GND 1 2 3 4 (Top View) 8 7 6 5 HV NC VCC DRV ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 17 of this data sheet. Typical Applications • AC−DC Adapters • Offline Battery Chargers • Auxiliary Power Supplies (USB, Appliances, TVs, etc.) © Semiconductor Components Industries, LLC, 2006 1 February, 2006 − Rev. 4 Publication Order Number: NCP1201/D NCP1201 C3 R3 470 p 100 k 250 V 1.0 W * D2 U1 1 4 2 3 2 3 + C2 4.7 m 400 V + 4 NCP1201 Q1 MTD1N60E 5 6 1N4937 + C5 10 m + C6 10 m 8 1N5819 D1 T1 L1 470 mH 0.2 A 6.5 V, 600 mA L3 47 mH 1.0 A R1 195.7 k DF06S + − BR1 90X264 Vac 1 C1 4.7 m 400 V C7 1.0 n 250 VAC Y1 + C4 10 mF SFH6156−2 4 R2 4.3 k L2 470 mH 0.2 A * Please refer to the application information section. R4 2.7 0.5 W 1 2 3 U2 D3 5V1 Figure 1. Typical Application Example http://onsemi.com 2 NCP1201 Iref BOK 1 + − 50 mA 10.5 V/12.5 V FB 2 Oscillator 60 or 100 kHz Clock + + CS 3 − 1.92 V − 80 K 1.07 V Output Skip Cycle Comparator + − 24 K Output Set Maximum 83% Duty Cycle Enable 6 Q Reset + − + Output − + − HV Current Source 7 NC 8 HV VCC Reset Reset TSD Startup Blanking GND 4 20 k + − 57 k 25 k Vref 250 ns L.E.B. + − Output 5 250 mA Internal Regulator Vref DRV 0.9 V Overload Figure 2. Simplified Functional Block Diagram http://onsemi.com 3 NCP1201 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PIN FUNCTION DESCRIPTION Pin No. 1 2 Pin Name BOK FB Function Bulk OK Description This pin detects the input line voltage by sensing the bulk capacitor, and disables the PWM when line voltage is lower than normal. Sets the Peak Current Setpoint By connecting an optocoupler to this pin, the peak current setpoint is adjusted according to the output power demand. Internal monitoring of this pin level triggers the fault management circuitry. This pin senses the primary inductor current and routes it to the internal comparator via an LEB circuit. − The driver’s output to an external MOSFET. This pin is connected to an external bulk capacitor of typically 10 mF. This unconnected pin ensures adequate creepage distance between High Voltage pin to other pins. Connected to the high−voltage rail, this pin injects a constant current into the VCC capacitor. 3 4 5 6 7 8 CS GND DRV VCC NC HV Current Sense Input The IC Ground Driving Pulses Supplies the IC No Connection Generates the VCC from the Line MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Power Supply Voltage, Pin 6 Input/Output Pins Pins 1, 2, 3, 5 Symbol VCC VIO Value Unit V V V −0.3, 16 −0.3, 6.5 500 100 178 Maximum Voltage on Pin 8 (HV) Thermal Resistance, Junction−to−Air, PDIP−8 Version Thermal Resistance, Junction−to−Air, SOIC Version Operating Junction Temperature Range Operating Ambient Temperature Range Storage Temperature Range ESD Capability, HBM (All pins except VCC and HV pins) (Note 1) ESD Capability, Machine Model (All pins except VCC and HV pins) (Note 1) VHV RqJA RqJA TJ TA Tstg − − °C/W °C/W °C °C °C kV V −40 to +150 −25 to +125 −55 to +150 2.0 200 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM) > 2.0 kV per JEDEC standard: JESD22−A114. Machine Model (MM) > 200 V per JEDEC standard: JESD22−A115. 2. Latchup Current Maximum Rating: ±150 mA per JEDEC standard: JESD78. http://onsemi.com 4 NCP1201 ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −25°C to +125°C, VCC = 11 V unless otherwise noted) Characteristic DYNAMIC SELF−SUPPLY VCC Increasing Level at which the Current Source Turns−Off VCC Decreasing Level at which the Current Source Turns−On Internal IC Current Consumption, No Output Load on Pin 5 Internal IC Current Consumption, 1.0 nF Output Load on Pin 5 NCP1201P60, NCP1201D60 NCP1201P100, NCP1201D100 Internal IC Current Consumption, Latchoff Phase INTERNAL STARTUP CURRENT SOURCE High−Voltage Current Source at VCCON – 0.2 V High−Voltage Current Source at VCC = 0 V HV Pin Leakage Current @ 450 V, VCC Pin Connected to Ground OUTPUT SECTION Output Voltage Rise−Time (CL = 1.0 nF, 10 V Output) Output Voltage Fall−Time (CL = 1.0 nF, 10 V Output) Source Resistance (VDRV = ) Sink Resistance (VDRV = ) CURRENT SENSE SECTION (Pin 5 Unloaded) Input Bias Current @ 1.0 V Input Level on Pin 3 Maximum Current Sense Input Threshold Default Current Sense Threshold for Skip Cycle Operation Propagation Delay from Current Detection to Gate OFF State Leading Edge Blanking Duration OSCILLATOR SECTION (VCC = 11 V, Pin 5 Loaded by 1.0 KW) Oscillation Frequency NCP1201P60, NCP1201D60 NCP1201P100, NCP1201D100 Built−in Frequency Jittering (as a function of Vcc voltage) NCP1201P60, NCP1201D60 NCP1201P100, NCP1201D100 Maximum Duty Cycle FEEDBACK SECTION (VCC = 11 V, Pin 5 Unloaded) Internal Pullup Resistor Feedback Pin to Pin 3 Current Setpoint Division Ratio BROWNOUT DETECT SECTION BOK Input Threshold Voltage BOK Input Bias Current (VBOK < Vth) Source Bias Current (Turn on After VBOK > Vth) FREQUENCY SKIP CYCLE SECTION Built−in Frequency Skip Cycle Comparator Voltage Threshold THERMAL SHUTDOWN Thermal Shutdown Trip Point, Temperature Rising (Note 3) Thermal Shutdown Hysteresis 3. Verified by design. TSD THYST − − 145 25 − − °C °C VSKIP 0.96 1.07 1.18 V Vth IIB−BOK ISC 1.75 − 40 1.92 11 50 2.05 100 58 V nA mA RUP Iratio 10 2.9 17 3.3 24 4.0 kW − Fjitter − − Dmax 74 493 822 83 − − 87 % FOSC 52 92 60 100 72 117 Hz/V kHz IIB−CS VILIMIT VILSKIP TDEL TLEB − 0.8 250 35 150 10 0.9 325 65 260 100 1.0 390 160 400 nA V mV ns ns Tr Tf ROH ROL − − 26 4.0 116 41 38 10 − − 60 22 ns ns W W IC1 IC2 ILEAK 3.6 7.5 − 5.3 11.1 30 7.1 15 70 mA mA mA VCCOFF VCCON ICC1 ICC2 0.75 1.6 ICC3 405 1.6 2.1 575 2.2 2.8 772 mA 11.5 9.6 440 12.5 10.5 905 13.5 11.3 1300 V V mA mA Symbol Min Typ Max Unit http://onsemi.com 5 NCP1201 TYPICAL CHARACTERISTICS VCCOFF, VCC OFF THRESHOLD VOLTAGE (V) VCCON, VCC ON THRESHOLD VOLTAGE (V) 12.9 12.7 12.5 12.3 12.1 11.9 11.7 −25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 10.8 10.6 10.4 10.2 10 9.8 −25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 Figure 3. VCC OFF Threshold Voltage vs. Junction Temperature Figure 4. VCC ON Threshold Voltage vs. Junction Temperature ICC2, CURRENT CONSUMPTION (mA) 1100 ICC1, CURRENT CONSUMPTION WITH NO LOAD (mA) 2.6 1 nF Load 2.4 2.2 2.0 1.8 1.6 1.4 −25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 60 KHz 1000 900 100 KHz 800 700 600 −25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 Figure 5. IC Current Consumption, ICC1 vs. Junction Temperature Figure 6. IC Current Consumption, ICC2 vs. Junction Temperature 700 ICC3, IC CURRENT CONSUMPTION AT LATCHOFF PHASE (mA) IC1, HV PIN STARTUP CURRENT SOURCE (mA) 8.0 VCC = 11 V 6.5 600 5.0 500 3.5 400 2.0 0.5 300 −25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 −25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 Figure 7. IC Current Consumption at Latchoff Phase vs. Junction Temperature Figure 8. HV Pin Startup Current Source vs. Junction Temperature http://onsemi.com 6 NCP1201 TYPICAL CHARACTERISTICS 14 IC2, HV PIN STARTUP CURRENT SOURCE (mA) ILEAK, LEAKAGE CURRENT (mA) 125 80 12 60 10 40 8 20 6 VCC = 0 V 4 −25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 0 −25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 Figure 9. HV Pin Startup Current Source vs. Junction Temperature Figure 10. Leakage Current vs. Junction Temperature 70 ROH, SOURCE RESISTANCE (W) ROL, SINK RESISTANCE (W) −25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 60 50 40 30 20 10 0 20 16 12 8 4 0 −25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 Figure 11. Output Source Resistance vs. Junction Temperature VILIMIT, MAXIMUM CURRENT SENSE THRESHOLD (V) IIB−CS, CS PIN INPUT BIAS CURRENT (nA) Figure 12. Output Sink Resistance vs. Junction Temperature 12 11 10 9 8 7 6 −25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 1.00 0.96 0.92 0.88 0.84 0.80 −25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 Figure 13. CS Pin Input Bias Current @ 1.0 V vs. Junction Temperature Figure 14. Maximum Current Sense Threshold vs. Junction Temperature http://onsemi.com 7 NCP1201 TYPICAL CHARACTERISTICS VILSKIP, DEFAULT CURRENT SENSE THRESHOLD FOR SKIP CYCLE (mV) 340 100 TDEL, PROPAGATION DELAY (nS) −25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 85 70 55 40 25 10 −25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 330 320 310 300 290 Figure 15. Default Current Setpoint for Skip Cycle vs. Junction Temperature 400 TLEB, LEADING EDGE BLANKING DURATION (nS) 350 300 250 200 150 100 50 0 −25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 Figure 16. Propagation Delay from Current Detection to Gate Driver vs. Junction Temperature FOSC, OSCILLATOR FREQUENCY (kHz) 120 100 KHz 100 80 60 KHz 60 40 20 0 −25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 Figure 17. Leading Edge Blanking Duration vs. Junction Temperature Figure 18. Oscillator Frequency vs. Junction Temperature 1400 Fjitter, FREQUENCY JITTER (Hz/V) 1200 1000 800 600 60 KHz 400 200 0 −25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 100 KHz Dmax, MAXIMUM DUTY CYCLE (%) 85 84 83 82 81 80 79 −25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 Figure 19. Frequency Jittering vs. Junction Temperature Figure 20. Maximum Duty Cycle vs. Junction Temperature http://onsemi.com 8 NCP1201 TYPICAL CHARACTERISTICS RUP, INTERNAL PULLUP RESISTOR (kW) 19 Iratio, FEEDBACK PIN TO PIN 3 CURRENT RATIO 18 17 16 15 14 13 −25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 3.40 3.35 3.30 3.25 3.20 3.15 3.10 3.05 3.00 −25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 Figure 21. FB Pin Pullup Resistor vs. Junction Temperature Vth, BOK INPUT THRESHOLD VOLTAGE (V) Figure 22. Feedback Pin to Pin 3 Current Setpoint Ratio vs. Junction Temperature IIB−BOK, BOK INPUT BIAS CURRENT (nA) 2.00 1.95 1.90 1.85 1.80 1.75 1.70 −25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 12 11 10 9 8 7 VBOK < Vth 6 −25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 Figure 23. BOK Threshold Voltage vs. Junction Temperature Figure 24. BOK Input Bias Current vs. Junction Temperature 51 50 49 48 47 46 VBOK < Vth 45 −25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 VSKIP, SKIP CYCLE COMPARATOR THRESHOLD VOLTAGE (V) ISC, BOK BIAS CURRENT (mA) 1.15 1.10 1.05 1.00 0.95 −25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 Figure 25. BOK Source Bias Current vs. Junction Temperature Figure 26. Skip Mode Threshold Voltage vs. Junction Temperature http://onsemi.com 9 NCP1201 DETAILED OPERATING DESCRIPTION Introduction The NCP1201 implements a standard current mode architecture where the switch−off time is dictated by the peak current setpoint. This component represents the ideal candidate where low part−count is the key criteria, particularly in low−cost AC−DC adapters, auxiliary supplies etc. Due to its high−performance High−Voltage technology, the NCP1201 incorporates all the necessary components normally needed in UC384X based supplies: timing components, feedback devices, low−pass filter and self−supply. This later point emphasizes the fact that ON Semiconductor’s NCP1201 does NOT need an auxiliary winding to operate: the device is self supplied from the high−voltage rail and delivers a VCC to the IC. This system is named the Dynamic Self−Supply (DSS). Dynamic Self−Supply The DSS principle is based on the charge/discharge of the VCC bulk capacitor from a low level up to a higher level. We can easily describe the current source operation following simple logic equations: POWER−ON: IF VCC < VCCOFF THEN Current Source is ON, no output pulses IF VCC decreasing > VCCON THEN Current Source is OFF, output is pulsing IF VCC increasing < VCCOFF THEN Current Source is ON, output is pulsing Typical values are: VCCOFF = 12.5 V, VCCON = 10.5 V To better understand the operation principle, Figure 27 sketch offers the necessary explanation, Vripple = 2 V VCCOFF = 12.5 V VCC VCCON = 10.5 V ON OFF Current Source Output Pulses 10 mS 30 mS 50 mS 70 mS 90 mS Figure 27. The Charge/Discharge Cycle Over a 10 mF VCC Capacitor The DSS behavior actually depends on the internal IC consumption and the MOSFET’s gate charge Qg. If we select a MOSFET like the MTP2N60E, Qg max equals 22 nC. With a maximum switching frequency of 70 kHz for the oscillator 60 kHz, the average power necessary to drive the MOSFET (excluding the driver efficiency and neglecting various voltage drops) is: Pdriver + Fsw(max) Qg VCC (eq. 1) Where, Pdriver = Average Power to drive the MOSFET Fsw(max) = Maximum switching frequency Qg = MOSFET’s gate charge VCC = VGS level applied to the gate of the MOSFET To obtain an estimation of the driving current, simply divide Pdriver by VCC, Idriver + Fsw(max) Qg + 1.54 mA (eq. 2) The total standby power consumption at no−load will therefore heavily rely on the internal IC current consumption plus the driving current (altered by the driver’s efficiency). Suppose that the IC is supplied from a 350 VDC line. The current flowing through pin 8 is a direct image of the NCP1201 current consumption (neglecting the switching losses of the HV current source). If ICC2 equals 2.1 mA @ TA = 25°C, then the power dissipated (lost) by the IC is simply: 350 V x 2.1 mA = 735 mW. For design and reliability reasons, it would be interesting to reduce this source of wasted power. In order to achieve that, different methods can be used. 1. Use a MOSFET with lower gate charge Qg; 2. Connect pin through a diode (1N4007 typically) to one of the mains input. The average value on pin 8 becomes: VmainsPEAK p 2 (eq. 3) http://onsemi.com 10 NCP1201 Our power contribution example drops to 223 V x 2.1 m = 468.3 mW. If a resistor is installed between the mains and the diode, you further force the dissipation to migrate from the package to the resistor. The resistor value should be carefully selected to account for low−line startup. HV 1 Mains Cbulk 2 3 4 8 7 6 5 Figure 28. A Simple Diode Naturally Reduces the Average Voltage on Pin 8 Skipping Cycle Mode The NCP1201 automatically skips switching cycles when the output power demand drops below a preset level. This is accomplished by monitoring the FB pin. In normal operation, FB pin imposes a peak current according to the load value. If the load demand decreases, the internal loop asks for less peak current. When this set−point reaches the skip mode threshold level, 1.07 V, the IC prevents the current from decreasing further down and starts to blank the output pulses, i.e. the controller enters the so−called Skip Cycle Mode, also named Controlled Burst Operation. The power transfer now depends upon the width of the pulse bunches, Figure 29. Suppose we have the following component values: Lp, primary inductance = 1.0 mH Fsw, switching frequency = 60 kHz Ip (skip) = 200 mA (or 333 mV/Rsense) The theoretical power transfer is therefore: 1 2 Lp Ip2 Fsw + 1.2 W (eq. 4) 3. Permanently force the VCC level above VCCOFF with an auxiliary winding. It will automatically disconnect the internal startup source and the IC will be fully self−supplied from this winding. Again, the total power drawn from the mains will significantly decrease. By using this approach, user need to make sure the auxiliary voltage never exceeds the 16 V limit for all line conditions. If the controller enters Skip Cycle Mode with a pulse packet length of 20 ms over a recurrent period of 100 ms, then the total power transfer reduced to 1.2 W x 0.2 = 240 mW. To better understand how this Skip Cycle Mode takes place, a look at the operation mode versus the FB pin voltage level shown below, immediately gives the necessary insight. FB 4.2 V, FB Pin Open 2.97 V, Upper Dynamic Range Normal Current Mode Operation Skip Cycle Operation Ip(min) = 333 mV / Rsense 1.07 V Figure 29. Feedback Pin Voltage and Modes of Operation When FB pin voltage level is above the skip cycle threshold (1.07 V by default), the peak current cannot exceed 0.9 V/Rsense. When the IC enters the skip cycle mode, the peak current cannot go below VSKIP/3.3. By using the peak current limit reduction scheme, the skip cycle takes place at a lower peak current, which guarantees noise free operation. http://onsemi.com 11 NCP1201 P1 = 0.4 W P2 = 1.8 W P3 = 3.6 W Figure 30. MOSFET VDS at Various Power Levels, P1