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NCP1201
PWM Current-- Mode
Controller for Universal
Off-- Line Supplies Featuring
Low Standby Power with
Fault Protection Modes
Housed in SOIC--8 or PDIP--8 package, the NCP1201 enhances the
previous NCP1200 series by offering a reduced optocoupler current with
additional Brownout Detection Protection (BOK). Similarly, the circuit
allows the implementation of complete off--line AC--DC adapters, battery
chargers or Switchmode Power Supplies (SMPS) where standby power is
a key parameter.
The NCP1201 features efficient protection circuitry. When in the
presence of a fault (e.g. failed optocoupler, overcurrent condition, etc.)
the control permanently disables the output pulses to avoid subsequent
damage to the system. The IC only restarts when the user cycles the
mains power supply.
With the low power internal structure, operating at a fixed
60 or 100 kHz, the controller supplies itself from the high--voltage rail,
avoiding the need of an auxiliary winding. This feature naturally eases
the designer’s task in battery charger applications. Finally, current--mode
control provides an excellent audio--susceptibility and inherent
pulse--by--pulse control.
When the load current falls down to a pre--defined setpoint (VSKIP)
value, e.g. the output power demand diminishes, the IC automatically
enters the skip cycle mode and can provide excellent efficiency under
light load conditions. The skip mode is designed to operate at relatively
lower peak current so that acoustic noise that commonly takes place will
not happen with NCP1201.
Features
AC Line Brownout Detect Protection, BOK Function
Latchoff Mode Fault Protection
No Auxiliary Winding Operation
Internal Output Short--Circuit Protection
Extremely Low No--Load Standby Power
Current--Mode with Skip--Cycle Capability
Internal Overtemperature Shutdown
Internal Leading Edge Blanking
250 mA Gate Peak Current Driving Capability
Internally Fixed Switching Frequency at 60 or 100 kHz
Built--in Frequency Jittering for EMI Reduction
Direct Optocoupler Connection
These Devices are Pb--Free, Halogen Free/BFR Free and are RoHS
Compliant
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MARKING
DIAGRAMS
8
SOIC--8
D SUFFIX
CASE 751
8
1
201Dx
ALYW
G
1
8
1201Py0
AWL
YYWWG
PDIP--8
P SUFFIX
CASE 626
8
1
1
x
y
y
xx
A
L
Y, YY
W, WW
G or G
= Device Code: 6 for 60 kHz
1 for 100 kHz
= Device Code: 6 for 60 kHz
10 for 100 kHz
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb--Free Package
PIN CONNECTIONS
BOK
1
8
HV
FB
2
7
NC
CS
3
6
VCC
GND
4
5
DRV
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
Typical Applications
AC--DC Adapters
Offline Battery Chargers
Auxiliary Power Supplies (USB, Appliances, TVs, etc.)
Semiconductor Components Industries, LLC, 2010
December, 2010 -- Rev. 6
1
Publication Order Number:
NCP1201/D
NCP1201
C3
R3
470 p 100 k
250 V 1.0 W
L1
DF06S
U1
1
3
D1
8
C1
4.7 m
400 V
C2
4.7 m
400 V
+
L3
1N5819
47 mH
1.0 A
+ C5
10 m
6
3
+
D2
1N4937
2
4
5
NCP1201
Q1
MTD1N60E
C7
1.0 n
250 VAC Y1
+ C4
10 mF
4
R2
4.3 k
R4
2.7
0.5 W
L2
470 mH
0.2 A
* Please refer to the application information section.
Figure 1. Typical Application Example
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2
SFH6156--2
1
2
3
90~264
Vac
4
BR1
6.5 V, 600 mA
*
R1
195.7 k
2
+
--
1
470 mH
0.2 A
T1
U2
D3
5V1
+ C6
10 m
NCP1201
Iref
BOK
1
8
+
+
-50 mA
10.5 V/12.5 V
Oscillator
60 or 100 kHz Clock
+
CS
3
1.92 V
--
Output
-80 K 1.07 V
Skip Cycle
Comparator
+
Set
Output
Reset
Reset
24 K
GND
4
20 k
+
--
57 k
25 k
Vref
NC
6
Q
VCC
TSD
+
--
7
--
Maximum 83%
Duty Cycle
--
250 ns
L.E.B.
HV Current
Source
Enable
+
--
--
Reset
FB
2
+
+ Output
HV
Startup
Blanking
Output
0.9 V
Overload
Figure 2. Simplified Functional Block Diagram
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3
5
250 mA
Internal
Regulator
Vref
DRV
NCP1201
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Function
Description
1
BOK
Bulk OK
This pin detects the input line voltage by sensing the bulk capacitor, and
disables the PWM when line voltage is lower than normal.
2
FB
Sets the Peak Current Setpoint
By connecting an optocoupler to this pin, the peak current setpoint is adjusted according to the output power demand. Internal monitoring of this
pin level triggers the fault management circuitry.
3
CS
Current Sense Input
This pin senses the primary inductor current and routes it to the internal
comparator via an LEB circuit.
4
GND
The IC Ground
--
5
DRV
Driving Pulses
The driver’s output to an external MOSFET.
6
VCC
Supplies the IC
This pin is connected to an external bulk capacitor of typically 10 mF.
7
NC
No Connection
This unconnected pin ensures adequate creepage distance between High
Voltage pin to other pins.
8
HV
Generates the VCC from the Line
Connected to the high--voltage rail, this pin injects a constant current into
the VCC capacitor.
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating
Symbol
Value
Unit
Power Supply Voltage, Pin 6
VCC
--0.3, 16
V
Input/Output Pins
Pins 1, 2, 3, 5
VIO
--0.3, 6.5
V
Maximum Voltage on Pin 8 (HV)
VHV
500
V
Thermal Resistance, Junction--to--Air, PDIP--8 Version
Thermal Resistance, Junction--to--Air, SOIC Version
RθJA
RθJA
100
178
C/W
C/W
Operating Junction Temperature Range
TJ
--40 to +150
C
Operating Ambient Temperature Range
TA
--25 to +125
C
Storage Temperature Range
Tstg
--55 to +150
C
ESD Capability, HBM (All pins except VCC and HV pins) (Note 1)
--
2.0
kV
ESD Capability, Machine Model (All pins except VCC and HV pins) (Note 1)
--
200
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model (HBM) > 2.0 kV per JEDEC standard: JESD22--A114.
Machine Model (MM) > 200 V per JEDEC standard: JESD22--A115.
2. Latchup Current Maximum Rating: 150 mA per JEDEC standard: JESD78.
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NCP1201
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25C, for min/max values TJ = --25C to +125C,
VCC = 11 V unless otherwise noted)
Symbol
Min
Typ
Max
Unit
VCC Increasing Level at which the Current Source Turns--Off
VCCOFF
11.5
12.5
13.5
V
VCC Decreasing Level at which the Current Source Turns--On
VCCON
9.6
10.5
11.3
V
Internal IC Current Consumption, No Output Load on Pin 5
ICC1
440
905
1300
mA
Internal IC Current Consumption, 1.0 nF Output Load on Pin 5
NCP1201P60, NCP1201D60
NCP1201P100, NCP1201D100
ICC2
0.75
1.6
1.6
2.1
2.2
2.8
Internal IC Current Consumption, Latchoff Phase
ICC3
405
575
772
mA
High--Voltage Current Source at VCCON – 0.2 V
IC1
3.6
5.3
7.1
mA
High--Voltage Current Source at VCC = 0 V
IC2
7.5
11.1
15
mA
ILEAK
--
30
70
mA
Output Voltage Rise--Time (CL = 1.0 nF, 10 V Output)
Tr
--
116
--
ns
Output Voltage Fall--Time (CL = 1.0 nF, 10 V Output)
Tf
--
41
--
ns
Characteristic
DYNAMIC SELF--SUPPLY
mA
INTERNAL STARTUP CURRENT SOURCE
HV Pin Leakage Current @ 450 V, VCC Pin Connected to Ground
OUTPUT SECTION
Source Resistance (VDRV = )
ROH
26
38
60
Ω
Sink Resistance (VDRV = )
ROL
4.0
10
22
Ω
CURRENT SENSE SECTION (Pin 5 Unloaded)
Input Bias Current @ 1.0 V Input Level on Pin 3
IIB--CS
--
10
100
nA
Maximum Current Sense Input Threshold
VILIMIT
0.8
0.9
1.0
V
Default Current Sense Threshold for Skip Cycle Operation
VILSKIP
250
325
390
mV
Propagation Delay from Current Detection to Gate OFF State
TDEL
35
65
160
ns
Leading Edge Blanking Duration
TLEB
150
260
400
ns
52
92
60
100
72
117
---
493
822
---
74
83
87
%
OSCILLATOR SECTION (VCC = 11 V, Pin 5 Loaded by 1.0 kΩ)
Oscillation Frequency
NCP1201P60, NCP1201D60
NCP1201P100, NCP1201D100
FOSC
Built--in Frequency Jittering (as a function of Vcc voltage)
NCP1201P60, NCP1201D60
NCP1201P100, NCP1201D100
Fjitter
Maximum Duty Cycle
Dmax
kHz
Hz/V
FEEDBACK SECTION (VCC = 11 V, Pin 5 Unloaded)
Internal Pullup Resistor
RUP
10
17
24
kΩ
Feedback Pin to Pin 3 Current Setpoint Division Ratio
Iratio
2.9
3.3
4.0
--
BROWNOUT DETECT SECTION
BOK Input Threshold Voltage
BOK Input Bias Current (VBOK < Vth)
Source Bias Current (Turn on After VBOK > Vth)
Vth
1.75
1.92
2.05
V
IIB--BOK
--
11
100
nA
ISC
40
50
58
mA
VSKIP
0.96
1.07
1.18
V
TSD
--
145
--
C
THYST
--
25
--
C
FREQUENCY SKIP CYCLE SECTION
Built--in Frequency Skip Cycle Comparator Voltage Threshold
THERMAL SHUTDOWN
Thermal Shutdown Trip Point, Temperature Rising (Note 3)
Thermal Shutdown Hysteresis
3. Verified by design.
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5
NCP1201
VCCON, VCC ON THRESHOLD VOLTAGE (V)
VCCOFF, VCC OFF THRESHOLD VOLTAGE (V)
TYPICAL CHARACTERISTICS
12.9
12.7
12.5
12.3
12.1
11.9
11.7
--25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)
125
10.8
10.6
10.4
10.2
10
9.8
--25
Figure 3. VCC OFF Threshold Voltage
vs. Junction Temperature
ICC2, CURRENT CONSUMPTION (mA)
ICC1, CURRENT CONSUMPTION
WITH NO LOAD (mA)
1000
900
800
700
--25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)
125
1 nF Load
2.4
2.2
100 KHz
2.0
1.8
60 KHz
1.6
1.4
--25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)
125
Figure 6. IC Current Consumption, ICC2
vs. Junction Temperature
700
8.0
IC1, HV PIN STARTUP CURRENT
SOURCE (mA)
ICC3, IC CURRENT CONSUMPTION
AT LATCHOFF PHASE (mA)
125
2.6
Figure 5. IC Current Consumption, ICC1
vs. Junction Temperature
600
500
400
300
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)
Figure 4. VCC ON Threshold Voltage
vs. Junction Temperature
1100
600
0
--25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)
125
Figure 7. IC Current Consumption at Latchoff Phase
vs. Junction Temperature
VCC = 11 V
6.5
5.0
3.5
2.0
0.5
--25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)
Figure 8. HV Pin Startup Current Source
vs. Junction Temperature
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125
NCP1201
TYPICAL CHARACTERISTICS
80
ILEAK, LEAKAGE CURRENT (mA)
IC2, HV PIN STARTUP CURRENT
SOURCE (mA)
14
12
10
8
6
VCC = 0 V
4
--25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)
60
40
20
0
125
--25
Figure 9. HV Pin Startup Current Source
vs. Junction Temperature
ROL, SINK RESISTANCE (Ω)
ROH, SOURCE RESISTANCE (Ω)
50
40
30
20
10
--25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)
16
12
8
4
0
125
--25
12
11
10
9
8
7
--25
0
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)
125
Figure 12. Output Sink Resistance
vs. Junction Temperature
VILIMIT, MAXIMUM CURRENT SENSE THRESHOLD (V)
Figure 11. Output Source Resistance
vs. Junction Temperature
IIB--CS, CS PIN INPUT BIAS CURRENT (nA)
125
20
60
6
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)
Figure 10. Leakage Current vs.
Junction Temperature
70
0
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)
125
Figure 13. CS Pin Input Bias Current @ 1.0 V
vs. Junction Temperature
1.00
0.96
0.92
0.88
0.84
0.80
--25
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)
Figure 14. Maximum Current Sense Threshold
vs. Junction Temperature
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7
0
125
NCP1201
340
100
TDEL, PROPAGATION DELAY (nS)
VILSKIP, DEFAULT CURRENT SENSE
THRESHOLD FOR SKIP CYCLE (mV)
TYPICAL CHARACTERISTICS
330
320
310
300
290
--25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)
55
40
25
--25
125
FOSC, OSCILLATOR FREQUENCY (kHz)
100 KHz
100
300
250
200
150
100
50
--25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)
125
80
60 KHz
60
40
20
0
--25
Figure 17. Leading Edge Blanking Duration
vs. Junction Temperature
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)
125
Figure 18. Oscillator Frequency
vs. Junction Temperature
1400
85
Dmax, MAXIMUM DUTY CYCLE (%)
Fjitter, FREQUENCY JITTER (Hz/V)
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)
120
350
1200
1000
100 KHz
800
600
60 KHz
400
200
0
0
Figure 16. Propagation Delay from Current Detection to
Gate Driver vs. Junction Temperature
400
TLEB, LEADING EDGE BLANKING
DURATION (nS)
70
10
125
Figure 15. Default Current Setpoint for Skip Cycle
vs. Junction Temperature
0
85
--25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)
125
84
83
82
81
80
79
--25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)
Figure 20. Maximum Duty Cycle
vs. Junction Temperature
Figure 19. Frequency Jittering
vs. Junction Temperature
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125
NCP1201
3.40
Iratio, FEEDBACK PIN TO PIN 3
CURRENT RATIO
RUP, INTERNAL PULLUP RESISTOR (kΩ)
TYPICAL CHARACTERISTICS
19
18
17
16
15
14
13
--25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)
3.20
3.15
3.10
3.05
IIB--BOK, BOK INPUT BIAS CURRENT (nA)
Vth, BOK INPUT THRESHOLD VOLTAGE (V)
3.25
--25
125
1.95
1.90
1.85
1.80
1.75
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)
125
12
11
10
9
8
7
VBOK < Vth
6
--25
Figure 23. BOK Threshold Voltage
vs. Junction Temperature
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)
125
Figure 24. BOK Input Bias Current
vs. Junction Temperature
1.15
VSKIP, SKIP CYCLE COMPARATOR
THRESHOLD VOLTAGE (V)
51
ISC, BOK BIAS CURRENT (mA)
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)
Figure 22. Feedback Pin to Pin 3 Current Setpoint Ratio
vs. Junction Temperature
2.00
--25
3.30
3.00
125
Figure 21. FB Pin Pullup Resistor
vs. Junction Temperature
1.70
3.35
50
1.10
49
1.05
48
47
1.00
46
45
VBOK < Vth
--25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)
0.95
125
Figure 25. BOK Source Bias Current
vs. Junction Temperature
--25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)
Figure 26. Skip Mode Threshold Voltage
vs. Junction Temperature
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125
NCP1201
DETAILED OPERATING DESCRIPTION
Introduction
The NCP1201 implements a standard current mode
architecture where the switch--off time is dictated by the peak
current setpoint. This component represents the ideal
candidate where low part--count is the key criteria,
particularly in low--cost AC--DC adapters, auxiliary supplies
etc. Due to its high--performance High--Voltage technology,
the NCP1201 incorporates all the necessary components
normally needed in UC384X based supplies: timing
components, feedback devices, low--pass filter and
self--supply. This later point emphasizes the fact that
ON Semiconductor’s NCP1201 does NOT need an auxiliary
winding to operate: the device is self supplied from the
high--voltage rail and delivers a VCC to the IC. This system
is named the Dynamic Self--Supply (DSS).
Vripple = 2 V
Dynamic Self--Supply
The DSS principle is based on the charge/discharge of the
VCC bulk capacitor from a low level up to a higher level. We
can easily describe the current source operation following
simple logic equations:
POWER--ON: IF VCC < VCCOFF THEN
Current Source is ON, no output pulses
IF VCC decreasing > VCCON THEN
Current Source is OFF, output is pulsing
IF VCC increasing < VCCOFF THEN
Current Source is ON, output is pulsing
Typical values are: VCCOFF = 12.5 V, VCCON = 10.5 V
To better understand the operation principle, Figure 27
sketch offers the necessary explanation,
VCCOFF = 12.5 V
VCC
VCCON = 10.5 V
ON
OFF
Current
Source
Output Pulses
10 mS
30 mS
50 mS
70 mS
90 mS
Figure 27. The Charge/Discharge Cycle Over a 10 mF VCC Capacitor
The DSS behavior actually depends on the internal IC
consumption and the MOSFET’s gate charge Qg. If we
select a MOSFET like the MTP2N60E, Qg max equals
22 nC. With a maximum switching frequency of 70 kHz for
the oscillator 60 kHz, the average power necessary to drive
the MOSFET (excluding the driver efficiency and
neglecting various voltage drops) is:
Pdriver = Fsw(max) × Qg × VCC
The total standby power consumption at no--load will
therefore heavily rely on the internal IC current
consumption plus the driving current (altered by the driver’s
efficiency). Suppose that the IC is supplied from a 350 VDC
line. The current flowing through pin 8 is a direct image of
the NCP1201 current consumption (neglecting the
switching losses of the HV current source). If ICC2 equals
2.1 mA @ TA = 25C, then the power dissipated (lost) by the
IC is simply: 350 V x 2.1 mA = 735 mW. For design and
reliability reasons, it would be interesting to reduce this
source of wasted power. In order to achieve that, different
methods can be used.
1. Use a MOSFET with lower gate charge Qg;
2. Connect pin through a diode (1N4007 typically) to
one of the mains input. The average value on pin 8
becomes:
(eq. 1)
Where,
Pdriver = Average Power to drive the MOSFET
Fsw(max) = Maximum switching frequency
Qg = MOSFET’s gate charge
VCC = VGS level applied to the gate of the MOSFET
To obtain an estimation of the driving current, simply
divide Pdriver by VCC,
VmainsPEAK × 2
π
Idriver = Fsw(max) × Qg = 1.54 mA (eq. 2)
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10
(eq. 3)
NCP1201
Skipping Cycle Mode
The NCP1201 automatically skips switching cycles when
the output power demand drops below a preset level. This is
accomplished by monitoring the FB pin. In normal
operation, FB pin imposes a peak current according to the
load value. If the load demand decreases, the internal loop
asks for less peak current. When this set--point reaches the
skip mode threshold level, 1.07 V, the IC prevents the
current from decreasing further down and starts to blank the
output pulses, i.e. the controller enters the so--called Skip
Cycle Mode, also named Controlled Burst Operation. The
power transfer now depends upon the width of the pulse
bunches, Figure 29.
Suppose we have the following component values:
Lp, primary inductance = 1.0 mH
Fsw, switching frequency = 60 kHz
Ip (skip) = 200 mA (or 333 mV/Rsense)
The theoretical power transfer is therefore:
Our power contribution example drops to 223 V x 2.1 m
= 468.3 mW. If a resistor is installed between the mains and
the diode, you further force the dissipation to migrate from
the package to the resistor. The resistor value should be
carefully selected to account for low--line startup.
HV
Mains
Cbulk
1
8
2
7
3
6
4
5
Figure 28. A Simple Diode Naturally Reduces the
Average Voltage on Pin 8
1×L ×I 2×F
p
p
sw = 1.2 W
2
3. Permanently force the VCC level above VCCOFF
with an auxiliary winding. It will automatically
disconnect the internal startup source and the IC
will be fully self--supplied from this winding.
Again, the total power drawn from the mains will
significantly decrease. By using this approach,
user need to make sure the auxiliary voltage never
exceeds the 16 V limit for all line conditions.
(eq. 4)
If the controller enters Skip Cycle Mode with a pulse packet
length of 20 ms over a recurrent period of 100 ms, then the
total power transfer reduced to 1.2 W x 0.2 = 240 mW.
To better understand how this Skip Cycle Mode takes
place, a look at the operation mode versus the FB pin voltage
level shown below, immediately gives the necessary insight.
FB
4.2 V, FB Pin Open
2.97 V, Upper Dynamic Range
Normal Current Mode Operation
Skip Cycle Operation
Ip(min) = 333 mV / Rsense
1.07 V
Figure 29. Feedback Pin Voltage and Modes of Operation
When FB pin voltage level is above the skip cycle threshold
(1.07 V by default), the peak current cannot exceed
0.9 V/Rsense. When the IC enters the skip cycle mode, the
peak current cannot go below VSKIP/3.3. By using the peak
current limit reduction scheme, the skip cycle takes place at
a lower peak current, which guarantees noise free operation.
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11
NCP1201
P1 = 0.4 W
P2 = 1.8 W
P3 = 3.6 W
Figure 30. MOSFET VDS at Various Power Levels, P1
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