NCP1205DR2G

NCP1205 Single Ended PWM Controller Featuring QR Operation and Soft Frequency Foldback The NCP1205 combines a true Current Mode Control modulator and a demagnetization detector to ensure full Discontinuous Conduction Mode in any load/line conditions and minimum drain voltage switching (Quasi−Resonant operation, also called critical conduction operation). With its inherent Variable Frequency Mode (VFM), the controller decreases its operating frequency at constant peak current whenever the output power demand diminishes. Associated with automatic multiple valley switching, this unique architecture guarantees minimum switching losses and the lowest power drawn from the mains when operating at no−load conditions. Thus, the NCP1205 is optimal for applications targeting the newest International Energy Agency (IEA) recommendations for standby power. The internal High−Voltage current source provides a reliable charging path for the VCC capacitor and ensures a clean and short startup sequence without deteriorating the efficiency once off. The continuous feedback signal monitoring implemented with an Overcurrent fault Protection circuitry (OCP) makes the final design rugged and reliable. The PDIP−14 offers an adjustable version of the OVP threshold via an external resistive network. Features http://onsemi.com MARKING DIAGRAM 8 PDIP−8 N SUFFIX CASE 626 1 1 14 14 1 PDIP−14 P SUFFIX CASE 646 1 16 16 1 SOIC−16 D SUFFIX CASE 751B 1 A WL YY, Y WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package NCP1205DG AWLYWW NCP1205P2 AWLYYWWG 1205P AWL YYWWG 8 • Natural Drain Valley Switching for Lower EMI and Quasi−Resonant • • • • • • • • • • • • • • • Operation (QR) Smooth Frequency Foldback for Low Standby and Minimum Ripple at Light−Load Adjustable Maximum Switching Frequency Internal 200 ns Leading Edge Blanking on Current Sense 250 mA Sink and Source Driver Wide Operating Voltages: 8.0 to 30 V Wide UVLO Levels: 7.2 to 15 V Typical Auto−Recovery Internal Short−Circuit Protection (OCP) Integrated 3.0 mA Typ Startup Source Current Mode Control Adjustable Overvoltage Level Pb−Free Packages are Available* High Power AC/DC Adapters for Notebooks, etc. Offline Battery Chargers Power Supplies for DVD, CD Players, TVs, Set−Top Boxes, etc. Auxiliary Power Supplies (USB, Appliances, etc.) ORDERING INFORMATION Device NCP1205P NCP1205PG NCP1205P2 NCP1205P2G NCP1205DR2 NCP1205DR2G Package PDIP−8 PDIP−8 (Pb−Free) PDIP−14 PDIP−14 (Pb−Free) SOIC−16 SOIC−16 (Pb−Free) Shipping† 50 Units/Rail 50 Units/Rail 25 Units/Rail 25 Units/Rail 2500/Tape & Reel 2500/Tape & Reel Applications *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Publication Order Number: NCP1205/D October, 2006 − Rev. 7 1 NCP1205 PIN CONNECTIONS HV HV 1 NC 2 Demag 3 HV 1 Demag 2 FB 3 Ct 4 PDIP−8 8 VCC 7 Drive 6 Isense 5 GND FB 4 Ct 5 OVP 6 NC 7 PDIP−14 14 NC 13 VCC 12 Drive 11 Isense 10 GND 9 NC 8 NC NC NC Demag FB Ct OVP NC 1 2 3 4 5 6 7 8 SOIC−16 16 NC 15 NC 14 VCC 13 Drive 12 Isense 11 GND 10 NC 9 NC PIN FUNCTION DESCRIPTION Pin No. PDIP−8 1 2 3 4 5 NA 6 7 8 PDIP−14 1 3 4 5 10 6 11 12 13 SOIC−16 1 4 5 6 11 7 12 13 14 Pin Name HV Demag FB Ct GND OVP Isense Drv VCC Function Startup rail Zero primary−current detection Feedback signal to control the PWM Timing capacitor The IC’s ground Overvoltage input The primary−current sensing pin This pin drives the external switcher Powers the IC Description Connected to the rectified HV rail, this pin provides a charging path to VCC bulk capacitor. This pin ensures the restart of the main switcher when operating in free−run. This level modulates the peak current level in free−running operation and modulates the frequency in VFM operation. By adding a capacitor from Ct to the ground, the user selects the minimum/maximum operating frequency. − By applying a 2.8 V typical level on this pin, the IC is permanently latched−off until VCC falls below UVLOL. This pin senses the primary current via an external shunt resistor. The IC is able to deliver or absorb 250 mA peak currents while delivering a clamped driving signal. A positive voltage up to 30 V maximum can be applied upon this pin before the IC stops. 1. PDIP−14 has different pinouts. Please see Pin Connections. 2. Pin 2, 7, 8, 9 and 14 are nonconnected on PDIP−14. 3. Pin 2, 3, 8, 9, 10, 15 and 16 are nonconnected on SOIC−16. http://onsemi.com 2 NCP1205 R2 150 + C1 10 mF 4x1N4007 + C14 22 mF D2 1N4148 D6 1N5819 C10 470 mF 10 V + L2 10 mH 5V + C11 100 mF 10 V R5 15 R8 22 k * R10 15 k M2 MTD1N60E 1 2 4 8 R4 10 IC4 D7 5.1 V Universal Input 7 NCP1205P 6 3 5 SFH6156−2 R6 4.7 k C12 1 nF R3 3.3 R1 560 C13 1.5 nF Y1 * Please refer to the application information section regarding this element. Figure 1. Typical Application Example for PDIP−8 Version + C1 10 mF R2 15 D2 1N4148 R5 15 R8 22 k 1 2 Universal Input 3 4 5 6 7 R6 2.7 k ROVPU 4x1N4007 * R10 15 k + C14 33 mF/35 V D6 1N5819 C10 470 mF 10 V + L2 10 mH 5V + C11 47 mF 10 V D7 4.3 V NCP1205P2 14 13 12 11 10 9 8 SFH6156−2 M2 MTD1N60E R4 6.8 IC4 R1 560 ROVPL C12 1 nF R3 3.3 * Please refer to the application information section regarding this element. Figure 2. Typical Application Example for PDIP−14 Version http://onsemi.com 3 NCP1205 Startup UVLOH = 15 V UVLOL = 7.2 V Internal VCC Internal Regulator 7 DRV Internal Clamp Verr Max = 3 V Verr Min = 10 mV 1/3 250 mV − 1 V Max Setpoint Clock R Flip−Flop Q D 2.5 V Current Comparator − + 5 GND 200 ns L.E.B 1V Verr VCO Feedback Toff = f (Verr) Max Toff = f (Ct) OVP − + Driver 6 Isense HV 1 Last Pulse of Demag after 4 ms 8 VCC Demag 2 DEMAG ? Rf − + + − Ri FB 3 Ct 4 Over Current Protection (OCP) V(−) < 1.5 V + − Lasts more than 128 ms? −−> Protection Circuitry 250 mV Clamp 18 k + − 2.8 V Figure 3. Internal Circuit Architecture for PDIP−8 Version http://onsemi.com 4 NCP1205 VCC Pin 13 Startup UVLOH = 15 V UVLOL = 7.2 V Last Pulse of Demag after 4 ms Internal VCC Internal Regulator HV 1 NC 2 Demag 3 14 13 VCC 12 DRV DEMAG ? Rf − + + − 2.5 V Verr Max = 3 V Verr Min = 10 mV 1/3 250 mV − 1 V Max Setpoint OVP Clock R Flip−Flop Q D Current Comparator − + 200 ns L.E.B Driver Internal Clamp Ri FB 4 11 Isense Ct 5 OVP 6 NC 7 Over Current Protection (OCP) V(−) < 1.5 V + − Lasts more than 128 ms? −−> Protection Circuitry 10 GND 9 NC 250 mV Clamp 1V Verr VCO Feedback Toff = f (Verr) Max Toff = f (Ct) OVP 2.0 k − + 8 NC 18 k + − 2.8 V Figure 4. Internal Circuit Architecture for PDIP−14 Version http://onsemi.com 5 NCP1205 MAXIMUM RATINGS Pin No. Rating Power Supply Voltage Thermal Resistance Junction−to−Air PDIP−8 PDIP−14 SOIC−16 PDIP−8 8 − − − − − − All Pins All Pins 2 PDIP−14 13 − − − − − − All Pins All Pins 3 SOIC−16 14 − − − − − − All Pins All Pins 4 Symbol Vin RqJA Min − − − − − − − − − Value Max 30 100 100 145 −25 to +125 150 −60 to +150 2.0 200 −5.0/+10 Unit V °C/W Operating Junction Temperature Range Maximum Junction Temperature Storage Temperature Range ESD Capability, HBM Model ESD Capability, Machine Model Demagnetization Pin Current TJ TJmax Tstg − − − °C °C °C kV V mA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. VCC = 12 V unless otherwise noted.) ELECTRICAL CHARACTERISTICS (For typical values TA = 25°C, for min/max values TJ = −25°C to +125°C, Max TJ = 150°C, Pin No. Characteristics Demagnetization Block Input Threshold Voltage (Vpin2 increasing) Hysteresis (Vpin2 decreasing) Input Clamp Voltage High State (Ipin2 = 3.0 mA) Low State (Ipin2 = −3.0 mA) Demag Propagation Delay No Demag Signal Activation Internal Input Capacitance at 1.0 V Demag Propagation Delay with 22 kW External Resistor Feedback Path Input Impedance at VFB = 3.0 V Internal Error Amplifier Closed Loop Gain Internal Built−In Offset Voltage for Error Detection Error Amplifier Level of VCO Take Over Internal Divider from Internal Error Amp, Pin to Current Setpoint Fault Detection Circuitry Internal Over Current Level Fault Time Duration to Latch Activation @ Ct = 1.0 ηF Over Current Latchoff Phase @ Ct = 1.0 ηF Hysteresis when VFB goes back into Regulation Overvoltage Protection Threshold for PDIP−14 and SOIC−16 versions Current Sense Comparator Input Bias Current @ 1.0 V Maximum Current Setpoint Minimum Current Setpoint 6 6 6 11 11 11 12 12 12 IIB Vcl Vmin − 0.9 225 0.02 1.0 250 − 1.1 285 mA V mV − − − − 6 − − − − − − − − − 7 WLL − − − OVP1 − − − − 2.5 1.5 128 1.0 100 2.8 − − − − 3.1 V ms s mV V 3 3 − − − 4 4 − − − 5 5 − − − Zin AVCL Vref − − − − 2.2 − − 50 −3.0 2.5 1.0 3.0 − − 2.8 − − kW − V V − 2 2 2 3 3 3 4 4 4 VCH VCL − − 2 2 − − 3 3 − − 4 4 − − Cpin2 − 8.0 −0.9 100 − − 100 10 −0.7 300 4.0 10 370 12 −0.5 350 8.0 − 480 ns ms pF ns Vth VH 50 − 65 30 85 − mV mV V PDIP−8 PDIP−14 SOIC−16 Symbol Min Typ Max Unit http://onsemi.com 6 NCP1205 ELECTRICAL CHARACTERISTICS (continued) (For typical values TA = 25°C, for min/max values TJ = 25°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted.) Pin No. Characteristics Current Sense Comparator (continued) Propagation Delay from Current Detection to Gate OFF State Leading Edge Blanking (LEB) Frequency Modulator Minimum Frequency Operation @ Ct = 1.0 ηF and VCC = 30 V Maximum Frequency Operation @ Ct = 1.0 ηF and VCC = 30 V Minimum Ct Charging Current (Note 4) Maximum Ct Charging Current (Note 4) Discharge Time @ Ct = 1.0 ηF Drive Output Output Voltage Rise Time @ CL = 1.0 ηF (DV = 10 V) Output Voltage Fall Time @ CL = 1.0 ηF (DV = 10 V) Clamped Output Voltage @ VCC = 30 V (Note 5) Voltage Drop on the Stage @ VCC = 10 V (Note 5) Undervoltage Lockout Startup Threshold (VCC Increasing) Minimum Operating Voltage (VCC Decreasing) Startup Current Source Maximum Voltage, Pin 1 Grounded Maximum Voltage, Pin 1 Decoupled (470 mF) Startup Current Source Flowing through Pin 1 Leakage Current in Offstate @ Vpin 1 = 500 V Device Current Consumption VCC less than UVLOH VCC = 30 V and Fsw = 2.0 kHz, CL = 1.0 ηF VCC = 30 V and Fsw = 125 kHz, CL = 1.0 ηF Startup Current to VCC Capacitor 4. Typical capacitor swing is between 0.5 V and 3.5 V. 5. Guaranteed by design, TJ = 25°C. 8 8 8 8 13 13 13 13 14 14 14 14 − − − − − − − 1.4 1.5 1.2 3.0 − 1.8 3.0 4.0 − mA mA mA mA 1 1 1 1 1 1 1 1 1 1 1 1 − − − − − − 2.3 − 450 500 3.0 32 − − 4.8 70 V V mA mA 8 8 13 13 14 14 UVLOH UVLOL 13.5 6.5 15 7.2 16.5 8.0 V V 7 7 7 12 12 12 12 12 13 13 13 12 tr tf VDRV VDRV − − 11 − 30 30 13 − 50 50 16 0.5 ns ns V V 4 4 4 4 4 5 5 5 5 5 6 6 6 6 6 Fmin Fmax ICtmin ICtmax − − 90 − 280 − 0 110 0 350 500 − 125 − 420 − kHz kHz mA mA ns 6 6 11 11 12 12 Tdel Tleb − − 200 200 250 − ns ns PDIP−8 PDIP−14 SOIC−16 Symbol Min Typ Max Unit http://onsemi.com 7 NCP1205 420 Ct CHARGING CURRENT (mA) 400 380 360 340 320 300 280 −50 0 50 TEMPERATURE (°C) 100 150 SWITCHING FREQUENCY (kHz) 125 120 115 110 105 100 95 90 −50 0 50 TEMPERATURE (°C) 100 150 Figure 5. Ct Charging Current versus Temperature Figure 6. Switching Frequency @ Ct = 1 nF versus Temperature STARTUP THRESHOLD (V) 16 15.5 15 14.5 14 13.5 −50 MAXIMUM CURRENT SET POINT (mV) 0 50 TEMPERATURE (°C) 100 16.5 1100 1050 1000 950 150 900 −50 0 50 TEMPERATURE (°C) 100 150 Figure 7. Startup Threshold versus Temperature Figure 8. Maximum Current Setpoint versus Temperature MINIMUM OPERATING VOLTAGE (V) 8 7.75 7.5 7.25 7 6.75 6.5 −50 0 50 TEMPERATURE (°C) 100 150 Figure 9. Minimum Operating Voltage versus Temperature http://onsemi.com 8 NCP1205 APPLICATION INFORMATION Introduction By implementing a unique smooth frequency reduction technique, the NCP1205 represents a major leap toward low−power Switchmode Power Supply (SMPS) integrated management. The circuit combines free−running operation with minimum drain−source switching (so−called valley switching), which naturally reduces the peak current stress as well as the ElectroMagnetic Interferences (EMI). At nominal output power, the circuit implements a traditional current−mode SMPS whose peak current setpoint is given by the feedback signal. However, rather than keeping the switching frequency constant, each cycle is initiated by the end of the primary demagnetization. The system therefore operates at the boundary between Discontinuous Conduction Mode (DCM) and Continuous Conduction Mode (CCM). Figure 10 details this terminology: IL Not 0 at Turn ON L > Lc IP 0 L = Lc L < Lc ON IL(avg) OFF Borderline 0 Before Turn ON 0 D/Fs Dead−Time Time Figure 10. Defining the Conduction Mode, Discontinuous, Continuous and Borderline When the output power demands decreases, the natural switching frequency raises. As a natural result, switching losses also increase and degrade the SMPS efficiency. To overcome this problem, the maximum switching frequency of the NCP1205 is clamped to typically 125 kHz. When the free running mode (also called Borderline Control Mode, BCM) reaches this clamp value, an internal Voltage−Controlled Oscillator (VCO) takes over and starts to decrease the switching frequency: we are in Variable Frequency Mode (VFM). Please note that during this transition phase, the peak current is not fixed but is still decreasing because the output power demand does. At a given state, the peak current reaches a minimum peak (typically 250 mV/Rsense), and cannot go further down: the switching frequency continues its decrease down to a possible minimum of 0 Hz (the IC simply stops switching). During normal free−running operation and VFM, the controller always ensures single or multiple drain−source valley switching. We will see later on how this is internally implemented. The FLYBACK operation is mainly defined through a simple formula: Pout + 1 · Lp · Ip2 · Fsw 2 (eq. 1) With: Lp the primary transformer inductance (also called the magnetizing inductance) Ip the peak current at which the MOSFET is turned off Fsw the nominal switching frequency To adjust the transmitted power, the PWM controller can play on the switching frequency or the peak current setpoint. To refine the control, the NCP1205 offers the ability to play on both parameters either altogether on an individual basis. http://onsemi.com 9 NCP1205 In order to clarify the device behavior, we can distinguish the following simplified operating phases: 1. The load is at its nominal value. The SMPS operates in borderline conduction mode and the switching frequency is imposed by the external elements (Vin, Lp, Ip, Vout). The MOSFET is turned on at the minimum drain−source level. 2. The load starts to decrease and the free−running frequency hits the internal clamp. 3. The frequency can no longer naturally increase because of the clamp. The frequency is now controlled by the internal VCO but remains constant. The peak current finds no other option that diminishing to satisfy equation (1). 4. The peak current has reached the internal minimum ceiling level and is now frozen for the remaining cycles. 5. To further reduce the transmitted power (VFB goes up), the VCO decreases the switching frequency. In case of output overshoot, the VCO could decrease the frequency down to zero. When the overshoot has gone, VFB diminishes again and the IC smoothly resumes its operation. Detailed Description The following sections describe the internal behavior of the NCP1205. Free−Running Operation As previously said, the operating frequency at nominal load is dictated by the external elements. We can split the different switching sections in two separated instants. In the following text we use the internal error voltage, Verr. This level is elaborated in Figure 13. Verr is linked to VFB (pin 4) by the following formula: Verr + 10 * 3 · VFB (eq. 2) ON time: The ON time is given by the time it takes to reach the peak current setpoint imposed by the level on FB pin (pin 4). Since this level is internally divided by three, the peak setpoint is simply: Ipk + 1 · Verr 3 · Rsense (eq. 3) The rising slope of the peak current is also dependent on the inductance value and the rectified DC input voltage by: dIL VinDC + dt Lp (eq. 4) By combining both equations, we obtain the ON time definition: ton + Lp VinDC · Ip + Lp · VERR VinDC · 3 · Rsense (eq. 5) Advantages of the Method By implementing the aforementioned control scheme, the NCP1205 brings the following advantages: • Discontinuous only operation: in DCM, the Flyback is a first order system (at low frequencies) and thus naturally eases the feedback loop compensation. • A low−cost secondary rectifier can be used due to smooth turn−off conditions. • Valley switching ensures minimum switching losses brought by Coss and all the parasitic capacitances. • By folding back the switching frequency, you turn the system into Pulse Duration Modulation. This method prevents from generating uncontrolled output ripple as with hysteretic controllers. • By letting you control the peak current value at which the frequency goes down, you ensure that this level is low enough to avoid transformer acoustic noise generation even at audible frequencies. OFF time: The time taken by the demagnetization of the transformer depends on the reset voltage applied at the switch opening. During the conduction time of the secondary diode, the primary side of the transformer undergoes a reflected voltage of: [Np/Ns . (Vf + Vout)]. This voltage applied on the primary inductance dictates the time needed to decrease from Ip down to zero: toff + Lp Np Ns · (Vout ) Vf) Lp · Verr (eq. 6) · Ip + Np Ns · (Vout ) Vf) · 3 · Rsense By adding ton + toff, we obtain the natural switching frequency of the SMPS operating in Borderline Conduction Mode (BCM): ton ) toff + Verr · Lp · 3 · Rsense 1) VinDC 1 Np Ns · (Vout ) Vf) (eq. 7) http://onsemi.com 10 NCP1205 If we now enter this formula into a spreadsheet, we can easily plot the switching frequency versus the output power demand: 250000 SWITCHING FREQUENCY (Hz) 200000 150000 100000 50000 VCO Action 0 0 5 10 OUTPUT POWER (W) 15 20 Transition BCM to VFM Fmax Fmax Figure 11. A Typical Behavior of Free Running Systems with a Smooth Frequency Foldback with the NCP1205 The typical above diagram shows how the frequency moves with the output power demand. The components used for the simulation were: Vin = 300 V, Lp = 6.5 mH, Vout = 10 V, Np/Ns = 12. The red line indicates where the maximum frequency is clamped. At this time, the VCO takes over and decreases the switching frequency to the minimum value. VCO Operation The VCO is controlled from the Verr voltage. For Verr levels above 1.0 V, the VCO frequency remains unchanged at 125 kHz. As soon as Verr starts to decrease below 1.0 V, Internal Verr the VCO frequency decreases with a typical small−signal slope of −175 kHz/mV @ Verr = 500 mV down to zero (typically at FB ≈ 3.3 V). The demagnetization synchronization is however kept when the Toff expands. The maximum switching frequency can be altered by adjusting the Ct capacitor on pin 5. The 125 kHz maximum operation ensures that the fundamental component stays external from the international EMI CISPR−22 specification beginning. The following drawing explains the philosophy behind the idea: 3V VCO Frequency is Fixed at 130 kHz BCM Mode Peak current can change 1V 0.75 V VCO Frequency can Decrease Peak Current is Fixed Figure 12. When the Power Demand goes Low, the Peak Current is Frozen and the Frequency Decreases http://onsemi.com 11 NCP1205 Zero Crossing Detector To detect the zero primary current, we make use of an auxiliary winding. By coupling this winding to the primary, we have a voltage image of the flux activity in the core. Figure 10 details the shape of the signal in BCM (L = Lc). The auxiliary winding for demagnetization needs to be wired in Forward mode. However, the application note describes an alternative solution showing how to wire the winding in Flyback as well. As Figure 13 depicts, when the MOSFET closes, the auxiliary winding delivers (Naux/Np . Vin). At the switch opening, we couple the auxiliary winding to the main output power winding and thus deliver: (−Naux/Ns . Vout). When DCM occurs, the ringing also takes place on the auxiliary winding. As soon as the level crosses−up the internal reference level (65 mV), a signal is internally sent to restart the MOSFET. Three different conditions can occur: 1. In BCM, every time the 65 mV line is crossed, the switch is immediately turned−on. By accounting for the internal Demag pin capacitance (10−15 pF typical), you can introduce a fixed delay, which, combined to the propagation delay, allows to precisely restart in the drain−source valley (minimum voltage to reduce capacitive losses). 2. When the IC enters VFM, the VCO delivers a pulse which is internally latched. As soon as the demagnetization pulse appears, the logic restarts the MOSFET. 3. As can be seen from Figure 13, the parasitic oscillations on the drain are subject to a natural damping, mainly imputed to ohmic losses. At a given point, the demag activity on the auxiliary winding becomes too low to be detected. To avoid any restart problem, the NCP1205 features an internal 4.0 ms timeout delay. This timeout runs after each demag pulse. If within 4.0 ms further to a demag pulse no activity is detected, an internal signal is combined with the VCO to actually restart the MOSFET (synchronized with Ct). Error Amplifier and Fault Detection The NCP1205 features an internal error amplifier solely used to detect an overcurrent problem. The application assumes that all the error gain associated with the precise reference level is located on the secondary side of the SMPS. Various solutions can be purposely implemented such as the TL431 or a dedicated circuit like the MC33341. In the NCP1205, the internal OPAMP is used to create a virtual ground permanently biased at 2.5 V (Figure 14), an internal reference level. By monitoring this virtual ground further called V(−), we have the possibility to confirm the good behavior of the loop. If by any mean the loop is broken (shorted optocoupler, open LED etc.) or the regulation cannot be reached (true output short−circuit), the OPAMP network is adjusted in order to no longer be able to ensure the 2.5 V virtual point V(−). If V(−) passes down the 1.5 V level (e.g. output shorted) for a time longer than 128 ms, then the pulses are stopped for 8 x 128 ms. The IC enters a kind of burst mode with bunch of pulses lasting 128 ms and repeating every 8 x 128 ms. If the loop is restored within the 8 x 128 ms period, then the pulses are back again on the output drive (synchronized with UVLOH). Drain Level Valley Switching Possible Demag 65 mV 2 0V Auxiliary Level IP = 0 4 ms Restart when Demag is too low 750.0 U 754.0 U 758.0 U 762.0 U 766.0 U Figure 13. Core Reset Detection is done through an Auxiliary Winding Operated in Forward http://onsemi.com 12 NCP1205 Monitor Rf 150 k Vfb Ri 50 k + Vfb V(−) VHIGH = 3 V VLOW = 5 mV 3 1 − + 2 2R 6 R Current Setpoint + V1 2.5 V 5 + Vlow 1.5 V + − 7 OCP Circuitry Figure 14. This Typical Arrangement Allows for an Easy Fault Detection Management To illustrate how the system reacts to a variable FB level, we have entered the above circuit into a SPICE simulator and observed the output waveforms. When FB is within regulation, the error flag is low. However, as soon as FB leaves its normal operating area, the OPAMP can no longer keep the V(−) point and either goes to the positive top or down to zero: the error flag goes high. Because of the large amount of delay necessary for this 128 ms operation, the capacitor used for the timing is Ct, connected from ground to pin 5. In normal VFM operation, this timing capacitor serves as the VCO capacitor and the error management circuit is transparent. As soon as an error is detected (error flag goes high), an internal switch routes Ct to the 128 ms generator. As a first effect, the switching frequency is no longer controlled by the VCO (if the error appears during VFM) and the system is relaxed to natural BCM. The capacitor now ramps up and down to be further divided and finally create the 128 ms delay. 6.500 Regulation Area 4.500 FB Virtual Point 2.500 1.5 V 500.0 M OCP Condition Error Flag 1.000 M 3.000 M 5.000 M 7.000 M 9.000 M Figure 15. By Monitoring the Internal Virtual Ground, the System can Detect the Presence of a Fault http://onsemi.com 13 NCP1205 As soon as the system recovers from the error, e.g. FB is back within its regulation area, the IC operation comes back to normal. To avoid any system thermal runaway, another internal 8 x 128 ms delay is combined with the previous 128 ms. It works as follows: the 128 ms delay is provided to account for any normal transients that engender a temporary loss of feedback (FB goes toward ground). However, when the 128 ms period is actually over (the feedback is definitively lost) the IC stops the output driving pulses for a typical period of 8 x 128 ms. During this mode, the rest of the functions are still activated. For instance, in lack of pulses, the self−supplied being no longer provided, the startup source turns on and off (when reaching the corresponding UVLOL and UVLOH levels), creating an hiccup waveform on the Vcc line. As soon as the feedback condition is restored, the 8 x 128 ms is interrupted and, in synchronism with the Vcc line, the IC is back to normal. The following diagrams show how this mechanism takes place when FB is down to zero (optocoupler opened) or up to Vcc (optocoupler shorted). If we assume that the error is permanently present, then a burst mode takes place with a 128/8 x 128 = 12.5% duty−cycle. The real transmitted power is thus: PoutBURST + 1 · Lp · Ip2 · Fsw · DutyBURST 2 Overvoltage Detection (OVP) On the PDIP−14 and the SOIC−16 versions, an OVP pin allows to shutdown the controller as soon as the level on this pin exceeds 2.8V, as detailed in Figure 16. In lack of switching pulses, the Vcc capacitor is no longer refreshed by the auxiliary supply and slowly discharges toward ground. When the Vcc level crosses UVLOL, a new startup sequence occurs. If the OVP has gone, the converter resumes its operation. − + Latched OVP 7 1 + 2.8 V 18 k 2k 8 OVP 2 Figure 16. In the PDIP−8 Version, the OVP Pad is not Pinned Out and is Available with PDIP−14 Devices Only Protecting Pin 1 Against Negative Spikes As any CMOS controller, NCP1205 is sensitive to negative voltages that could appear on it’s pins. To avoid any adverse latch−up of the IC, we strongly recommend inserting a 15 k resistor in series with pin 1 and the high−voltage rail, as shown in Figures 17 and 18. This 15 k resistor prevents from adversely latching the controller in case of negative spikes appearing on the bulk capacitor during the power−off sequence. Please note that this resistor does not dissipate any continuous power and can therefore be of low power type. Two 8.2 k can also be wired in series to sustain the large DC voltage present on the bulk. http://onsemi.com 14 NCP1205 VCC OVP detected on Pin 6 UVLOH UVLOL Drive Unit VCC Reaches UVLOL Figure 17. When the VCC Voltage Goes Above the Maximum Value, the Device Enters Safe Burst Mode VCC Arbitrary VCC Representation UVLOH UVLOL Drive 8 x 128 ms maximum if loop does not recover V(−) 3.5 V Loop Recovers Here 1.5 V 128 ms Figure 18. When the Internal V(−) Passes Below 1.5 V, the IC Senses a Short−Circuit Event http://onsemi.com 15 NCP1205 PACKAGE DIMENSIONS PDIP−8 N SUFFIX CASE 626−05 ISSUE L NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC −−− 10_ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC −−− 10_ 0.030 0.040 8 5 − B− 1 4 F NOTE 2 − A− L C −T− SEATING PLANE J N D K M M TA M H G 0.13 (0.005) B M PDIP−14 CASE 646−06 ISSUE P 14 8 B 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 −−− 10 _ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 −−− 10 _ 0.38 1.01 A F N −T− SEATING PLANE L C H G D 14 PL K M J M DIM A B C D F G H J K L M N 0.13 (0.005) http://onsemi.com 16 NCP1205 PACKAGE DIMENSIONS SOIC−16 D SUFFIX CASE 751B−05 ISSUE J − A− 16 9 − B− 1 8 P 8 PL 0.25 (0.010) M B S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 G F K C −T− SEATING PLANE R X 45 _ M D 16 PL M J 0.25 (0.010) TB S A S ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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