NCP12400BBEBA0DR2G

DATA SHEET www.onsemi.com Fixed Frequency Current Mode Controller for Flyback Converters NCP12400 The NCP12400 is a new fixed−frequency current−mode controller featuring the Dynamic Self−Supply. This function greatly simplifies the design of the auxiliary supply and the VCC capacitor by activating the internal startup current source to supply the controller during start−up, transients, latch, stand−by etc. This device contains a special HV detector which detects the application unplug from the ac input line and triggers the X2 discharge current. This HV structure allows the brown−out detection as well. It features a timer−based fault detection that ensures the detection of overload and an adjustable compensation to help keep the maximum power independent of the input voltage. Due to frequency foldback, the controller exhibits excellent efficiency in light load condition while still achieving very low standby power consumption. Internal frequency jittering, ramp compensation, and a versatile latch input make this controller an excellent candidate for the robust power supply designs. A dedicated Off Mode allows to reach the extremely low no load input power consumption via “sleeping” whole device and thus minimize the power consumption of the control circuitry. Features • Fixed−Frequency Current−Mode Operation 65 kHz or 100 kHz • • • • • • • • • • • • • Frequency Options Frequency Foldback then Skip Mode for Maximized Performance in Light Load and Standby Conditions Timer−Based Overload Protection with Latched (Option A) or Autorecovery (Option B) Operation High−Voltage Current Source with Brown−Out Detection and Dynamic Self−Supply, Simplifying the Design of the VCC Circuitry Frequency Modulation for Softened EMI Signature Adjustable Overpower Protection Dependant on the Mains Voltage Fault Input for Overvoltage and Over Temperature Protection VCC Operation up to 28 V, with Overvoltage Detection 300/500 mA Source/Sink Drive Peak Current Capability 4/10 ms Soft−Start Internal Thermal Shutdown No−Load Standby Power < 30 mW X2 Capacitor in EMI Filter Discharging Feature These are Pb−Free Devices SOIC−7 CASE 751U MARKING DIAGRAM 8 XXXXX ALYWG G 1 400VWXYZf = Specific Device Code (see page 2) A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) PIN CONNECTIONS 1 8 FAULT HV FB CS VCC GND DRV 4 (Top View) 5 ORDERING INFORMATION See detailed ordering and shipping information on page 44 of this data sheet. Typical Applications • • • • • Offline Adapters for Notebooks, LCD, and Printers Offline Battery Chargers Consumer Electronic Power Supplies Auxiliary/Housekeeping Power Supplies Offline Adapters for Notebooks © Semiconductor Components Industries, LLC, 2017 June, 2023 − Rev. 9 1 Publication Order Number: NCP12400/D NCP12400 TYPICAL APPLICATION SCHEMATIC Figure 1. Flyback Converter Application using the NCP12400 Table 1. OPTIONS Part NCP12400 OPN Brown Out Start − Stop OCP Fault Frozen Current Setpoint NCP12400BAHAB0DR2G 103 − 100 V Latched 300 mV NCP12400BAHBB0DR2G 111 − 103 V Latched NCP12400BBBBB2DR2G 111 − 103 V NCP12400BBHAA1DR2G Soft Start Frequency OTP/OVP No, min. 3 pulses only 4 ms 65 kHz Latched 300 mV Yes, min. 3 pulses, 800 Hz burst 4 ms 65 kHz Latched Autorecovery 150 mV Yes, min. 3 pulses, 800 Hz burst 4 ms 65 → 100 kHz Latched 111 − 103 V Autorecovery 300 mV No, min. 3 pulses only 10 ms 100 kHz Autorecovery NCP12400CAHAB0DR2G 95 − 93 V Latched 300 mV No, min. 3 pulses only 4 ms 65 kHz Latched NCP12400CBAAB0DR2G 95 − 93 V Autorecovery No No, min. 3 pulses only 4 ms 65 kHz Latched NCP12400CBBAB0DR2G 95 − 93 V Autorecovery 150 mV No, min. 3 pulses only 4 ms 65 kHz Latched NCP12400CBHAA0DR2G 95 − 93 V Autorecovery 300 mV No, min. 3 pulses only 10 ms 65 kHz Autorecovery NCP12400EAHBB0DR2G Brown In, No BO Latched 300 mV Yes, min. 3 pulses, 800 Hz burst 4 ms 65 kHz Latched NCP12400BBBBA0DR2G 111 − 103 V Autorecovery 150 mV Yes, min. 3 pulses, 800 Hz burst 10 ms 65 kHz Latched NCP12400BBHAB0DR2G 111 − 103 V Autorecovery 300 mV No, min. 3 pulses only 4 ms 65 kHz Latched NCP12400BBEBA0DR2G 111 − 103 V Autorecovery 210 mV Yes, min. 3 pulses, 800 Hz burst 10 ms 65 kHz Latched NCP12400BBAAA0DR2G 111 − 103 V Autorecovery No No 10 ms 65 kHz Autorecovery www.onsemi.com 2 Quiet skip NCP12400 Table 2. SPECIFIC DEVICE CODE KEY 400 V W X Y Z f Part BO OCP Fault Frozen Current Setpoint Quiet Skip Soft Start Frequency A − 229−211 V B − 111−103 V C − 95−93 V D − No BO E − Brown In, no BO A − Latched B − Autorecovery A −No B − 150 mV C − 170 mV D − 190 mV E − 210 mV F − 230 mV G − 250 mV H − 300 mV A − No, min. 3 pulses A − 10 ms B − 4 ms 0 − 65 kHz 1 − 100 kHz 2 − 65 → 100 kHz B − Yes, min. 3 pulses, 800 Hz burst Table 3. PIN FUNCTION DESCRIPTION Pin # Pin Name Function 1 FAULT FAULT Input 2 FB Feedback + Shutdown Pin 3 CS Current Sense 4 GND 5 DRV Drive Output 6 VCC VCC Input 8 HV High−Voltage Pin Pin Description Pull the pin up or down to stop the controller. An internal current source allows the direct connection of an NTC for over temperature detection. Device can restart in autorecovery mode or can be latched depending on the option. An optocoupler connected to ground controls the output regulation. The part goes to the low consumption Off mode if the FB input pin is pulled to GND. This input senses the primary current for current−mode operation, and offers an overpower compensation adjustment. This pin implements over voltage protection as well. The controller ground. Drives external MOSFET. This supply pin accepts up to 28 Vdc, with overvoltage detection. The pin is connected to an external auxiliary voltage. Connects to the rectified ac line to perform the functions of start−up current source, Self−Supply, brown−out detection and X2 capacitor discharge function and the HV sensing for the overpower protection purposes. It is not allowed to connect this pin to a dc voltage. www.onsemi.com 3 NCP12400 SIMPLIFIED INTERNAL BLOCK SCHEMATIC Vdd Intc Intc Vhv DC sample HV Brown _In OVP_CMP OM & X2 & Vcc TSD Set Q Rese t Qb IC startB Vcc regulator X 2 discharge 11 V regulator Vdd reg ON_CMP 10.8V 9.5V Vc cOFF SS_end UVLO Brown _Out PowerOnReset _CMP RESET Vdd VccON 7V Vcc ON RESET 12V VCC Vcc_Int UVLO_CMP Latch Dual HV start −up current source control Vc c(reg) 26V 0. 4V Votp 1. 2V 1k 300 us OTP Filter Vc cR ESET OTP_CMP 8 mA VccOVP_CMP 10 us Filter VccOVP Vc cOVP FAULT Vclamp Rc lamp AC_Off OVP 2. 5V Vov p 55 us Filter STOP_CMP VccMIN 10.5V Off_mode_CMP1 2.2V Set V on Vc cMI N 5uA VCC ICstart Q Reset Qb Off_mode_CMP2 FB 0. 6V Square output OSC 65kHz ton_max output 3. 0V freq folback PFM input CSref Saw output Ramp_OTA 4uMho Skip _CMP 1.4V FBbuffer Vramp_of fset Rfb1 Vfb(reg) FM input jittering Int ernal resit anc e 40k Voff GoToOffMode timer 500ms VCC SkipB Set IC stopB PWM Iopc = 0.5u*(Vhv −125) Soft Start timer 1uA Ilimit_CMP MAX_ton Ilimit Set Q Fault timer 0.7V Vi lim Reset Qb CSstop_CMP 1.05V VC Ss top Brown _Out TSD OVP_CMP LEB 1 us 4 events timer 1.05V Vovp 600ns timer DRV Figure 2. Simplified Internal Block Schematic www.onsemi.com 4 RESET Fault 4 events timer GND Qb Enable SS _end Vfb < 1.64 V fix current setpoint 210mV LEB 120 ns Q Lat chB SoftStart _CMP LEB 250 ns Fault B Brown_OutB Reset Vdd CS DRV PWM_CMP TSD Latch management Div ision rat io 4 Rf b3 R fb2 2. 6V V to I Vf b(opc ) Vhv DC sample Vsk ip Clamp MAX_ton IC stop Latch NCP12400 Table 4. MAXIMUM RATINGS Rating Symbol Value Unit –0.3 to 20 ±1000 (peak) V mA VCCPower Supply voltage, VCC pin, continuous voltage Power Supply voltage, VCC pin, continuous voltage (Note 2) –0.3 to 36 ±30 (peak) V mA Maximum voltage on HV pin (Dc−Current self−limited if operated within the allowed range) –0.3 to 750 ±20 V mA Vmax Maximum voltage on low power pins (except pin 5, pin 6 and pin 8) (Dc−Current self−limited if operated within the allowed range) (Note 2) –0.3 to 5.5 ±10 (peak) V mA RqJ−A Thermal Resistance SOIC−7 Junction-to-Air, low conductivity PCB (Note 3) Junction-to-Air, medium conductivity PCB (Note 4) Junction-to-Air, high conductivity PCB (Note 5) 162 147 115 RqJ−C Thermal Resistance Junction−to−Case 73 °C/W TJMAX Operating Junction Temperature −40 to +150 °C Storage Temperature Range DRV (pin 5) Maximum voltage on DRV pin (Dc−Current self−limited if operated within the allowed range) (Note 2) VCC (pin 6) HV (pin 8) TSTRGMAX °C/W −60 to +150 °C ESD Capability, HBM model (All pins except HV) (Note 1) > 4000 V ESD Capability, HBM model (pin 8, HV) > 2000 V ESD Capability, Charge Discharge Model (Note 1) > 500 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. This device series contains ESD protection and exceeds the following tests: Human Body Model 4000 V per JEDEC standard JESD22, Method A114E Charge Discharge Model Method 500 V per JEDEC standard JESD22, Method C101E 2. This device contains latch-up protection and exceeds 100 mA per JEDEC Standard JESD78. 3. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 50 mm2 of 2 oz copper traces and heat spreading area. As specified for a JEDEC 51-1 conductivity test PCB. Test conditions were under natural convection or zero air flow. 4. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 100 mm2 of 2 oz copper traces and heat spreading area. As specified for a JEDEC 51-2 conductivity test PCB. Test conditions were under natural convection or zero air flow. 5. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 650 mm2 of 2 oz copper traces and heat spreading area. As specified for a JEDEC 51-3 conductivity test PCB. Test conditions were under natural convection or zero air flow. Table 5. ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VHV = 125 V, VCC = 11 V unless otherwise noted) Symbol Min Typ Max Unit VHV(min) − 30 40 V VCC = 0 V VCC = VCC(on) − 0.5 V Istart1 Istart2 0.2 5 0.5 8 0.8 11 mA VHV = 750 V, VCC = 15 V Istart(off) − 2 6 mA Turn−on threshold level, VCC going up HV current source stop threshold (depending on the version) VCC(on) 11.0 15.0 12.0 16.2 13.0 17.5 V HV current source restart threshold VCC(min) 9.5 10.5 11.5 V Turn−off threshold VCC(off) 8.4 8.9 9.3 V Overvoltage threshold Overvoltage threshold (option EAHBB, BBBBB) VCC(ovp) 25 30 26.5 32 28 34 V tVCC(blank) − 10 − ms Characteristics Test Condition HIGH VOLTAGE CURRENT SOURCE Minimum voltage for current source operation Current flowing out of VCC pin Off−state leakage current SUPPLY Blanking duration on VCC(off) and VCC(ovp) detection 6. Guaranteed by design. 7. CS pin source current is a sum of Ibias and IOPC, thus at VHV = 125 V is observed the Ibias only, because IOPC is switched off. www.onsemi.com 5 NCP12400 Table 5. ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VHV = 125 V, VCC = 11 V unless otherwise noted) Characteristics Test Condition Symbol Min Typ Max Unit VCC(reset) 4.8 7.0 7.7 V SUPPLY VCC decreasing level at which the internal logic resets VCC level for ISTART1 to ISTART2 transition VCC(inhibit) 1.0 2.1 3.0 V DRV open, VFB = 3 V, 65 kHz DRV open, VFB = 3 V, 100 kHz ICC1 1.0 1.1 1.3 1.4 2.0 2.1 mA mA Cdrv = 1 nF, VFB = 3 V, 65 kHz Cdrv = 1 nF, VFB = 3 V, 100 kHz ICC2 1.5 2.0 2.1 2.6 2.9 3.4 mA mA Skip or before start−up ICC3 400 500 650 mA Fault mode (fault or latch) ICC4 300 430 550 mA Off−mode ICC5 − 25 − mA Brown−out thresholds (option A) VHV going up VHV going down VHV(start) VHV(stop) 210 194 229 211 248 228 V Brown−out thresholds (option B) VHV going up VHV going down VHV(start) VHV(stop) 102 94 111 103 120 116 V Brown−out thresholds (option BAHAB) VHV going up VHV going down VHV(start) VHV(stop) 93 90 103 100 113 110 V Brown−out thresholds (option C) VHV going up VHV going down VHV(start) VHV(stop) 87 85 95 93 103 101 V Brown−out thresholds (option E) VHV going up VHV(start) 90 100 110 V tHV 42 48 64 73 86 98 ms VHV(hyst) 2.0 3.0 4.0 V tsample − 1.0 − ms tDET 21 32 43 ms Internal current consumption BROWN−OUT Timer duration for line cycle drop−out (depending on the version) X2 DISCHARGE Comparator hysteresis observed at HV pin HV signal sampling period Timer duration for no line detection Discharge timer duration tDIS 21 32 43 ms VCC(dis) 10.0 11.0 12.0 V Oscillator frequency 65 kHz version Oscillator frequency 100 kHz version fOSC 61 94 65 100 69 110 kHz Maximum duty−ratio (corresponding to maximum on time at maximum switching frequency) DMAX 75 80 85 % Frequency jittering amplitude, in percentage of FOSC Ajitter ±3.0 ±4.0 ±5.0 kHz Frequency jittering modulation frequency Fjitter 85 125 165 Hz Shunt regulator voltage at VCC pin during X2 discharge event OSCILLATOR FREQUENCY FOLDBACK Feedback voltage threshold below which frequency foldback starts TJ = 25°C VFB(foldS) 2.4 2.5 2.6 V Feedback voltage threshold below which frequency foldback is complete TJ = 25°C VFB(foldE) 2.05 2.15 2.25 V VFB = Vskip(in) + 0.1 fOSC(min) 25 28 31 kHz Minimum switching frequency 6. Guaranteed by design. 7. CS pin source current is a sum of Ibias and IOPC, thus at VHV = 125 V is observed the Ibias only, because IOPC is switched off. www.onsemi.com 6 NCP12400 Table 5. ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VHV = 125 V, VCC = 11 V unless otherwise noted) Characteristics Test Condition Symbol Min Typ Max Unit Rise time, 10 to 90% of VCC VCC = VCC(off) + 0.2 V, CDRV = 1 nF trise − 40 70 ns Fall time, 90 to 10% of VCC VCC = VCC(off) + 0.2 V, CDRV = 1 nF tfall − 30 60 ns Current capability VCC = VCC(off) + 0.2 V, CDRV = 1 nF DRV high, VDRV = 0 V DRV low, VDRV = VCC OUTPUT DRIVER mA IDRV(source) IDRV(sink) − − 300 500 − − VCC = VCC(ovp) – 0.2 V, DRV high, RDRV = 33 kW, Cload = 220 pF VDRV(clamp) 10 12 14 V VCC = VCC(min) + 0.2 V, RDRV = 33 kW, DRV high VDRV(drop) − − 1 V Input Pull−up Current VCS = 0.7 V Ibias − 1 − mA Maximum internal current setpoint VFB > 3.5 V VILIM 0.66 0.70 0.74 V Propagation delay from VIlimit detection to DRV off VCS = VILIM tdelay − 50 70 ns tLEB 180 250 320 ns VCS(stop) 0.95 1.05 1.15 V tBCS 75 120 150 ns tSSTART − 3.2 10 4.0 13 4.8 ms VI(freeze) 100 140 145 250 150 190 210 300 200 240 270 350 mV VOVP(CS) 1.00 1.05 1.10 V Blanking duration on OVP detection tOVP,CS 0.7 1.0 1.3 ms Delay time constant before OTP confirmation tOVP,del − 600 − ns Scomp(65kHz) Scomp(100kHz) − − −32.5 −50 − − mV / ms RFB(up) 30 40 50 kW KFB − 4 − − VFB(ref) 4.5 5 5.5 V TJ = 25°C VFB(off) − 0.8 − V VFB going down, TJ = 25°C VFB going up, TJ = 25°C Vskip(in) Vskip(out) 0.9 1.05 1.0 1.15 1.1 1.25 V nP,skip 3 − − tskip − − 38 Clamping voltage (maximum gate voltage) High−state voltage drop CURRENT SENSE Leading Edge Blanking Duration for VILIM Threshold for immediate fault protection activation Leading Edge Blanking Duration for VCS(stop) (Note 6) Soft−start duration (option A) Soft−start duration (option B) From 1st pulse to VCS = VILIM Frozen current setpoint (option B) Frozen current setpoint (option D) Frozen current setpoint (option E) Frozen current setpoint (option H) Over voltage protection threshold when DRV is low VCS going up INTERNAL SLOPE COMPENSATION Slope of the compensation ramp FEEDBACK Internal pull−up resistor TJ = 25°C VFB to internal current setpoint division ratio (Note 6) Internal pull−up voltage on the FB pin Offset between FB pin and internal FB divider SKIP CYCLE MODE Feedback voltage thresholds for skip mode Minimum number of pulses in burst Skip out delay 6. Guaranteed by design. 7. CS pin source current is a sum of Ibias and IOPC, thus at VHV = 125 V is observed the Ibias only, because IOPC is switched off. www.onsemi.com 7 ms NCP12400 Table 5. ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VHV = 125 V, VCC = 11 V unless otherwise noted) Characteristics Test Condition Symbol Min Typ Max Unit The voltage above which the part enters the on mode VCC > VCC(off), VHV = 60 V VON − 2.2 − V The voltage below which the part enters the off mode VCC > VCC(off) VOFF 0.5 0.6 0.7 V VCC > VCC(off), VHV = 60 V VHYST 500 − − mV Pull−up current in off mode VCC > VCC(off) IOFF − 5 − mA Go To Off mode timer VCC > VCC(off) tGTOM 400 500 600 ms tfault 108 128 178 ms tfault,res 150 200 250 ms tautorec 0.85 1.00 1.35 s KOPC − 0.54 − mA / V REMOTE CONTROL ON FB PIN Minimum hysteresis between the VON and VOFF OVERLOAD PROTECTION Fault timer duration Fault timer reset time VCS < 0.7 V, D < 90% DMAX Autorecovery mode latch−off time duration OVERPOWER PROTECTION VHV to IOPC conversion ratio Current flowing out of CS pin (Note 7) VHV = 125 V VHV = 162 V VHV = 325 V VHV = 365 V IOPC(125) IOPC(162) IOPC(325) IOPC(365) − − − 105 0 20 110 130 − − − 150 mA FB voltage above which IOPC is applied VHV = 365 V VFB(OPCF) − 2.6 − V FB voltage below which is no IOPC applied VHV = 365 V VFB(OPCE) − 1.6 − V High threshold VLatch going up VOVP 2.43 2.50 2.57 V Low threshold VLatch going down, TJ = 25°C VOTP 0.380 0.400 0.420 V OTP resistance threshold (TJ = 25°C) External NTC resistance is going down ROTP 7.6 8.0 8.5 kW OTP resistance threshold (TJ = 80°C) External NTC resistance is going down ROTP − 8.5 − kW OTP resistance threshold (TJ = 110°C) External NTC resistance is going down ROTP − 9.5 − kW INTC INTC(SSTART) 30 60 50 100 70 140 INTC 47 50 53 mA Blanking duration on high latch detection tLatch(OVP) 35 50 70 ms Blanking duration on low latch detection tLatch(OTP) − 350 − ms ILatch = 0 mA ILatch = 1 mA Vclamp0(Latch) Vclamp1(Latch) 1.0 1.8 1.2 2.4 1.4 3.0 V TJ going up TTSD − 150 − °C TJ going down TTSD(HYS) − 30 − °C FAULT INPUT Current source for direct NTC connection During normal operation During soft−start VLatch = 0.2 V Current source for direct NTC connection During normal operation VLatch = 0.2 V, TJ = 25°C Clamping voltage mA TEMPERATURE SHUTDOWN Temperature shutdown Temperature shutdown hysteresis 6. Guaranteed by design. 7. CS pin source current is a sum of Ibias and IOPC, thus at VHV = 125 V is observed the Ibias only, because IOPC is switched off. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 8 NCP12400 TYPICAL CHARACTERISTIC Figure 3. Minimum Voltage for HV Current Source Operation VHV(min) Figure 4. High Voltage Startup Current Flowing Out of VCC Pin Istart1 of VCC Pin Fault/Short Figure 5. HV Pin Device Startup Threshold VHV(start) Figure 6. Off−state Leakage Current from HV Pin Istart(off) Figure 7. High Voltage Startup Current Flowing Out of VCC Pin Istart2 Figure 8. HV Pin Device Stop Threshold VHV(stop) www.onsemi.com 9 NCP12400 Figure 9. Maximum Internal Current Setpoint VILIM Figure 10. Threshold for the Very Fast Fault Protection Activation VCS(stop) Figure 11. Propagation Delay tdelay Figure 12. Frozen Current Setpoint VI(freeze) for the Light Load Operation Figure 13. Over Voltage Protection Threshold at CS Pin VOVP(CS) Figure 14. Leading Edge Blanking Duration tLEB www.onsemi.com 10 NCP12400 Figure 15. FB Pin Internal Pull−up Resistor RFB(up) Figure 16. Built in Offset between FB Pin and Internal Divider VFB(off) Figure 17. FB Pin Skip−In and Skip−Out Levels Vskip(in) and Vskip(out) Figure 18. FB Pin Open Voltage VFB(ref) Figure 19. FB Pin Frequency Foldback Thresholds VFB(foldS) and VFB(foldE) www.onsemi.com 11 NCP12400 Figure 20. Oscillator Switching Frequency fOSC Figure 21. Minimum Switching Frequency fOSC(min) Figure 22. X2 Discharge Comparator Hysteresis Observed at HV Pin VHV(hyst) Figure 23. Maximum Duty Cycle DMAX Figure 24. The Fault Timer Duration tfault Figure 25. HV Signal Sampling Period Tsample www.onsemi.com 12 NCP12400 Figure 26. VCC Turn−on Threshold Level, VCC Going Up HV Current Source Stop Threshold VCC(on) Figure 27. VCC Turn−off Threshold (UVLO) VCC(off) Figure 28. Internal Current Consumption when DRV Pin is Unloaded ICC1 Figure 29. HV Current Source Restart Threshold VCC(min) Figure 30. VCC Decreasing Level at which the Internal Logic Resets VCC(reset) Figure 31. Internal Current Consumption when DRV Pin is Loaded by 1 nF Capacitance ICC2 www.onsemi.com 13 NCP12400 Figure 32. Internal Current Consumption in Skip Mode ICC3 Figure 33. FB Pin Voltage Level Above which is Entered Normal Operating Mode VON Figure 34. Go To Off Mode Timer Duration tGTOM Figure 35. Internal Current Consumption in Off Mode ICC5 Figure 36. FB Pin Voltage Level Below which is Entered Off Mode VOFF www.onsemi.com 14 NCP12400 Figure 37. FB Pin Voltage Thresholds for Overpower Compensation Figure 38. Fault Pin High Threshold for OVP VOVP Figure 39. Current INTC Sourced Out from the Fault Pin, allowing Direct NTC Connection Figure 40. Current Flowing Out from CS Pin for Over Power Compensation @ 365 V at HV Pin IOPC(365) NOTE: The OTP resistance maximum and minimum courses are not the guaranteed limits, but the maximum and minimum measured data values from the device characterization. Figure 41. Fault Pin Low Threshold for OTP VOTP Figure 42. The OTP Resistance Threshold ROTP www.onsemi.com 15 NCP12400 APPLICATION INFORMATION Functional Description For loads that are between approximately 32% and 10% of full rated power, the converter operates in frequency foldback mode (FFM). If the feedback pin voltage is lower than 1.4 V the peak switch current is kept constant and the output voltage is regulated by modulating the switching frequency for a given and fixed input voltage VHV. Effectively, operation in FFM results in the application of constant volt−seconds to the flyback transformer each switching cycle. Voltage regulation in FFM is achieved by varying the switching frequency in the range from 65 kHz to 28 kHz. For extremely light loads (below approximately 6% full rated power), the converter is controlled using bursts of 28 kHz pulses. This mode is known as skip mode. The FFM, keeping constant peak current and skip mode allows design of the power supplies with increased efficiency under the light loading conditions. Keep in mind that the aforementioned boundaries of steady−state operation are approximate because they are subject to converter design parameters. The NCP12400 includes all necessary features to build a safe and efficient power supply based on a fixed−frequency flyback converter. The NCP12400 is a multimode controller as illustrated in Figure 43. The mode of operation depends upon line and load condition. Under all modes of operation, the NCP12400 terminates the DRV signal based on the switch current. Thus, the NCP12400 always operates in current mode control so that the power MOSFET current is always limited. Under normal operating conditions, the FB pin commands the operating mode of the NCP12400 at the voltage thresholds shown in Figure 43. At normal rated operating loads (from 100% to approximately 33% full rated power) the NCP12400 controls the converter in a fixed−frequency PWM mode. It can operate in the continuous conduction mode (CCM) or discontinuous conduction mode (DCM) depending upon the input voltage and loading conditions. If the controller is used in CCM with a wide input voltage range, the duty−ratio may increase up to 50%. The build−in slope compensation prevents the appearance of sub−harmonic oscillations in this operating area. Low consumption off mode ON OFF 0V VOFF Vskip(in) PWM at f OSC FFM Skip mode Vskip(out) VFB(foldE) VON VFB(foldS) VFBilim V FB Figure 43. Mode Control with FB Pin Voltage decreases below the 0.6 V the controller will enter the low consumption off mode. The controller can start if the FB pin voltage increases above the 2.2 V level. See the detailed status diagrams for the both versions fully latched A and the autorecovery B on the following figures. The basic status of the device after wake–up by the VCC is the off mode and mode is used for the overheating protection mode if the thermal shutdown protection is activated. There was implemented the low consumption off mode allowing to reach extremely low no load input power. This mode is controlled by the FB pin and allows the remote control (or secondary side control) of the power supply shut−down. Most of the device internal circuitry is unbiased in the low consumption off mode. Only the FB pin control circuitry and X2 cap discharging circuitry is operating in the low consumption off mode. If the voltage at feedback pin www.onsemi.com 16 NCP12400 Off Mode Latch =X AutoRec =X V FB >V ON Check Latch =X AutoRec = X V HV >V HV (min ) No AC X2 cap Discharge Latch = 0 AutoRec =0 Latch *AutoRec BO +TSD Reset Latch =0 AutoRec =0 BO Latch Latch =1 BO+TSD Stop BO Autorecovery Latch AutoRec =1 V CSstop SSend Skip in Running Skip out delay Skip mode Skip in V CC fault Dynamic Self−Supply Soft Start Efficient operating mode (V CC >V CCon )*BO V CC >V CCoff V CC V CCoff ) V CC < V CCreset Power On Reset BO LatchCondition AutoRec = (V CSstop *4clk ) + ( V ILIM+ MaxDC )*t fault + ( V CC < V CCoff )* t VCC (blank ) = OVP + OTP + V CCovp *t VCC (blank) Conditions for Autorecovery version (B) LatchCondition AutorecoveryCondition www.onsemi.com Extra Low Consumption V CC < V CCreset Latch = 0 AutoRec =0 Dynamic Self−Supply Conditions for Latched version (A) LatchCondition = OVP + OTP + V CCovp *t VCC (blank ) + ( VCSstop *4clk ) + ( V ILIM +MaxDC )*t fault Figure 44. Operating Status Diagram of the Device NCP12400 VCC VCC(on) VCC(dis) VCC(min) VCC(off) VCC(inhibit) HV current source= Istart1 HV current source= Istart2 Before start Normal mode Overload UVLO level VCC(off) is trigged before OCP timer elapsed tautorec Fault mode Low consumption off mode X2 discharge time Figure 45. VCC Management Timing Diagram Start−up of the Controller The information about the fault (permanent Latch or Autorecovery) is kept during the low consumption off mode due the safety reason. The reason is not to allow unlatch the device by the remote control being in off mode. At start−up, the current source turns on when the voltage on the HV pin is higher than VHV(min), and turns off when VCC reaches VCC(on), then turns on again when VCC reaches www.onsemi.com 18 NCP12400 the die would be too much. As a result, an auxiliary voltage source is needed to supply VCC during normal operation. The Dynamic Self−Supply is useful to keep the controller alive when no switching pulses are delivered, e.g. in brown−out condition, or to prevent the controller from stopping during load transients when the VCC might drop. The NCP12400 accepts a supply voltage as high as 28 V, with an overvoltage threshold VCC(ovp) that latches the controller off. VCC(min), until the input voltage is high enough to ensure a proper start−up, i.e. when VHV reaches VHV(start). The controller actually starts the next time VCC reaches VCC(on). The controller then delivers pulses, starting with a soft−start period tSSTART during which the peak current linearly increases before the current−mode control takes over. Even though the Dynamic Self−Supply is able to maintain the VCC voltage between VCC(on) and VCC(min) by turning the HV start−up current source on and off, it can only be used in light load condition, otherwise the power dissipation on VHV V HV(start) V HV(min) Waits next VCC(on) before starting time VCC V CC(on) V CC(min) HV current source = I start1 HV current source = Istart2 V CC(inhibit) time DRV Figure 46. VCC Start−up Timing Diagram time controller). There is only one condition for which the current source doesn’t turn on when VCC reaches VCC(inhibit): the voltage on HV pin is too low (below VHV(min)). For safety reasons, the start−up current is lowered when VCC is below VCC(inhibit), to reduce the power dissipation in case the VCC pin is shorted to GND (in case of VCC capacitor failure, or external pull−down on VCC to disable the www.onsemi.com 19 NCP12400 V HV V HV(start) VHV(min) Device starts at V CC (on) event time V CC V CC(on) V CC(min) V CC(off) HV current source = I start1 HV current source = I start2 UVLO level V CC (off ) is trigged before OCP timer elapsed V CC(inhibit) time DRV Device stops thanks to pre−short protection time Figure 47. Latch After the Preshort HV Sensing of Rectified AC Voltage thresholds are fixed, but they are designed to fit most of the standard ac−dc conversion applications. When the input voltage goes below VHV(stop), a brown−out condition is detected, and the controller stops. The HV current source maintains VCC between VCC(on) and VCC(min) levels until the input voltage is back above VHV(start). The NCP12400 features on its HV pin a true ac line monitoring circuitry. It includes a minimum start−up threshold and an autorecovery brown−out protection; both of them independent of the ripple on the input voltage. It is allowed only to work with an unfiltered, rectified ac input to ensure the X2 capacitor discharge function as well, which is described in following. The brown−out protection www.onsemi.com 20 NCP12400 HV timer elapsed VHV VHV (start ) V HV(stop ) time HV stop tHV Brown−out detected Waits next VccON before starting V CC time V CC(on) V CC(min) DRV Brown−out condition resets the Internal Latch time time Figure 48. Ac Line Drop−out Timing Diagram drop−out. The device restart after the ac line voltage drop−out is protected to the parasitic restart initiated e.g. the spikes induced at HV pin immediately after the device is stopped by the residual energy in the EMI filter. The device restart is allowed only after the 1st watch dog signal event. The basic principle is shown at Figure 49 and detail of the device restart is shown at Figure 50. When VHV crosses the VHV(start) threshold, the controller can start immediately. When it crosses VHV(stop), it triggers a timer of duration tHV, this ensures that the controller doesn’t stop in case of line cycle drop−out. When VHV crosses the VHV(start) threshold, the controller starts when the VCC crosses the next VCC(on) event. When it crosses VHV(stop), it triggers a timer of duration tHV, this ensures that the controller doesn’t stop in case of line cycle www.onsemi.com 21 NCP12400 HV timer elapsed VHV VHV(start) V HV(stop) Spike induced by residual energy in EMI filter HV stop tHV time Brown−out detected Waits next VccON before starting VCC time V CC(on) V CC(min) DRV Brown−out condition resets the Internal Latch time time Figure 49. Ac Line Drop−out Timing Diagram with the Parasitic Spike www.onsemi.com 22 NCP12400 V HV SAMPLE TSAMPLE V HV ( start ) V HV ( stop ) V HV (hyst ) st 1 HV edge resets the watch dog and starts the peak detection of HV pin signal Comparator Output time time Sample clock time nd 2 sample clock pulse after last HV edge initiates the watch dog signal Watch dog signal 2 nd sample clock pulse after last HV edge initiates the watch dog signal time HV stop tHV Device can restart after 1 st Watch dog signal when HV signal crosses V HV(start ) level Brown−out detected time VCC VCC (on ) V CC(mini) time DRV Device is stopped Device restarts time Figure 50. Detailed Timing Diagram of the Device Restart after the Short ac Line Drop−out www.onsemi.com 23 NCP12400 X2 Cap Discharge Feature In case of the dc signal presence on the high voltage input, the direct sample of the high voltage obtained via the high voltage sensing structure and the delayed sample of the high voltage are equivalent and the comparator produces the low level signal during the presence of this signal. No edges are present at the output of the comparator, that’s why the detection timer is not reset and dc detect signal appears. The minimum detectable slope by this ac detector is given by the ration between the maximum hysteresis observed at HV pin VHV(hyst),max and the sampling time: The X2 capacitor discharging feature is offered by usage of the NCP12400. This feature save approx. 16 mW – 25 mW input power depending on the EMI filter X2 capacitors volume and it saves the external components count as well. The discharge feature is ensured via the start−up current source with a dedicated control circuitry for this function. The X2 capacitors are being discharged by current defined as Istart2 when this need is detected. There is used a dedicated structure called ac line unplug detector inside the X2 capacitor discharge control circuitry. See the Figure 51 for the block diagram for this structure and Figures 52, 53, 54 and 55 for the timing diagrams. The basic idea of ac line unplug detector lies in comparison of the direct sample of the high voltage obtained via the high voltage sensing structure with the delayed sample of the high voltage. The delayed signal is created by the sample & hold structure. The comparator used for the comparison of these signals is without hysteresis inside. The resolution between the slopes of the ac signal and dc signal is defined by the sampling time TSAMPLE and additional internal offset NOS. These parameters ensure the noise immunity as well. The additional offset is added to the picture of the sampled HV signal and its analog sum is stored in the C1 storage capacitor. If the voltage level of the HV sensing structure output crosses this level the comparator CMP output signal resets the detection timer and no dc signal is detected. The additional offset NOS can be measured as the VHV(hyst) on the HV pin. If the comparator output produces pulses it means that the slope of input signal is higher than set resolution level and the slope is positive. If the comparator output produces the low level it means that the slope of input signal is lower than set resolution level or the slope is negative. There is used the detection timer which is reset by any edge of the comparator output. It means if no edge comes before the timer elapses there is present only dc signal or signal with the small ac ripple at the HV pin. This type of the ac detector detects only the positive slope, which fulfils the requirements for the ac line presence detection. S min + V HV(hyst),max (eq. 1) T sample Than it can be derived the relationship between the minimum detectable slope and the amplitude and frequency of the sinusoidal input voltage: V max + V HV(hyst),max 2 @ p @ f @ T sample + 22.7 V + 5 2 @ p @ 35 @ 1 @ 10 −3 + (eq. 2) The minimum detectable AC RMS voltage is 16 V at frequency 35 Hz, if the maximum hysteresis is 5 V and sampling time is 1 ms. The X2 capacitor discharge feature is available in any controller operation mode to ensure this safety feature. The detection timer is reused for the time limiting of the discharge phase, to protect the device against overheating. The discharging process is cyclic and continues until the ac line is detected again or the voltage across the X2 capacitor is lower than VHV(min). This feature ensures to discharge quite big X2 capacitors used in the input line filter to the safe level. It is important to note that it is not allowed to connect HV pin to any dc voltage due this feature. e.g. directly to bulk capacitor. During the HV sensing or X2 cap discharging the VCC net is kept above the VCC(off) voltage by the Self−Supply in any mode of device operation to supply the control circuitry. During the discharge sequence is not allowed to start−up the device. www.onsemi.com 24 NCP12400 Figure 51. The ac Line Unplug Detector Structure Used for X2 Capacitor Discharge System Figure 52. The ac Line Unplug Detector Timing Diagram www.onsemi.com 25 NCP12400 Figure 53. The ac Line Unplug Detector Timing Diagram Detail with Noise Effects www.onsemi.com 26 NCP12400 VHV VHV(start) VHV(stop) Starts only at VCC(on) AC line unplug X2 capacitor discharge time HV timer starts AC line Unplug detector starts HV timer restarts No AC detection One Shot tHV t DET time DRV Brown−out X2 discharge time X2 discharge current t DIS time VCC VCC(on) VCC(dis) VCC(min) time Figure 54. HV Pin ac Input Timing Diagram with X2 Capacitor Discharge Sequence when the Application is Unplugged Under Extremely Low Line Condition www.onsemi.com 27 NCP12400 VHV X2 capacitor discharge X2 capacitor discharge AC line unplug VHV(start) VHV(stop) tHV Starts only at VCC(on) HV timer starts HV timer restarts time AC line Unplug detector starts No AC detection One Shot tDET tDET time DRV Device is stopped X2 discharge X2 discharge time X2 discharge current t DIS tDIS time VCC VCC(dis) Device shunts the X2 discharge current internally time Figure 55. HV Pin ac Input Timing Diagram with X2 Capacitor Discharge Sequence When the Application is Unplugged Under High Line Condition The Low Consumption Off Mode Only the X2 cap discharge and Self−Supply features is enabled in the low consumption off mode. The X2 cap discharging feature is enable due the safety reasons and the Self−Supply is enabled to keep the VCC supply, but only very low VCC consumption appears in this mode. Any other features are disabled in this mode. The information about the latch status of the device is kept in the low consumption off mode and this mode is used for the TSD protection as well. The protection timer GoToOffMode tGTOM is used to protect the application against the false activation of the low consumption off mode by the fast drop outs of the FB pin voltage below the 0.4 V level. E.g. in case when is present high FB pin voltage ripple during the skip mode. There was implemented the low consumption off mode allowing to reach extremely low no load input power as described in previous chapters. If the voltage at feedback pin decreases below the 0.6 V the controller enters the off mode. The internal VCC is turned−off, the IC consumes extremely low VCC current and only the voltage at external VCC capacitor is maintained by the Dynamic Self−Supply circuit. The Dynamic Self−Supply circuit keeps the VCC voltage between the VCC(on) and VCC(off) levels. The supply for the FB pin watch dog circuitry and FB pin bias is provided via the low consumption current sources from the external VCC capacitor. The controller can only start, if the FB pin voltage increases above the 2.2 V level. See Figure 56 for timing diagrams. www.onsemi.com 28 NCP12400 VHV VHV(start) VFB DRV start condition AC line unplug X2 capacitor discharge X2 capacitor discharge time Low consumption mode Low consumption off mode VON Ready to RUN tGTSG VOFF VCC VCC(on) VCC(dis) VCC(off) Starts only at VCC(on) DSS start to charge the Vcc cap Dynamic Self−Supply in off mode RUN VCC(inhibit) One Shot HV timer starts AC line Unplug detector starts HV timer restarts No AC detection time No AC detection tDET tDET time DRV Skip mode X2 cyclic discharge process starts X2 discharge current time tDIS tDIS time Figure 56. Start−up, Shut−down and AC Line Unplug Time Diagram Oscillator with Frequency Jittering fOSC The NCP12400 includes an oscillator that sets the switching frequency 65 kHz or 100 kHz depending on the version. The maximum duty−ratio of the DRV pin is 80%. In order to improve the EMI signature, the switching frequency jitters ±4 kHz around its nominal value, with a triangle−wave shape and at a frequency of 125 Hz. This frequency jittering is active even when the frequency is decreased to improve the efficiency in light load condition. f OSC + 4 kHz Nominal f OSC fOSC − 4 kHz 8 ms (125 Hz) Time Figure 57. Frequency Modulation of the Maximum Switching Frequency www.onsemi.com 29 NCP12400 Low Load Operation Modes: Frequency Foldback Mode (FFM) and Skip Mode frequency foldback mode to provide the natural transformer core anti−saturation protection. The frequency jittering is still active while the oscillator frequency decreases as well. The current setpoint is fixed to 300 mV in the frequency foldback mode if the feedback voltage decreases below the Vfb(freeze) level. This feature increases efficiency under the light loads conditions as well. In order to improve the efficiency in light load conditions, the frequency of the internal oscillator is linearly reduced from its nominal value down to fOSC(min). This frequency foldback starts when the voltage on FB pin goes below Vfb(foldS), and is complete when Vfb reaches Vfb(foldE). The maximum on−time duration control is kept during the Fsw Fixed I peak f OSC Skip f OSC(min) FB V skip(in) VFB(foldE) VFB(freeze) VFB(foldS) Voffset + K FB X V ILIM V skip(out) Figure 58. Frequency Foldback Mode Characteristic Internal current setpoint VILIM Fixed I peak V I(freeze) VFB V skip(in) VFB(foldE) VFB(freeze) VFB(foldS) K FB X V ILIM V skip(out) Figure 59. Current Setpoint Dependency on the Feedback Pin Voltage When the FB voltage reaches Vskip(in) while decreasing, skip mode is activated: the driver stops, and the internal consumption of the controller is decreased. While VFB is below Vskip(out), the controller remains in this state; but as soon as VFB crosses the skip out threshold, the DRV pin starts to pulse again. The NCP12400 device includes logic which allows going into skip mode after the DRV cycle is finished by reaching of the peak current value. This technique eliminates the last short pulses in skip mode, which increases the system efficiency at light loads and makes easier the application of active secondary rectification circuitry. www.onsemi.com 30 NCP12400 Figure 60. Skip Mode Timing Diagram FB Vskip(out) Vskip(in) time OSC (internal signal) time CS Skip signal does not immediately stop the pulse Enters skip VI(freeze) time Figure 61. Technique Preventing Short Pulses in Skip Mode www.onsemi.com 31 NCP12400 Quiet−Skip drive pulses have been counted (if not, they do not stop until the end of the nP,skip −th pulse). They are not allowed to start again until the timer expires, even if the skip−exit threshold is reached first. It is important to note that the timer will not force the next cycle to begin – i.e. if the natural skip frequency is such that skip−exit is reached after the timer expires, the drive pulses will wait for the skip−exit threshold. This means that during no−load, there will be a minimum of nP,skip drive pulses, and the burst−cycle period will likely be much longer than 1250 ms. This operation helps to improve efficiency at no−load conditions. In order to exit burst mode, the FB voltage must rise higher than Vskip(tran) level. If this occurs before tquiet expires, the drive pulses will resume immediately – i.e. the controller won’t wait for the timer to expire. Figure 63 provides an example of how Quiet−Skip works, while Figure 62 shows the immediate leaving the quiet skip mode by crossing the transient enhancement level Vskip(tran). To further avoid acoustic noise, the circuit prevents the burst frequency during skip mode from entering the audible range by limiting it to a maximum of 800 Hz. This is achieved via a timer tquiet that is activated during Quiet−Skip. The start of the next burst cycle is prevented until this timer has expired. As the output power decreases, the switching frequency decreases. Once it hits minimum switching frequency fOSC(min), the skip−in threshold is reached and burst mode is entered − switching stops as soon as the current drive pulses ends – it does not stop immediately. Once switching stops, FB will rise. As soon as FB crosses the skip−exit threshold, drive pulses will resume, but the controller remains in burst mode. At this point, a 1250 ms (typ) timer tquiet is started together with a count to nP,skip pulses counter. This nP,skip pulses counter ensures the minimum number of DRV signal pulses in burst. The next time the FB voltage drops below the skip−in threshold, DRV pulses stop at the end of the current pulse as long as nP,skip www.onsemi.com 32 NCP12400 VFB Vskip(tran) Crossing the transient enhancement level stops the quiet skip immediately Vskip(out) Vskip(in) Exits skip after quiet timer expires DRV Time t quiet t quiet Enters skip Enters skip Time Figure 62. Leaving the Quiet−Skip Mode during Load Transient V FB Vskip(out) Vskip(in) V FB Vskip(out) Vskip(in) DRV time Running just above skip mode with f sw = f osc(min) DRV Sequence of events 1 ; 2 ; 3 starts the quiet skip mode 2 1 The DRV pulses does not start even when V FB > Vskip(out) in the quiet skip mode time 3 t quiet n P,skip time t quiet n P,skip When V FB >V skip (tran ) the quiet skip mode immediately finishes V FB Vskip(tran) time V skip(out) Vskip(in) DRV n P,skip n P,skip Quiet skip mode forces at least n p,skip pulses in skip mode burst tquiet tquiet time n P,skip DRV pulses does not start because V FB < V skip (in ) time Figure 63. Quiet−Skip Timing Diagram − option www.onsemi.com 33 NCP12400 Clamped Driver voltage subducted by offset typically 0.8 V and divided by 4 sets the threshold: when the voltage ramp reaches this threshold, the output driver is turned off. The maximum value for the current sense is 0.7 V, and it is set by a dedicated comparator. Each time the controller is starting, i.e. the controller was off and starts – or restarts – when VCC reaches VCC(on), a soft−start is applied: the current sense set−point is increased by 32 discrete steps from 0 (the minimum level can be higher than 0 because of the LEB and propagation delay) until it reaches VILIM (after a duration of tSSTART), or until the FB loop imposes a setpoint lower than the one imposed by the soft−start (the 2 comparators outputs are OR’ed). During the soft−start the oscillator frequency increase from the minimum switching frequency to the maximum switching frequency following the ramp applied to current sense set−point. The supply voltage for the NCP12400 can be as high as 36 V, but most of the MOSFETs that will be connected to the DRV pin cannot accept more than 20 V on their gate. The driver pin is therefore safely clamped below 16 V. This driver has a typical capability of 500 mA for source current and 800 mA for sink current. Current−Mode Control With Slope Compensation and Soft−Start NCP12400 is a current−mode controller, which means that the FB voltage sets the peak current flowing in the transformer primary inductance and the MOSFET. This is done through a PWM comparator: the current is sensed across a resistor and the resulting voltage is applied to the CS pin. It is applied to one input of the PWM comparator through a 250 ns LEB block. On the other input the FB VFB KFB x V ILIM Time Soft−start ramp Soft−start ramp V FB takes over soft −start VILIM VILIM tSSTART Time OSC frequency CS Setpoint tSSTART Time fSW V ILIM fSW ,min Time Figure 64. Soft−Start Feature www.onsemi.com 34 t SSTART Time NCP12400 toggles, the controller immediately enters the protection mode. In order to allow the NCP12400 to operate in CCM with a duty−ratio above 50%, the fixed slope compensation is internally applied to the current−mode control. The slope appearing on the internal voltage setpoint for the PWM comparator is −32.5 mV/ms typical. The slope compensation can be observable as a value of the peak current at CS pin. The internal slope compensation circuitry uses a saw−tooth signal synchronized with the internal oscillator is subtracted from the FB voltage divided by KFB. Under some conditions, like a winding short−circuit for instance, not all the energy stored during the on−time is transferred to the output during the off−time, even if the on−time duration is at its minimum (imposed by the propagation delay of the detector added to the LEB duration). As a result, the current sense voltage keeps on increasing above VILIM, because the controller is blind during the LEB blanking time. Dangerously high current can grow in the system if nothing is done to stop the controller. That’s what the additional comparator, that senses when the current sense voltage on CS pin reaches VCS(stop) ( = 1.5 x VILIM ), does: as soon as this comparator Figure 65. Slope Compensation Block Diagram Internal PWM setpoint VFB / KFB VFB / KFB − 0.2 V 0% 40% 80% 100% Figure 66. Slope Compensation Timing Diagram www.onsemi.com 35 Duty Cycle NCP12400 Internal Overpower Protection Unfortunately, due to the inherent propagation delay of the logic, the actual peak current is higher at high input voltage than at low input voltage, leading to a significant difference in the maximum output power delivered by the power supply. The power delivered by a flyback power supply is proportional to the square of the peak current in discontinuous conduction mode: P OUT + 1 @ h @ L P @ F SW @ I P 2 2 (eq. 3) Ipeak DIpeak to be compensated I LIMIT High Line Low Line time tdelay tdelay Figure 67. Needs for Line Compensation For True Overpower Protection But this offset is unwanted to appear when the current sense signal is small, i.e. in light load conditions, where it would be in the same order of magnitude. Therefore the compensation current is only added when the FB voltage is higher than VFB(OPCE). However, because the HV pin is being connected to ac voltage, there is needed an additional circuitry to read or at least closely estimate the actual voltage on the bulk capacitor. To compensate this and have an accurate overpower protection, an offset proportional to the input voltage is added on the CS signal by turning on an internal current source: by adding an external resistor in series between the sense resistor and the CS pin, a voltage offset is created across it by the current. The compensation can be adjusted by changing the value of the resistor. I OPC VHV V FB(OPCE) V FB VFB(OPCF) Figure 68. Overpower Protection Current Relation to Feedback Voltage I OPC I OPC(365) I OPC(125) 365 V 125 V V HV Figure 69. Overpower Protection Current Relation to Peak of Rectified Input Line AC voltage www.onsemi.com 36 NCP12400 Figure 70. Block Schematic of Overpower Protection Circuit can deliver, and the CS set−point reaches VILIM. When this event occurs, an internal tfault timer is started: once the timer times out, DRV pulses are stopped and the controller is either latched off. This latch is released in autorecovery mode. The controller tries to restart after tautorec. The other possibilities of the latch release are the brown−out condition or the VCC power on reset. The timer is reset when the CS set−point goes back below VILIM before the timer elapses. The fault timer is also started if the driver signal is reset by the maximum on time. The controller also enters the same protection mode if the voltage on the CS pin reaches 1.5 times the maximum internal set−point VCS(stop) (allows to detect winding short−circuits) or there appears low VCC supply. See Figure 71 for the timing diagram. A 5−bit A/D converter with the peak detector senses the ac input, and its output is periodically sampled and reset, in order to follow closely the input voltage variations. The sample and reset events are given by the output from the ac line unplug detector. The sensed HV pin voltage peak value is validated when no HV edges from comparator are present after last falling edge during 2 sample clocks. See Figure 71 for details. Overcurrent Protection with Fault Timer The overload protection depends only on the current sensing signal, making it able to work with any transformer, even with very poor coupling or high leakage inductance. When an overcurrent occurs on the output of the power supply, the FB loop asks for more power than the controller www.onsemi.com 37 NCP12400 Figure 71. Overpower Compensation Timing Diagram www.onsemi.com 38 NCP12400 Table 6. PROTECTION MODES AND THE LATCH MODE RELEASES Event Timer Protection Next Device Status Release to Normal Operation Mode Overcurrent VCS > VILIM Fault timer Latch Autorecovery Brown−out VCC < VCC(reset) Maximum on time Fault timer Latch Brown−out VCC < VCC(reset) Maximum duty cycle Fault timer Latch Brown−out VCC < VCC(reset) Winding short VCS > VCS(stop) 4 consecutive pulses Latch Autorecovery Brown−out VCC < VCC(reset) Low supply VCC < VCC(off) 10 ms timer Latch Autorecovery Brown−out VCC < VCC(reset) External OTP, OVP 55 ms Latch Brown−out VCC < VCC(reset) High supply VCC > VCC(ovp) 10 ms timer Latch Brown−out VCC < VCC(reset) Brown−out VHV < VHV(stop) HV timer Device stops (VHV > VHV(start)) & (VCC > VCC(on)) Internal TSD 10 ms timer Device stops, HV start−up current source stops (VHV > VHV(start)) & (VCC > VCC(on)) & TSDb Off mode VFB < VOFF 500 ms timer Device stops and internal VCC is turned off (VHV > VHV(start)) & (VCC > VCC(on)) & (VFB > VON) www.onsemi.com 39 NCP12400 VCC(on) VCC(min) Figure 72. Latched Timer−Based Overcurrent Protection www.onsemi.com 40 NCP12400 Output Load Fault disappears Overcurrent applied Max Load time Fault Flag Fault timer starts time V CC V CC (on ) V CC ( min ) Restart At V CC ON (new burst cycle if Fault still present) DRV time Controller stops time Fault timer tfault t fault t autorec Figure 73. Timer−based Protection Mode with Autorecovery Release from Latch−off www.onsemi.com 41 time NCP12400 FAULT Input Figure 74. OVP/OTP Detection Schematic The FAULT input pin is dedicated to the latch−off function: it includes 2 levels of detection that define a working window, between a high latch and a low latch: within these 2 thresholds, the controller is allowed to run, but as soon as either the low or the high threshold is crossed, the controller is latched off. The controller can be released from the latch mode by the autorecovery, but it depends on the version of the product. The lower threshold is intended to be used with an NTC thermistor, thanks to an internal current source INTC. An active clamp prevents the voltage from reaching the high threshold if it is only pulled up by the INTC current. To reach the high threshold, the pull−up current has to be higher than the pull−down capability of the clamp (typically 1.5 mA at VOVP). To avoid any false triggering, spikes shorter than 50 ms (for the high latch and 65 kHz version) or 350 ms (for the low latch) are blanked and only longer signals can actually latch the controller. C FAULT max + t SSTART Reset occurs when a brown−out condition is detected or the VCC is cycled down to a reset voltage, which in a real application can only happen if the power supply is unplugged from the ac line. Upon startup, the internal references take some time before being at their nominal values; so one of the comparators could toggle even if it should not. Therefore the internal logic does not take the latch signal into account before the controller is ready to start: once VCC reaches VCC(on), the latch pin High latch state is taken into account and the DRV switching starts only if it is allowed; whereas the Low latch (typically sensing an over temperature) is taken into account only after the soft−start is finished. In addition, the NTC current is doubled to INTC(SSTART) during the soft−start period, to speed up the charging of the FAULT pin capacitor The maximum value of FAULT pin capacitor is given by the following formula (The standard start−up condition is considered and the NTC current is neglected): min @ I NTC(SSTART) min V OTP max + 3.2 @ 10 −3 @ 60 @ 10 −6 F + 457 nF 0.420 www.onsemi.com 42 (eq. 4) NCP12400 VCC(on) VCC(min) Figure 75. Latch Timing Diagram Temperature Shutdown low power consumption. There is kept the VCC supply to keep the TSD information. When the temperature falls below the low threshold, the start−up of the device is enabled again, and a regular start−up sequence takes place. See the status diagrams at the Figure 44. The NCP12400 includes a temperature shutdown protection with a trip point typically at 150°C and the typical hysteresis of 30°C. When the temperature rises above the high threshold, the controller stops switching instantaneously, and goes to the off mode with extremely www.onsemi.com 43 NCP12400 ORDERING INFORMATION Ordering Part No. Overload Protection Switching Frequency NCP12400BAHAB0DR2G Latched 65 kHz NCP12400BAHBB0DR2G Latched 65 kHz NCP12400BBBBB2DR2G Autorecovery 65 → 100 kHz NCP12400BBHAA1DR2G Autorecovery 100 kHz NCP12400CAHAB0DR2G Latched 65 kHz NCP12400CBAAB0DR2G Autorecovery 65 kHz NCP12400CBBAB0DR2G Autorecovery 65 kHz NCP12400CBHAA0DR2G Autorecovery 65 kHz NCP12400EAHBB0DR2G Latched 65 kHz NCP12400BBBBA0DR2G Autorecovery 65 kHz NCP12400BBHAB0DR2G Autorecovery 65 kHz NCP12400BBEBA0DR2G Autorecovery 65 kHz NCP12400BBAAA0DR2G Autorecovery 65 kHz Package Shipping† SOIC−7 (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 44 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−7 CASE 751U ISSUE E SCALE 1:1 DATE 20 OCT 2009 −A− 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B ARE DATUMS AND T IS A DATUM SURFACE. 4. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 5. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5 −B− S 0.25 (0.010) B M M 1 4 G C R X 45 _ J −T− SEATING PLANE H 0.25 (0.010) K M D 7 PL M T B S A DIM A B C D G H J K M N S INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 S GENERIC MARKING DIAGRAM SOLDERING FOOTPRINT* 8 1.52 0.060 7.0 0.275 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 1 XXX A L Y W G 4.0 0.155 0.6 0.024 = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 XXXXX ALYWX G mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the onsemi Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98AON12199D SOIC−7 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2023 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−7 CASE 751U ISSUE E STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. 7. NOT USED 8. EMITTER DATE 20 OCT 2009 STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. NOT USED 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. NOT USED 8. SOURCE, #1 STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. 6. 7. NOT USED 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. 7. NOT USED 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. NOT USED 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR (DIE 1) 2. BASE (DIE 1) 3. BASE (DIE 2) 4. COLLECTOR (DIE 2) 5. COLLECTOR (DIE 2) 6. EMITTER (DIE 2) 7. NOT USED 8. COLLECTOR (DIE 1) STYLE 9: PIN 1. EMITTER (COMMON) 2. COLLECTOR (DIE 1) 3. COLLECTOR (DIE 2) 4. EMITTER (COMMON) 5. EMITTER (COMMON) 6. BASE (DIE 2) 7. NOT USED 8. EMITTER (COMMON) STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. NOT USED 8. GROUND STYLE 11: PIN 1. SOURCE (DIE 1) 2. GATE (DIE 1) 3. SOURCE (DIE 2) 4. GATE (DIE 2) 5. DRAIN (DIE 2) 6. DRAIN (DIE 2) 7. NOT USED 8. DRAIN (DIE 1) STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. NOT USED 8. COMMON CATHODE DOCUMENT NUMBER: DESCRIPTION: 98AON12199D SOIC−7 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2023 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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