NCP1240
Fixed Frequency Current
Mode Controller for Flyback
Converters
The NCP1240 is a new fixed−frequency current−mode controller
featuring the Dynamic Self−Supply. This function greatly simplifies
the design of the auxiliary supply and the VCC capacitor by activating
the internal startup current source to supply the controller during
start−up, transients, latch, stand−by etc. This device contains a special
HV detector which detect the application unplug from the AC input
line and triggers the X2 discharge current. This HV structure allows
the brown−out detection as well.
It features a timer−based fault detection that ensures the detection of
overload and an adjustable compensation to help keep the maximum
power independent of the input voltage.
Due to frequency foldback, the controller exhibits excellent
efficiency in light load condition while still achieving very low
standby power consumption. Internal frequency jittering, ramp
compensation, and a versatile latch input make this controller an
excellent candidate for the robust power supply designs.
A dedicated Off mode allows to reach the extremely low no load
input power consumption via “sleeping” whole device and thus
minimize the power consumption of the control circuitry.
Features
• Fixed−Frequency Current−Mode Operation (65 kHz and 100 kHz
frequency options)
• Frequency Foldback then Skip Mode for Maximized Performance in
•
•
•
•
•
•
•
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MARKING
DIAGRAM
8
SOIC−7
CASE 751U
40Xfff
ALYWX
G
1
40Xfff = Specific Device Code
X = A, B, E or F
fff = 065 or 100
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
PIN CONNECTIONS
Latch 1
8
HV
6
VCC
FB 2
CS 3
GND 4
5 DRV
Light Load and Standby Conditions
(Top View)
Timer−Based Overload Protection with Latched (Options A and E) or
Auto−Recovery (Options B and F) Operation
High−voltage Current Source with Brown−Out Detection and
ORDERING INFORMATION
See detailed ordering and shipping information on page 44 of
Dynamic Self−Supply, Simplifying the Design of the VCC Circuitry
this data sheet.
Frequency Modulation for Softened EMI Signature
Adjustable Overpower Protection Dependant on the Bulk Voltage
Latch−off Input Combined with the Overpower Protection Sensing
Input
VCC Operation up to 28 V, With Overvoltage Detection
Typical Applications
500/800 mA Source/Sink Drive Peak Current
• AC−DC Adapters for Notebooks, LCD, and Printers
Capability
• Offline Battery Chargers
10 ms Soft−Start
• Consumer Electronic Power Supplies
Internal Thermal Shutdown
• Auxiliary/Housekeeping Power Supplies
No−Load Standby Power < 30 mW
• Offline Adapters for Notebooks
X2 Capacitor in EMI Filter Discharging Feature
•
•
•
•
• These Devices are Pb−Free and Halogen Free/BFR Free
© Semiconductor Components Industries, LLC, 2015
July, 2015 − Rev. 1
1
Publication Order Number:
NCP1240/D
NCP1240
GND
GND
GND
VCC 6
DRV 5
+
W2
RLOAD
W1
4
GND
6
Q1
COUT
GND
NCP1240
ROPP
R4
GND GND
3 CS
4 GND
C1
HV 8
RSENSE
NTC
2
5
W3
1 LATCH
2 FB
C4
CCLAMP
RCLAMP
CBULK
+
D5
34
D4
34
IC1
dc output
D1
3
D3
D8
D10
CX1
CX2
ac input
GND
RHV
D9
12 L1
1 TR
D2
12 L2
D7
D6
TYPICAL APPLICATION EXAMPLE
GND
2
PC817
GND
GND
C3
R1
1
3
IC2
NCP431
R2
C2
R3
OK1
4
GND
GND
Figure 1. Flyback Converter Application Using the NCP1240
OPTIONS
Part
Option
Frequency
OCP Fault
A
65 kHz
Latched
A
100 kHz
Latched
B
65 kHz
Autorecovery
B
100 kHz
Autorecovery
E
65 kHz
Latched
F
65 kHz
Autorecovery
NCP1240
PIN FUNCTION DESCRIPTION
Pin No
Pin Name
Function
Pin Description
1
LATCH
Latch−Off Input
Pull the pin up or down to latch−off the controller. An internal current source
allows the direct connection of an NTC for over temperature detection.
2
FB
Feedback + Shutdown pin
An optocoupler collector to ground controls the output regulation. The part
goes to the low consumption Off mode if the FB input pin is pulled to GND.
3
CS
Current Sense
4
GND
−
5
DRV
Drive output
6
VCC
VCC input
8
HV
High−voltage pin
This Input senses the Primary Current for current−mode operation, and
offers an overpower compensation adjustment.
The controller ground
Drives external MOSFET
This supply pin accepts up to 28 Vdc, with overvoltage detection. The pin is
connected to an external auxiliary voltage. It is not allowed to connect
another circuit to this pin to keep low input power consumption.
Connects to the rectified AC line to perform the functions of Start−up
Current Source, Self−Supply, brown−out detection and X2 capacitor
discharge function and the HV sensing for the overpower protection
purposes. It is not allowed to connect this pin to DC voltage.
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2
NCP1240
SIMPLIFIED INTERNAL BLOCK SCHEMATIC
Intc
Intc
Vdd
Vhv DC sample
HV
Brown_Out
OVP_CMP
SG & X2 & Vcc
TSD
Dual HV
Start−up
current source
control
VCC
Vcc_Int
UVLO_CMP
9.3V
Latch
ICstartB
Vdd reg
ON_CMP
Brown_Out
10.8V
Q
Vcc regulator
PowerOnReset_CMP
RESET
Vdd
VccON
Reset Qb
Vcc(reg)
Set
VccOFF
SS_end
UVLO
VccRESET
26V
OTP
0.4V
Votp
1k
350 us
Filter
1.2V
Vclamp Rclamp
OTP_CMP
10 us
Filter
VccOVP
VccOVP
LATCH
8 mA
VccOVP_CMP
2.5V
Vovp
AC_Off
OVP
50 us
Filter
5V
12V
VccON
RESET
STOP_CMP
VccMIN
8.4V
Off_mode_CMP1
2.2V
Set
Von
VccMIN
5uA
VCC
ICstart
Q
Reset Qb
Off_mode_CMP2
FB
0.8V
OSC 65kHz
ton_max output
3.0V
PFM input
freq folback
CSref
Saw output
Ramp_OTA
FBbuffer
4uMho
VCC
Vskip
SkipB
1.4V
Skip_CMP
Vramp_offset
Rfb1
Vfb(reg)
Square output
FM input
jittering
Internal resitance 40k
Voff
GoToOffMode timer 500ms
Clamp
PWM_CMP
Set
IC stopB
Q
PWM
Qb
LatchB
SoftStart_CMP
V to I
FaultB
Reset
Brown_OutB
Vfb(opc)
DRV
Division ratio 4
Rfb3
Rfb2
Vhv DC sample
MAX_ton
Iopc = 0.5u*(Vhv−125)
Enable
Soft Start timer
Vdd
SS_end
1uA
Itran_CMP
Itran
Vcs(tran)
0.5V
CS
Set
Reset
Ilimit_CMP
Q
Transient timer up/down
Fault
Qb
MAX_ton
Ilimit
Set
Fault timer
Q
RESET
Fault
Qb
Latch management
GND
0.7V
Vilim
IC stop
Reset
Autorecovery timer
CSstop_CMP
LEB 120ns
Brown_Out
1.05V
VCSstop
4 events timer
TSD
Figure 2. Simplified Internal Block Schematic
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3
TSD
Latch
NCP1240
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
–0.3 to 20
±1000 (peak)
V
mA
VCCPower Supply voltage, VCC pin, continuous voltage
Power Supply voltage, VCC pin, continuous voltage (Note 1)
–0.3 to 28
±30 (peak)
V
mA
Maximum voltage on HV pin
(Dc−Current self−limited if operated within the allowed range)
–0.3 to 500
±20
V
mA
Vmax
Maximum voltage on low power pins (except pin 5, pin 6 and pin 8)
(Dc−Current self−limited if operated within the allowed range) (Note 1)
–0.3 to 10
±10 (peak)
V
mA
RqJ−A
Thermal Resistance SOIC−7
Junction-to-Air, low conductivity PCB (Note 2)
Junction-to-Air, medium conductivity PCB (Note 3)
Junction-to-Air, high conductivity PCB (Note 4)
162
147
115
RqJ−C
Thermal Resistance Junction−to−Case
73
°C/W
TJMAX
Operating Junction Temperature
−40 to +150
°C
Storage Temperature Range
−60 to +150
°C
ESD Capability, HBM model (All pins except HV) per JEDEC Standard JESD22,
Method A114E
> 2000
V
ESD Capability, Machine Model per JEDEC Standard JESD22, Method A115A
> 200
V
DRV
(pin 5)
Maximum voltage on DRV pin
(Dc−Current self−limited if operated within the allowed range) (Note 1)
VCC
(pin 6)
HV
(pin 8)
TSTRGMAX
°C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device contains latch-up protection and exceeds 100 mA per JEDEC Standard JESD78.
2. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 50 mm2 of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51-1 conductivity test PCB. Test conditions were under natural convection or zero air flow.
3. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 100 mm2 of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51-2 conductivity test PCB. Test conditions were under natural convection or zero air flow.
4. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 650 mm2 of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51-3 conductivity test PCB. Test conditions were under natural convection or zero air flow.
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VHV = 125 V,
VCC = 11 V unless otherwise noted)
Symbol
Min
Typ
Max
Unit
VHV(min)
−
30
40
V
VCC = 0 V
VCC = VCC(on) − 0.5 V
Istart1
Istart2
0.2
5
0.5
8
0.8
11
mA
Off−state Leakage Current
VHV = 500 V, VCC = 15 V
Istart(off)
10
25
50
mA
Off−mode HV Supply Current
VHV = 141 V,
VHV = 325 V,
VCC loaded by 4.7 mF cap
IHV(off)
−
−
45
50
60
70
mA
HV Current Source Regulation Threshold
VCC(reg)
8
11
−
V
Turn−on Threshold Level, VCC Going Up
HV Current Source Stop Threshold
VCC(on)
11.0
12.0
13.0
V
HV Current Source Restart Threshold
VCC(min)
7.8
8.4
9.0
V
Turn−off Threshold (Note 5)
VCC(off)
8.8
9.3
9.8
V
Overvoltage Threshold
VCC(ovp)
25
26.5
28
V
Characteristics
Test Condition
HIGH VOLTAGE CURRENT SOURCE
Minimum Voltage for Current Source
Operation
Current Flowing Out of VCC Pin
(X2 discharge current value is equal to Istart2)
SUPPLY
5.
6.
7.
8.
VCC(off) < VCC(min) with the minimum gap 0.5 V.
Internal supply current only, currents sourced via FB pin is not included (current is flowing in GND pin only).
Guaranteed by design.
CS pin source current is a sum of Ibias and IOPC, thus at VHV = 125 V is observed the Ibias only, because IOPC is switched off.
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NCP1240
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VHV = 125 V,
VCC = 11 V unless otherwise noted)
Characteristics
Test Condition
Symbol
Min
Typ
Max
Unit
Blanking Duration on VCC(off) and VCC(ovp)
Detection
tVCC(blank)
−
10
−
ms
VCC Decreasing Level at Which the Internal
Logic Resets
VCC(reset)
4.8
7.0
7.7
V
VCC Level for ISTART1 to ISTART2 Transition
VCC(inhibit)
0.2
0.8
1.25
V
DRV open, VFB = 3 V, 65 kHz
DRV open, VFB = 3 V, 100 kHz
ICC1
ICC1
1.3
1.3
1.85
1.85
2.2
2.2
mA
Cdrv = 1 nF, VFB = 3 V, 65 kHz
Cdrv = 1 nF, VFB = 3 V, 100 kHz
ICC2
ICC2
1.8
2.0
2.6
2.9
3.0
3.2
Off mode (skip or before start−up)
ICC3
0.5
0.65
0.8
Fault mode (fault or latch)
ICC4
0.35
0.5
0.7
VHV going up
VHV going down
VHV(start)
VHV(stop)
102
94
111
103
120
112
V
tHV
35
50
75
ms
VHV(hyst)
1.5
3.5
5
V
Tsample
−
1.0
−
ms
Timer Duration for No Line Detection
tDET
43
64
86
ms
Discharge Timer Duration
tDIS
43
64
86
ms
fOSC
58
87
65
100
72
109
kHz
SUPPLY
Internal Current Consumption (Note 6)
BROWN−OUT
Brown−Out Thresholds
Timer Duration for Line Cycle Drop−out
X2 DISCHARGE
Comparator Hysteresis Observed at HV Pin
HV Signal Sampling Period
OSCILLATOR
Oscillator Frequency
Maximum On Time for TJ = 25°C to +125°C
Only
fOSC = 65 kHz
fOSC = 100 kHz
tONmax(65kHz)
tONmax(100kHz)
11.5
7.5
12.3
8.0
13.1
8.5
ms
Maximum On Time
fOSC = 65 kHz
fOSC = 100 kHz
tONmax(65kHz)
tONmax(100kHz)
11.3
7.4
12.3
8.0
13.1
8.5
ms
Maximum Duty Cycle (corresponding to
maximum on time at maximum switching
frequency)
fOSC = 65 kHz
fOSC = 100 kHz
DMAX
−
80
−
%
Frequency Jittering Amplitude, in Percentage
of FOSC
Ajitter
±3
±5.5
±8
%
Frequency Jittering Modulation Frequency
Fjitter
85
125
165
Hz
FREQUENCY FOLDBACK
Feedback Voltage Threshold Below Which
Frequency Foldback Starts
TJ = 25°C
VFB(foldS)
2.35
2.5
2.6
V
Feedback Voltage Threshold Below Which
Frequency Foldback is Complete
TJ = 25°C
VFB(foldE)
1.4
1.5
1.6
V
VFB = Vskip(in) + 0.1
fOSC(min)
23
21
27
27
32
32
Minimum Switching Frequency
(NCP1240A/B)
(NCP1240E/F)
5.
6.
7.
8.
kHz
VCC(off) < VCC(min) with the minimum gap 0.5 V.
Internal supply current only, currents sourced via FB pin is not included (current is flowing in GND pin only).
Guaranteed by design.
CS pin source current is a sum of Ibias and IOPC, thus at VHV = 125 V is observed the Ibias only, because IOPC is switched off.
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NCP1240
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VHV = 125 V,
VCC = 11 V unless otherwise noted)
Characteristics
Test Condition
Symbol
Min
Typ
Max
Unit
Rise Time, 10% to 90% of VCC
VCC = VCC(min) + 0.2 V,
CDRV = 1 nF
trise
−
40
70
ns
Fall Time, 90% to 10% of VCC
VCC = VCC(min) + 0.2 V,
CDRV = 1 nF
tfall
−
40
70
ns
Current Capability
VCC = VCC(min) + 0.2 V,
CDRV = 1 nF
DRV high, VDRV = 0 V
DRV low, VDRV = VCC
OUTPUT DRIVER
Clamping Voltage (maximum gate voltage)
High−state Voltage Drop
mA
IDRV(source)
IDRV(sink)
−
−
500
800
−
−
VCC = VCCmax – 0.2 V, DRV high,
RDRV = 33 kW, Cload = 220 pF
VDRV(clamp)
11
13.5
16
V
VCC = VCC(min) + 0.2 V,
RDRV = 33 kW, DRV high
VDRV(drop)
−
−
1
V
CURRENT SENSE
Input Pull−up Current
VCS = 0.7 V
Ibias
−
1
−
mA
Maximum Internal Current Setpoint
VFB > 3.5 V
VILIM
0.66
0.70
0.74
V
Propagation Delay from VIlimit Detection to
DRV Off
VCS = VILIM
tdelay
−
80
110
ns
tLEB
200
250
340
ns
Threshold for Fast Fault Protection Activation
VCS(stop)
0.95
1.05
1.15
V
Leading Edge Blanking Duration for VCS(stop)
(Note 7)
tBCS
90
120
150
ns
tSSTART
8
11
14
ms
Scomp(65kHz)
Scomp(100kHz)
−
−
−32.5
−50
−
−
mV /
ms
RFB(up)
30
40
50
kW
KFB
−
4
−
−
VFB(ref)
4.5
5
5.5
V
TJ = 25°C
VFB(off)
−
0.8
−
V
VFB going down, TJ = 25°C
VFB going up, TJ = 25°C
Vskip(in)
Vskip(out)
1.1
1.2
1.2
1.3
1.3
1.4
V
The Voltage Above which the Part Enters the
On Mode
VCC > VCC(off), VHV = 60 V
VON
−
2.2
−
V
The Voltage Below which the Part Enters the
Off Mode
VCC > VCC(off)
VOFF
0.5
0.6
0.7
V
VCC > VCC(off), VHV = 60 V
VHYST
500
−
−
mV
VCC > VCC(off)
IOFF
−
5
−
mA
Leading Edge Blanking Duration for VILIM
Soft−start Duration
From 1st pulse to VCS = VILIM
INTERNAL SLOPE COMPENSATION
Slope of the Compensation Ramp
FEEDBACK
Internal Pull−up Resistor
TJ = 25°C
VFB to Internal Current Setpoint Division
Ratio
Internal Pull−up Voltage on the FB Pin
(Note 7)
Feedback Voltage Below which the Peak
Current is Frozen
SKIP CYCLE MODE
Feedback Voltage Thresholds for Skip Mode
REMOTE CONTROL ON FB PIN
Minimum Hysteresis Between the VON and
VOFF
Pull−up Current in Off Mode
5.
6.
7.
8.
VCC(off) < VCC(min) with the minimum gap 0.5 V.
Internal supply current only, currents sourced via FB pin is not included (current is flowing in GND pin only).
Guaranteed by design.
CS pin source current is a sum of Ibias and IOPC, thus at VHV = 125 V is observed the Ibias only, because IOPC is switched off.
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NCP1240
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VHV = 125 V,
VCC = 11 V unless otherwise noted)
Characteristics
Test Condition
Symbol
Min
Typ
Max
Unit
VCC > VCC(off)
tGTOM
400
500
600
ms
tfault
44
9.1
64
14
84
23.2
ms
tautorec
0.85
1.00
1.35
s
VCS(tran)
0.46
0.49
0.52
V
4.1
44
6.1
64
8.1
84
s
ms
KOPC
−
0.54
−
mA / V
REMOTE CONTROL ON FB PIN
Go To Off Mode Timer
OVERLOAD PROTECTION
Fault Timer Duration
(NCP1240A/B)
(NCP1240E/F)
Autorecovery Mode Latch−off Time Duration
CS Threshold for Transient Peak Timer
Activation
Transient Peak Power Timer Duration
VCS(peak) = VCS(tran) + 0.1 V from 1st
(NCP1240A/B) time VCS > VCS(tran) to DRV stop
(NCP1240E/F)
ttran
OVERPOWER PROTECTION
VHV to IOPC Conversion Ratio
Current Flowing out of CS Pin (Note 8)
VHV = 125 V
VHV = 162 V
VHV = 325 V
VHV = 365 V
IOPC(125)
IOPC(162)
IOPC(325)
IOPC(365)
−
−
−
105
0
20
110
130
−
−
−
150
mA
FB Voltage Above which IOPC is Applied
VHV = 365 V
VFB(OPCF)
−
2.6
−
V
FB Voltage Below which is No IOPC Applied
VHV = 365 V
VFB(OPCE)
−
2.1
−
V
High Threshold
VLatch going up
VOVP
2.35
2.5
2.65
V
Low Threshold
VLatch going down
VOTP
−
0.4
−
V
External NTC resistance
is going down
ROTP
6.6
−
−
7.7
8.5
9.5
8.6
−
−
kW
INTC
20
60
50
100
70
140
tLatch(OVP)
35
20
50
35
70
55
ms
tLatch(OTP)
−
350
−
ms
ILatch = 0 mA
ILatch = 1 mA
Vclamp0(Latch)
Vclamp1(Latch)
1.0
1.8
1.2
2.4
1.4
3.0
V
TJ going up
TTSD
−
150
−
°C
TJ going down
TTSD(HYS)
−
30
−
°C
LATCH−OFF INPUT
OTP Resistance Threshold
(TJ = 25°C)
(TJ = 80°C)
(TJ = 110°C)
Current Source for Direct NTC Connection
During Sormal Operation
During Soft−start
VLatch = 0 V
Blanking Duration On High Latch Detection
65 kHz version
100 kHz version
INTC(SSTART)
Blanking Duration On Low Latch Detection
Clamping voltage
mA
TEMPERATURE SHUTDOWN
Temperature shutdown
Temperature shutdown hysteresis
5.
6.
7.
8.
VCC(off) < VCC(min) with the minimum gap 0.5 V.
Internal supply current only, currents sourced via FB pin is not included (current is flowing in GND pin only).
Guaranteed by design.
CS pin source current is a sum of Ibias and IOPC, thus at VHV = 125 V is observed the Ibias only, because IOPC is switched off.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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NCP1240
TYPICAL CHARACTERISTIC
30
32
28
30
Istart(off) (mA)
VHV(min) (V)
26
24
22
20
26
24
22
18
16
−50
−25
0
25
50
75
100
20
−50
125
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 3. Minimum Current Source Operation
VHV(min)
Figure 4. Off−State Leakage Current Istart(off)
50
8.8
45
8.7
8.6
40
IHV(off) @ VHV = 325 V
Istart2 (mA)
IHV(off) (mA)
28
35
8.5
8.4
30
8.3
25
8.2
−25
0
25
50
75
100
8.1
−50
125
−25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 5. Off−Mode HV Supply Current IHV(off)
Figure 6. High Voltage Startup Current
Flowing Out of VCC Pin Istart2
120
120
115
115
VHV(stop) (V)
VHV(start) (V)
20
−50
110
105
100
95
−50
125
110
105
100
−25
0
25
50
75
100
125
95
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. Brown−out Device Start Threshold
VHV(start)
Figure 8. Brown−out Device Stop Threshold
VHV(stop)
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NCP1240
TYPICAL CHARACTERISTIC
0.52
0.75
0.74
0.51
0.73
VCS(tran) (V)
VILIM (V)
0.72
0.71
0.70
0.69
0.68
0.67
0.50
0.49
0.48
0.47
0.66
0.65
−50
−25
0
25
50
75
100
0.46
−50
125
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9. Maximum Internal Current Setpoint
VILIM
Figure 10. Threshold for Transient Peak Power
Timer Activation VCS(tran)
90
1.15
1.13
80
1.11
70
1.07
tdelay (ns)
VCS(stop) (V)
1.09
1.05
1.03
60
50
1.01
0.99
40
0.97
0.95
−50
−25
0
25
50
75
100
30
−50
125
−25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. Threshold for Immediate Fault
Protection Activation VCS(stop)
Figure 12. Propagation Delay tdelay
125
130
320
128
310
126
124
IOPC(365) (mA)
tLEB (ns)
300
290
280
122
120
118
116
270
114
260
250
−50
112
−25
0
25
50
75
100
110
−50
125
−25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. Leading Edge Blanking Duaration
tLEB
Figure 14. Maximum Overpower
Compensating Current IOPC(365) Flowing Out
of CS Pin
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125
NCP1240
TYPICAL CHARACTERISTIC
5.20
50
48
5.10
46
5.00
VFB(ref) (V)
RFB(up) (kW)
44
42
40
38
4.90
4.80
36
34
4.70
32
30
−50
−25
0
25
50
75
100
4.60
−50
125
−25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 15. FB Pin Internal Pull−up Resistor
RFB(up)
Figure 16. FB Pin Open Voltage VFB(ref)
4.50
1.20
4.40
1.10
125
4.30
1.00
VFB(off) (V)
KFB (−)
4.20
4.10
4.00
3.90
0.90
0.80
0.70
3.80
0.60
3.70
0.50
3.60
−25
0
25
50
75
100
0.40
−50
125
0
25
50
75
100
TEMPERATURE (°C)
Figure 17. VFB to Internal Current Setpoint
Division Ratio KFB
Figure 18. Offset Voltage VFB(off) between
FB Pin and Internal FB Divider
2.65
12
2.60
11
2.55
10
2.50
8
2.40
7
−25
0
25
50
75
100
125
6
−50
−25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 19. Latch Pin High Threshold VOVP
Figure 20. OTP Reistance Threshold ROTP at
Latch Pin
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10
125
9
2.45
2.35
−50
−25
TEMPERATURE (°C)
ROTP (kW)
VOVP (V)
3.50
−50
125
NCP1240
TYPICAL CHARACTERISTIC
120
70
65
110
60
INTC(SSTART) (mA)
INTC (mA)
55
50
45
40
35
30
100
90
80
70
25
−25
0
25
50
75
100
60
−50
125
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 22. Current INTC(SSTART) Sourced from
the Latch Pin, During Soft−Start
100
8.5
99
8.4
98
8.3
97
8.2
96
95
94
8.1
8.0
7.9
93
7.8
92
7.7
91
7.6
90
−50
−25
Figure 21. Current INTC Sourced from the
Latch Pin, Allowing Direct NTC Connection
fOSC (kHz)
fOSC (kHz)
20
−50
−25
0
25
50
75
100
7.5
−50
125
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 23. Oscillator fOSC for the 65 kHz
Version (NCP1240A/B only)
Figure 24. Maximum ON Time tONmax for the
65 kHz Version (NCP1240A/B only)
82
30
81
29
80
28
fOSC(min) (ms)
DMAX (%)
79
78
77
76
27
26
25
75
24
74
23
73
72
−50
−25
0
25
50
75
TEMPERATURE (°C)
100
125
22
−50
Figure 25. Maximum Duty Ratio DMAX
−25
0
25
50
75
TEMPERATURE (°C)
100
Figure 26. Minimum Switching Frequency
fOSC(min)
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125
NCP1240
TYPICAL CHARACTERISTIC
1.80
2.80
1.70
2.70
VFB(foldE) (V)
VFB(foldS) (V)
1.60
2.60
2.50
2.40
1.50
1.40
1.30
1.20
2.30
2.20
−50
1.10
−25
0
25
50
75
100
125
1.00
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 28. FB Pin Voltage Below Which
Frequency Foldback Complete VFB(foldE)
1.50
1.60
1.40
1.50
1.30
1.40
Vskip(on) (V)
Vskip(in) (V)
Figure 27. FB Pin Voltage Below Which
Frequency Foldback Starts VFB(foldS)
1.20
1.10
1.30
1.20
1.00
1.10
0.90
1.00
0.80
−50
−25
0
25
50
75
100
125
0.90
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 29. FB Pin Skip−In Level Vskip(in)
Figure 30. FB Pin Skip−Out Level Vskip(out)
2.80
2.50
2.40
2.70
2.30
2.20
VFB(OPCE) (V)
VFB(OPCF) (V)
2.60
2.50
2.40
2.10
2.00
1.90
1.80
2.30
1.70
2.20
2.10
−50
1.60
−25
0
25
50
75
100
125
1.50
−50
TEMPERATURE (°C)
−25
0
25
50
75
100
TEMPERATURE (°C)
Figure 31. FB Pin Level VFB(OPCF) Above
Which is the Overpower Compensation
Applied
Figure 32. FB Pin Level VFB(OPCE) Below
Which is No Overpower Compensation
Applied
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125
NCP1240
TYPICAL CHARACTERISTIC
9.0
13.0
12.8
8.8
12.6
VCC(min) (V)
VCC(on) (V)
12.4
12.2
12.0
11.8
11.6
11.4
8.6
8.4
8.2
8.0
11.2
11.0
−50
−25
0
25
50
75
100
7.8
−50
125
−25
TEMPERATURE (°C)
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 33. VCC Turn−on Threshold Level, VCC
Going Up HV Current Source Stop Threshold
VCC(on)
Figure 34. HV Current Source Restart
Threshold VCC(min)
9.4
7.0
6.9
9.3
6.8
VCC(reset) (V)
VCC(off) (V)
9.2
9.1
9.0
6.7
6.6
6.5
6.4
6.3
8.9
6.2
8.8
−50
−25
0
25
50
75
100
6.1
−50
125
−25
TEMPERATURE (°C)
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 35. VCC Turn−off Threshold (UVLO)
VCC(off)
Figure 36. VCC Decreasing Level at Which the
Internal Logic Resets VCC(reset)
2.2
3.2
2.1
3.0
2.0
2.8
ICC2 (mA)
ICC1 (mA)
1.9
1.8
1.7
1.6
2.6
2.4
1.5
2.2
1.4
1.3
−50
−25
0
25
50
TEMPERATURE (°C)
75
100
125
2.0
−50
Figure 37. Internal Current Consumption when
DRV Pin is Unloaded
−25
0
25
50
75
TEMPERATURE (°C)
100
125
Figure 38. Internal Current Consumption when
DRV Pin is Loaded by 1 nF
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NCP1240
4.0
1.10
3.8
1.08
3.6
1.06
3.4
1.04
Tsample (ms)
VHV(hyst) (V)
TYPICAL CHARACTERISTIC
3.2
3.0
2.8
1.02
1.00
0.98
2.6
0.96
2.4
0.94
2.2
0.92
2.0
−50
−25
0
25
50
75
100
0.90
−50
125
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 39. X2 Discharge Comparator
Hysteresis Observed at HV Pin VHV(hyst)
Figure 40. HV Signal Sampling Period Tsample
80
75
70
75
70
60
tfault (V)
tHV (ms)
65
55
50
65
60
45
55
40
35
−50
−25
0
25
50
75
100
50
−50
125
0
25
50
75
100
TEMPERATURE (°C)
Figure 41. Timer Duration for Line Cycle
Drop−out tHV
Figure 42. Fault Timer Duration tfault
(NCP1240A/B only)
8.00
600
7.50
580
125
560
7.00
540
tGTOM (ms)
6.50
ttran (s)
−25
TEMPERATURE (°C)
6.00
5.50
520
500
480
460
5.00
440
4.50
420
4.00
−50
−25
0
25
50
75
100
125
400
−50
−25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 43. Transient Peak Power Timer Timer
Duration ttran (NCP1240A/B only)
Figure 44. Go To Off Mode Timer Duration
tGTOM
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125
NCP1240
APPLICATION INFORMATION
Functional Description
range, the duty−ratio may increase up to 50%. The build−in
slope compensation prevents the appearance of
sub−harmonic oscillations in this operating area.
The converter operates in frequency foldback mode
(FFM) for loads that are between approximately 17% and
48% of full rated power.
Effectively, operation in FFM results in the application of
constant volt−seconds to the flyback transformer each
switching cycle. Voltage regulation in FFM is achieved by
varying the switching frequency in the range from 65 kHz
(or 100 kHz) to 27 kHz. For extremely light loads (below
approximately 6% full rated power), the converter is
controlled using bursts of 27 kHz pulses. This mode is called
as skip mode. The FFM, keeping constant peak current and
skip mode allows design of the power supplies with
increased efficiency under the light loading conditions.
Keep in mind that the aforementioned boundaries of
steady−state operation are approximate because they are
subject to converter design parameters.
The NCP1240 includes all necessary features to build a
safe and efficient power supply based on a fixed−frequency
flyback converter. The NCP1240 is a multimode controller
as illustrated in Figure 45. The mode of operation depends
upon line and load condition. Under all modes of operation,
the NCP1240 terminates the DRV signal based on the switch
current. Thus, the NCP1240 always operates in current
mode control so that the power MOSFET current is always
limited.
Under normal operating conditions, the FB pin commands
the operating mode of the NCP1240 at the voltage
thresholds shown in Figure 45. At normal rated operating
loads (from 100% to approximately 33% full rated power)
the NCP1240 controls the converter in fixed frequency
PWM mode. It can operate in the continuous conduction
mode (CCM) or discontinuous conduction mode (DCM)
depending upon the input voltage and loading conditions. If
the controller is used in CCM with a wide input voltage
Low consumption off mode
ON
OFF
0V
PWM at f OSC
FFM
Skip mode
0.8 V 1.2 V
1.5 V
1.3 V
2.2 V
2.5 V
3.6 V
VFB
Figure 45. Mode Control with FB Pin Voltage
decreases below the 0.6 V the controller will enter the low
consumption off mode. The controller can start if the FB pin
voltage increases above the 2.2 V level.
See the detailed status diagrams for the versions fully
latched A and the autorecovery B on the following figures.
The basic status of the device after wake–up by the VCC is
the off mode and mode is used for the overheating protection
mode if the thermal shutdown protection is activated.
There was implemented the low consumption off mode
allowing to reach extremely low no load input power. This
mode is controlled by the FB pin and allows the remote
control (or secondary side control) of the power supply
shut−down. Most of the device internal circuitry is unbiased
in the low consumption off mode. Only the FB pin control
circuitry and X2 cap discharging circuitry is operating in the
low consumption off mode. If the voltage at feedback pin
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15
NCP1240
VHV > VHV(NOAC)
<
VOFF)
*
GTOMtimer*(VCC
>
VCCoff)
BO+TSD
Reset
Latch=0
VCC
fault
Soft
Start
(VCC < VCCoff
(VCC > VCCon)*BO
Efficient operating mode
BO+TSD
Stop
VCC > VCCoff
SSend
Skip in
Running
Skip
mode
Dynamic Self−Supply
Skip out
(if not enoughgh auxiliary voltage is
present)
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Extra Low Consumption
(VFB
(VFB > VON)*Latch
BO
Latch
Latch=1
(VCC < VCCoff
16
Off Mode
Latch=X
(VFB > VON)*Latch
No AC
AC present
+
discharged
BO
OVP+OTP+VCCovp+VCSstop
(VILIM +MaxDC)*tfault
X2 cap
Discharge
Latch=0
VCC > VCCreset
Power On
Reset
Latch=0
Regulated Self−Supply
VCC > VCCreset
Figure 46. Operating Status Diagram for the Fully Latched Versions A and E of the Device
NCP1240
VHV > V
VCC
>
VCCoff
(VCC > VCCon)*BO
Efficient operating mode
BO+TSD
Stop
BO
Autorecovery
Latch
AutoRec=1
Soft
Start
VCC
fault
VCC
<
SSend
Skip in
VCCoff
Running
Skip
mode
present)
Skip out
Dynamic Self−Supply
(if not enough auxiliary voltage is
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BO+TSD
Reset
Latch=0
AutoRec=0
BO+tautorec
Extra Low Consumption
(VFB > VON)*Latch*AutoRec
BO
Latch
Latch=1
VCSstop
VCC < VCCoff
17
Off Mode
Latch=X
AutoRec=X
BO
OVP+OTP+VCCovp
(VFB > VON)*AutoRec
(VILIM + MaxDC)*tfault
(VFB < VOFF) * GTOMtimer*(VCC > VCCoff)
AC present
+
discharged
(VFB > VON)*Latch
No AC
HV(NOAC)
X2 cap
Discharge
Latch=0
AutoRec=0
VCC < VCCreset
Power On
Reset
Latch=0
AutoRec=0
Regulated Self−Supply
VCC > VCCreset
Figure 47. Operating Status Diagram for the Autorecovery Versions B and F of the Device
NCP1240
Even though the Dynamic Self−Supply is able to maintain
the VCC voltage between VCC(on) and VCC(min) by turning
the HV start−up current source on and off, it can only be used
in light load condition, otherwise the power dissipation on
the die would be too much. As a result, an auxiliary voltage
source is needed to supply VCC during normal operation.
The Dynamic Self−Supply is useful to keep the controller
alive when no switching pulses are delivered, e.g. in
brown−out condition, or to prevent the controller from
stopping during load transients when the VCC might drop.
The NCP1240 accepts a supply voltage as high as 28 V, with
an overvoltage threshold VCC(ovp) that latches the controller
off.
The information about the fault (permanent Latch or
Autorecovery) is kept during the low consumption off mode
due the safety reason. The reason is not to allow unlatch the
device by the remote control being in off mode.
Start−up of the Controller
At start−up, the current source turns on when the voltage
on the HV pin is higher than VHV(min), and turns off when
VCC reaches VCC(on), then turns on again when VCC reaches
VCC(min), until the input voltage is high enough to ensure a
proper start−up, i.e. when VHV reaches VHV(start). The
controller actually starts the next time VCC reaches VCC(on).
The controller then delivers pulses, starting with a soft−start
period tSSTART during which the peak current linearly
increases before the current−mode control takes over.
VHV
V HV(start)
V HV(min)
Waits next VCC(on)
before starting
time
VCC
V CC(on)
V CC(min)
HV current
source = I start1
HV current
source = Istart2
V CC(inhibit)
time
DRV
Figure 48. VCC Start−up Timing Diagram
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18
time
NCP1240
For safety reasons, the start−up current is lowered when
VCC is below VCC(inhibit), to reduce the power dissipation in
case the VCC pin is shorted to GND (in case of VCC capacitor
failure, or external pull−down on VCC to disable the
controller). There is only one condition for which the current
source doesn’t turn on when VCC reaches VCC(inhibit): the
voltage on HV pin is too low (below VHV(min)).
threshold and an autorecovery brown−out protection; both
of them independent of the ripple on the input voltage. It is
allowed only to work with an unfiltered, rectified ac input to
ensure the X2 capacitor discharge function as well, which is
described in following. The brown−out protection
thresholds are fixed, but they are designed to fit most of the
standard ac−dc conversion applications.
When the input voltage goes below VHV(stop), a
brown−out condition is detected, and the controller stops.
The HV current source maintains VCC at VCC(min) level until
the input voltage is back above VHV(start).
HV Sensing of Rectified AC Voltage
The NCP1240 features on its HV pin a true ac line
monitoring circuitry. It includes a minimum start−up
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NCP1240
Figure 49. Ac Line Drop−out Timing Diagram
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20
NCP1240
VOUT
VOUT(typ)
Overload
applied
Waits next
VccON before
VCC
time
VCC(on)
VCC(off)
VCC(min)
tautorec
Autorecovery
timer starts
Autorecovery
timer elapses
time
DRV
Controller
restarts
Controller
latches off
time
Figure 50. VCC Collapses After Overload and Its Recovery
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21
NCP1240
HV timer elapsed
VHV
VHV(start)
VHV(stop)
Spike induced by
residual energy in
HV stop
tHV
time
Brown−out
detected
Waits next
VccON before
starting
VCC
time
VCC(on)
VCC(min)
DRV
Brown−out
condition
resets the
Internal Latch
Figure 51. Ac Line Drop−out Timing Diagram with Parasitic Spike
time
time
immediately after the device is stopped by the residual
energy in the EMI filter. The device restart is allowed only
after the 1st watch dog signal event. The basic principle is
shown at Figure 49 and detail of the device restart is shown
at Figure 52.
When VHV crosses the VHV(start) threshold, the controller
can start immediately. When it crosses VHV(stop), it triggers
a timer of duration tHV, this ensures that the controller
doesn’t stop in case of line cycle drop−out. The device restart
after the ac line voltage drop-out is protected to the parasitic
restart initiated e.g. the spikes induced at HV pin
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NCP1240
Figure 52. Detailed Timing Diagram of the Device Restart After the Short ac Line Drop−out
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NCP1240
X2 Cap Discharge Feature
In case of the dc signal presence on the high voltage input,
the direct sample of the high voltage obtained via the high
voltage sensing structure and the delayed sample of the high
voltage are equivalent and the comparator produces the low
level signal during the presence of this signal. No edges are
present at the output of the comparator, that’s why the
detection timer is not reset and dc detect signal appears.
The minimum detectable slope by this ac detector is given
by the ration between the maximum hysteresis observed at
HV pin VHV(hyst),max and the sampling time:
The X2 capacitor discharging feature is offered by usage
of the NCP1240. This feature saves approximately 16 mW
− 25 mW input power depending on the EMI filter X2
capacitors volume and it saves the external components
count as well. The discharge feature is ensured via the
start−up current source with a dedicated control circuitry for
this function. The X2 capacitors are being discharged by
current defined as Istart2 when this discharge event is
detected.
There is used a dedicated structure called ac line unplug
detector inside the X2 capacitor discharge control circuitry.
See the Figure 53 for the block diagram for this structure and
Figures 54, 55, 56 and 57 for the timing diagrams. The basic
idea of ac line unplug detector lies in comparison of the
direct sample of the high voltage obtained via the high
voltage sensing structure with the delayed sample of the high
voltage. The delayed signal is created by the sample & hold
structure.
The comparator used for the comparison of these signals
is without hysteresis inside. The resolution between the
slopes of the ac signal and dc signal is defined by the
sampling time TSAMPLE and additional internal offset NOS.
These parameters ensure the noise immunity as well. The
additional offset is added to the picture of the sampled HV
signal and its analog sum is stored in the C1 storage
capacitor. If the voltage level of the HV sensing structure
output crosses this level the comparator CMP output signal
resets the detection timer and no dc signal is detected. The
additional offset NOS can be measured as the VHV(hyst) on
the HV pin. If the comparator output produces pulses it
means that the slope of input signal is higher than set
resolution level and the slope is positive. If the comparator
output produces the low level it means that the slope of input
signal is lower than set resolution level or the slope is
negative. There is used the detection timer which is reset by
any edge of the comparator output. It means if no edge
comes before the timer elapses there is present only dc signal
or signal with the small ac ripple at the HV pin. This type of
the ac detector detects only the positive slope, which fulfils
the requirements for the ac line presence detection.
S min +
V HV(hyst),max
(eq. 1)
T sample
Than it can be derived the relationship between the
minimum detectable slope and the amplitude and frequency
of the sinusoidal input voltage:
V max +
V HV(hyst),max
2 @ p @ f @ T sample
+
5
2 @ p @ 35 @ 1 @ 10 −3 (eq. 2)
+ 22.7 V
The minimum detectable AC RMS voltage is 16 V at
frequency 35 Hz, if the maximum hysteresis is 5 V and
sampling time is 1 ms.
The X2 capacitor discharge feature is available in any
controller operation mode to ensure this safety feature. The
detection timer is reused for the time limiting of the
discharge phase, to protect the device against overheating.
The discharging process is cyclic and continues until the ac
line is detected again or the voltage across the X2 capacitor
is lower than VHV(min). This feature ensures to discharge
quite big X2 capacitors used in the input line filter to the safe
level. It is important to note that it is not allowed to
connect HV pin to any dc voltage due this feature. e.g.
directly to bulk capacitor.
During the HV sensing or X2 cap discharging the VCC net
is kept above the VCC(off) voltage by the Self−Supply in any
mode of device operation to supply the control circuitry.
During the discharge sequence is not allowed to start−up the
device.
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24
NCP1240
Figure 53. The ac Line Unplug Detector Structure Used for X2 Capacitor Discharge System
Figure 54. The ac Line Unplug Detector Timing Diagram
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25
NCP1240
Figure 55. The ac Line Unplug Detector Timing Diagram Detail with Noise Effects
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26
NCP1240
Figure 56. HV Pin ac Input Timing Diagram with X2 Capacitor Discharge Sequence When the Application is
Unplugged Under Extremely Low Line Condition
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NCP1240
Figure 57. HV Pin ac Input Timing Diagram with X2 Capacitor Discharge Sequence When the Application is
Unplugged Under High Line Condition
The Low Consumption Off Mode
Only the X2 cap discharge and Self−Supply features is
enabled in the low consumption off mode. The X2 cap
discharging feature is enable due the safety reasons and the
Self−Supply is enabled to keep the VCC supply, but only
very low VCC consumption appears in this mode. Any other
features are disabled in this mode.
The information about the latch status of the device is kept
in the low consumption off mode and this mode is used for
the TSD protection as well. The protection timer
GoToOffMode tGTOM is used to protect the application
against the false activation of the low consumption off mode
by the fast drop outs of the FB pin voltage below the 0.6 V
level. E.g. in case when is present high FB pin voltage ripple
during the skip mode.
There was implemented the low consumption off mode
allowing to reach extremely low no load input power as
described in previous chapters. If the voltage at feedback pin
decreases below the 0.6 V the controller enters the off mode.
The internal VCC is turned−off, the IC consumes extremely
low VCC current and only the voltage at external VCC
capacitor is maintained by the Self−Supply circuit. The
Self−Supply circuit keeps the VCC voltage at the VCC(reg)
level. The supply for the FB pin watch dog circuitry and FB
pin bias is provided via the low consumption current sources
from the external VCC capacitor. The controller can only
start, if the FB pin voltage increases above the 2.2 V level.
See Figure 58 for timing diagrams.
www.onsemi.com
28
NCP1240
Figure 58. Start−up, Shutdown and AC Line Unplug Time Diagram
Oscillator with Maximum On Time and Frequency
Jittering
The NCP1240 includes an oscillator that sets the
switching frequency 65 kHz or 100 kHz depending on the
version. The maximum on time is 12.3 ms (for 65 kHz
version) or 8 ms (for 100 kHz version) with an accuracy of
±7%. The maximum on time corresponds to maximum duty
cycle of the DRV pin is 80% at full switching frequency. In
order to improve the EMI signature, the switching frequency
jitters ±6 % around its nominal value, with a triangle−wave
shape and at a frequency of 125 Hz. This frequency jittering
is active even when the frequency is decreased to improve
the efficiency in light load condition.
Figure 59. Frequency Modulation of the Maximum
Switching Frequency
www.onsemi.com
29
NCP1240
Low Load Operation Modes: Frequency Foldback
Mode (FFM) and Skip Mode
VFB(foldS), and is complete when VFB reaches VFB(foldE).
The maximum on−time duration control is kept during the
frequency foldback mode to provide the natural transformer
core anti−saturation protection. The frequency jittering is
still active while the oscillator frequency decreases as well.
In order to improve the efficiency in light load conditions,
the frequency of the internal oscillator is linearly reduced
from its nominal value down to fOSC(min). This frequency
foldback starts when the voltage on FB pin goes below
Figure 60. Frequency Foldback Mode Characteristic
When the FB voltage reaches Vskip(in) while decreasing,
skip mode is activated: the driver stops, and the internal
consumption of the controller is decreased. While VFB is
below Vskip(out), the controller remains in this state; but as
soon as VFB crosses the skip out threshold, the DRV pin
starts to pulse again.
Figure 61. Skip Mode Timing Diagram
www.onsemi.com
30
NCP1240
Figure 62. Technique Preventing Short Pulses in Skip Mode
Clamped Driver
resulting voltage is applied to the CS pin. It is applied to one
input of the PWM comparator through a 250 ns LEB block.
On the other input the FB voltage divided by 5 sets the
threshold: when the voltage ramp reaches this threshold, the
output driver is turned off. The maximum value for the
current sense is 0.7 V, and it is set by a dedicated comparator.
Each time the controller is starting, i.e. the controller was
off and starts – or restarts – when VCC reaches VCC(on), a
soft−start is applied: the current sense setpoint is increased
by 15 discrete steps from 0 (the minimum level can be
higher than 0 because of the LEB and propagation delay)
until it reaches VILIM (after a duration of tSSTART), or until
the FB loop imposes a setpoint lower than the one imposed
by the soft−start (the two comparators outputs are OR’ed).
The supply voltage for the NCP1240 can be as high as
28 V, but most of the MOSFETs that will be connected to the
DRV pin cannot accept more than 20 V on their gate. The
driver pin is therefore clamped safely below 16 V. This
driver has a typical capability of 500 mA for source current
and 800 mA for sink current.
Current−Mode Control With Slope Compensation and
Soft−Start
NCP1240 is a current−mode controller, which means that
the FB voltage sets the peak current flowing in the
inductance and the MOSFET. This is done through a PWM
comparator: the current is sensed across a resistor and the
www.onsemi.com
31
NCP1240
Figure 63. Soft−Start Feature
In order to allow the NCP1240 to operate in CCM with a
duty cycle above 50%, the fixed slope compensation is
internally applied to the current−mode control. The slope
appearing on the internal voltage setpoint for the PWM
comparator is −32.5 mV/ms typical for the 65 kHz version,
and −50 mV/ms for the 100 kHz version. The slope
compensation can be observable as a value of the peak
current at CS pin.
The internal slope compensation circuitry uses a sawtooth
signal synchronized with the internal oscillator is subtracted
from the FB voltage divided by KFB.
Under some conditions, like a winding short−circuit for
instance, not all the energy stored during the on time is
transferred to the output during the off time, even if the on
time duration is at its minimum (imposed by the propagation
delay of the detector added to the LEB duration). As a result,
the current sense voltage keeps on increasing above VILIM,
because the controller is blind during the LEB blanking
time. Dangerously high current can grow in the system if
nothing is done to stop the controller. That’s what the
additional comparator, that senses when the current sense
voltage on CS pin reaches VCS(stop) ( = 1.5 x VILIM ), does:
the controller enters the protection mode as soon as this
comparator toggles four times consecutively.
www.onsemi.com
32
NCP1240
Figure 64. Slope Compensation Block Diagram
Figure 65. Slope Compensation Timing Diagram
Internal Overpower Protection
Unfortunately, due to the inherent propagation delay of
the logic, the actual peak current is higher at high input
voltage than at low input voltage, leading to a significant
difference in the maximum output power delivered by the
power supply.
The power delivered by a flyback power supply is
proportional to the square of the peak current in
discontinuous conduction mode:
P OUT +
1
@ h @ L P @ F SW @ I P
2
2
(eq. 3)
www.onsemi.com
33
NCP1240
Figure 66. Needs for Line Compensation For True Overpower Protection
would be in the same order of magnitude. Therefore the
compensation current is only added when the FB voltage is
higher than VFB(OPCE). However, because the HV pin is
being connected to ac voltage, there is needed an additional
circuitry to read or at least closely estimate the actual voltage
on the bulk capacitor.
To compensate this and have an accurate overpower
protection, an offset proportional to the input voltage is
added on the CS signal by turning on an internal current
source: by adding an external resistor in series between the
sense resistor and the CS pin, a voltage offset is created
across it by the current. The compensation can be adjusted
by changing the value of the resistor.
But this offset is unwanted to appear when the current
sense signal is small, i.e. in light load conditions, where it
Figure 67. Overpower Protection Current Relation to Feedback Voltage
www.onsemi.com
34
NCP1240
Figure 68. Overpower Protection Current Relation to Peak of Rectified Input Line AC voltage
HV
Positive slope
R1
Sample & Hold
CMP
Detection timer
DC detect
reset
Q1
Nos
R2
Lo frq OSC
OPC control
C1
Rfb1
Vfb(reg)
FB
Internal resitance 40k
Out sq
A/D 3 bit
Converter
+
Peak detector
3 bit
Register
FBbuffer
Vfb(opcf)
Ictrl
Division ratio 4
Rfb3
Rfb2
I generator
PWM_CMP
PWM
CS
LEB 250ns
Figure 69. Block Schematic of Overpower Protection Circuit
line unplug detector. The sensed HV pin voltage peak value
is validated when no HV edges from comparator are present
after last falling edge during two sample clocks. See
Figure 70 for details.
A 3 bit A/D converter with the peak detector senses the ac
input, and its output is periodically sampled and reset, in
order to follow closely the input voltage variations. The
sample and reset events are given by the output from the ac
www.onsemi.com
35
NCP1240
Overcurrent Protection with Fault timer
Other possibilities of the latch release are the brown−out
condition or the VCC power on reset. The timer is reset when
the CS setpoint goes back below VILIM before the timer
elapses. The fault timer is also started if the driver signal is
reset by the maximum on time. The controller also enters the
same protection mode if the voltage on the CS pin reaches
1.5 times the maximum internal setpoint VCS(stop) (allows to
detect winding short−circuits) or there appears low VCC
supply. See Figures 71 and 72 for the timing diagram.
In autorecovery mode if the fault has gone, the supply
resumes operation; if not, the system starts a new burst cycle.
The overload protection depends only on the current
sensing signal, making it able to work with any transformer,
even with very poor coupling or high leakage inductance.
When an overcurrent event occurs on the output of the
power supply, the FB loop asks for more power than the
controller can deliver, and the CS setpoint reaches VILIM.
When this event occurs, an internal tfault timer is started:
once the timer times out, DRV pulses are stopped and the
controller is either latched off (latched protection, options A
and E) or this latch is released by the autorecovery mode
(options B and F), the controller tries to restart after tautorec.
www.onsemi.com
36
NCP1240
VHVSAMPLE
TSAMPLE
VHV(hyst)
time
1st HV edge
resets the watch
dog and starts
the peak
detection of HV
pin signal
Comparator
Output
time
Sample clock
time
Watch dog
signal
2nd sample clock
pulse after last
HV edge initiates
the watch dog
signal
2nd sample clock
pulse after last
HV edge initiates
the watch dog
signal
time
Peak detector
Reset
Reset
Sample
Sample
time
IOPC
time
Figure 70. Overpower Compensation Timing Diagram
www.onsemi.com
37
NCP1240
PROTECTION MODES AND THE LATCH MODE RELEASES
Event
Timer Protection
Next Device Status
Release to Normal Operation Mode
Overcurrent
VILIM > 0.7 V
Fault timer
Latch
Autorecovery – B and F versions
Brown−out
VCC < VCC(reset)
Peak power
VILIM > 0.5 V
Transient timer
Latch
Autorecovery – B and F versions
Brown−out
VCC < VCC(reset)
Maximum on time
Fault timer
Latch
Autorecovery – B and F versions
Brown−out
VCC < VCC(reset)
Winding short
Vsense > VCS(stop)
4consecutive pulses
Latch
Autorecovery – B and F versions
Brown−out
VCC < VCC(reset)
Low supply
VCC < VCC(off)
10 ms timer
Latch
Autorecovery – B and F versions
Brown−out
VCC < VCC(reset)
External OTP, OVP
55 ms (35 ms at 100 kHz)
Latch
Brown−out
VCC < VCC(reset)
High supply
VCC > VCC(ovp)
10 ms timer
Latch
Brown−out
VCC < VCC(reset)
Brown−out
VHV < VHV(stop)
HV timer
Device stops
(VHV > VHV(start)) & (VCC > VCC(on))
Internal TSD
10 ms timer
Device stops, HV start−up
current source stops
(VHV > VHV(start)) & (VCC > VCC(on)) & TSDb
Off mode
VFB < VOFF
150 ms timer (NCP1240A/B)
500 ms timer (NCP1240E/F)
Device stops and internal
VCC is turned off
(VHV > VHV(start)) & (VCC > VCC(on)) &
(VFB > VON)
www.onsemi.com
38
NCP1240
VCC(on)
VCC(min)
Figure 71. Latched Timer−Based Overcurrent Protection (Options A/E)
www.onsemi.com
39
NCP1240
VCC(on)
VCC(min)
Figure 72. Timer−Based Protection Mode with Autorecovery Release from Latch−off (Options B/F)
Duel−Level Overcurrent Protection
comparator whose threshold is VCS(tran), a CS voltage level
lower than VILIM, which starts the counting of another timer,
with a duration ttran longer than tfault (6 s is the typical value).
If the timer reaches its maximum duration, the controller
enters protection mode which is latched or autorecovery
released depending on the option.
For some applications (e.g. limited power supplies), it is
necessary that the controller maintains regulation while it
has detected a first level of overload. This is to authorize a
transient peak power higher than the maximum continuous
output power. This is implemented by adding another
www.onsemi.com
40
NCP1240
Figure 73. Too Long Transient Peak Power Delivery
If the conditions change from transient power delivery to
overload, the overload timer starts to count. The timing
diagram could look like the one in Figure 74.
www.onsemi.com
41
NCP1240
Figure 74. Transient Peak Power Followed by Overload
www.onsemi.com
42
NCP1240
Latch−Off Input
Figure 75. Latch Detection Schematic
The Latch pin is dedicated to the latch−off function: it
includes two levels of detection that define a working
window, between a high latch and a low latch: within these
two thresholds, the controller is allowed to run, but as soon
as either the low or the high threshold is crossed, the
controller is latched off. The lower threshold is intended to
be used with an NTC thermistor, thanks to an internal current
source INTC.
An active clamp prevents the voltage from reaching the
high threshold if it is only pulled up by the INTC current. To
reach the high threshold, the pull−up current has to be higher
than the pull−down capability of the clamp (typically
1.5 mA at VOVP).
To avoid any false triggering, spikes shorter than 50 ms
(for the high latch and 65 kHz version) or 350 ms (for the low
latch) are blanked and only longer signals can actually latch
the controller.
C LATCH
max +
t SSTART
Reset occurs when a brown−out condition is detected or
the VCC is cycled down to a reset voltage, which in a real
application can only happen if the power supply is
unplugged from the ac line.
Upon startup, the internal references take some time
before being at their nominal values; so one of the
comparators could toggle even if it should not. Therefore the
internal logic does not take the latch signal into account
before the controller is ready to start: once VCC reaches
VCC(on), the latch pin High latch state is taken into account
and the DRV switching starts only if it is allowed; whereas
the Low latch (typically sensing an over temperature) is
taken into account only after the soft−start is finished. In
addition, the NTC current is doubled to INTC(SSTART) during
the soft−start period, to speed up the charging of the Latch
pin capacitor. The maximum value of Latch pin capacitor is
given by the following formula (The standard start−up
condition is considered and the NTC current is neglected):
min @ I NTC(SSTART) min
V clamp0
min
+
8.0 @ 10 −3 @ 130 @ 10 −6
F + 1.04 mF (eq. 4)
1.0
www.onsemi.com
43
NCP1240
VCC(on)
VCC(min)
Figure 76. Latch Timing Diagram
Temperature Shutdown
low power consumption. There is kept the VCC supply to
keep the TSD information. When the temperature falls
below the low threshold, the start−up of the device is enabled
again, and a regular start−up sequence takes place. See the
status diagrams at the Figures 46 and 47.
The NCP1240 includes a temperature shutdown
protection with a trip point typically at 150°C and the typical
hysteresis of 30°C. When the temperature rises above the
high threshold, the controller stops switching
instantaneously, and goes to the off mode with extremely
ORDERING INFORMATION
Ordering Part No.
Overload Protection
NCP1240AD065R2G
Latched
NCP1240BD065R2G
Autorecovery
NCP1240ED065R2G
Latched
NCP1240FD065R2G
Autorecovery
NCP1240AD100R2G
Latched
NCP1240BD100R2G
Autorecovery
Switching Frequency
Package
Shipping†
65 kHz
SOIC−7
(Pb−Free)
2500 / Tape & Reel
65 kHz
SOIC−7
(Pb−Free)
2500 / Tape & Reel
100 kHz
SOIC−7
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
44
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−7
CASE 751U−01
ISSUE E
DATE 20 OCT 2009
SCALE 1:1
−A−
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B ARE DATUMS AND T
IS A DATUM SURFACE.
4. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
5. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5
−B− S
0.25 (0.010)
B
M
M
1
4
G
C
R
X 45 _
J
−T−
SEATING
PLANE
H
0.25 (0.010)
K
M
D 7 PL
M
T B
S
A
DIM
A
B
C
D
G
H
J
K
M
N
S
INCHES
MIN MAX
0.189 0.197
0.150 0.157
0.053 0.069
0.013 0.020
0.050 BSC
0.004 0.010
0.007 0.010
0.016 0.050
0_
8_
0.010 0.020
0.228 0.244
S
GENERIC
MARKING DIAGRAM
SOLDERING FOOTPRINT*
8
1.52
0.060
7.0
0.275
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
1
XXX
A
L
Y
W
G
4.0
0.155
0.6
0.024
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
1.270
0.050
SCALE 6:1
XXXXX
ALYWX
G
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
98AON12199D
DESCRIPTION:
7−LEAD SOIC
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−7
CASE 751U−01
ISSUE E
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6.
7. NOT USED
8. EMITTER
DATE 20 OCT 2009
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. NOT USED
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. NOT USED
8. SOURCE, #1
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5.
6.
7. NOT USED
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6.
7. NOT USED
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. NOT USED
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR (DIE 1)
2. BASE (DIE 1)
3. BASE (DIE 2)
4. COLLECTOR (DIE 2)
5. COLLECTOR (DIE 2)
6. EMITTER (DIE 2)
7. NOT USED
8. COLLECTOR (DIE 1)
STYLE 9:
PIN 1. EMITTER (COMMON)
2. COLLECTOR (DIE 1)
3. COLLECTOR (DIE 2)
4. EMITTER (COMMON)
5. EMITTER (COMMON)
6. BASE (DIE 2)
7. NOT USED
8. EMITTER (COMMON)
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. NOT USED
8. GROUND
STYLE 11:
PIN 1. SOURCE (DIE 1)
2. GATE (DIE 1)
3. SOURCE (DIE 2)
4. GATE (DIE 2)
5. DRAIN (DIE 2)
6. DRAIN (DIE 2)
7. NOT USED
8. DRAIN (DIE 1)
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. NOT USED
8. COMMON CATHODE
DOCUMENT NUMBER:
98AON12199D
DESCRIPTION:
7−LEAD SOIC
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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