NCP1249CD65R2G

NCP1249C, NCP1249D High-Voltage Current­Mode PWM Controller Featuring Peak Power Excursion and Self-Relaxing Off Mode http://onsemi.com The NCP1249 is a highly integrated high−voltage PWM controller capable of delivering a rugged and high performance offline power supply with extremely low no−load consumption. With a supply range up to 30 V, the controller hosts a jittered 65 kHz switching circuitry operated in peak current mode control. When the power on the secondary side starts to decrease, the controller automatically folds back its switching frequency down to a minimum level of 26 kHz. As the power further goes down, the part enters skip cycle while freezing the peak current setpoint. To help build rugged converters, the controller features several key protective features: a internal brown−out, a non−dissipative Over Power Protection for a constant maximum output current regardless of the input voltage and two latched over voltage protection inputs − either through a dedicated pin or via the VCC input. The controller architecture is arranged to authorize a transient peak power excursion when the peak current hits the limit. At this point, the switching frequency is increased from 65 kHz to 130 kHz until the peak requirement disappears. The timer duration is then modulated as the converter crosses a peak power excursion mode (long) or undergoes a short circuit (short). MARKING DIAGRAM 1 1 XXXXX A L Y W G • • • • • • • • = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package PIN CONNECTIONS X2 FB/REM OPP/Latch Timer • High−Voltage Current Source for Lossless Start−up Sequence • Automatic and Lossless X2 Capacitors Discharge Function • 65 kHz Fixed−Frequency Current−Mode Control Operation with • NCP1249x65 ALYW G SOIC−9 NB D SUFFIX CASE 751BP Features 130 kHz Excursion Internal and Adjustable Over Power Protection (OPP) Circuit Internal Brown−Out Protection Circuit Frequency Foldback Down to 26 kHz and Skip−Cycle in Light Load Conditions Adjustable Ramp Compensation Internally Fixed 4 ms Soft−Start Adjustable Timer-Based Auto−Recovery Overload/Short−Circuit Protection 100% to 25% Timer Reduction from Overload to Short−Circuit Fault Frequency Jittering in Normal and Frequency Foldback Modes Latched OVP Input for Improved Robustness and Latched OVP on VCC 9 9 1 HV VCC DRV GND (Top View) • Up to 30 V VCC Maximum Rating • +300 mA/ −500 mA Source/Sink Drive Capability • Extremely Low No−Load Standby Power via Controlled Self−Relaxing Off Mode • Option for Auto−Recovery or Latched Short−Circuit Protection • Internal Thermal Shutdown with Hysteresis • These are Pb−Free Devices Typical Applications • Converters Requiring Peak−power Capability such as Printers Power Supplies, ac−dc Adapters for Game Stations ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2013 September, 2013 − Rev. 0 1 Publication Order Number: NCP1249C/D NCP1249C, NCP1249D Vbulk Vout . L1 . L2 OVP . L1 1 L2 2 OPP 10 9 3 8 4 7 5 6 NCP1249 ramp comp. Figure 1. Typical Application Example Table 1. PIN FUNCTIONS Pin No Pin Name Function Pin Description 1 X2 X2-capacitors discharge When the voltage on this pin disappears, the controller ensures the X2−capacitors discharge. 2 FB/REM Combined feedback and remote pin Connecting an opto-coupler to this pin allows regulation. The opto−coupler can pull the feedback pin down and brings the controller in a deep sleep mode. 3 CS Current sense + ramp compensation This pin monitors the primary peak current but also offers a means to introduce slope compensation. 4 OPP/LATC H Adjust the Over Power Protection Latches off the part A resistive divider from the auxiliary winding to this pin sets the OPP compensation level. When brought above 3 V, the part is fully latched off. 5 TIMER Fault timer adjustment A resistor to ground adjusts the timer duration in fault condition. 6 GND - The controller ground. 7 DRV Driver output The driver’s output to an external MOSFET gate. 8 VCC Supplies the controller This pin is connected to an external auxiliary voltage and supplies the controller. When above a certain level, the part fully latches off. 9 NC - Increases insulation distance between high and low voltage pins. 10 HV High-voltage input This pin provides a charging current during start−up and auto−recovery faults but also a means to efficiently discharge the input X2 capacitors. Table 2. OPTIONS AND ORDERING INFORMATION Device Overload Protection Switching Frequency Peak Frequency Package Shipping† NCP1249CD65R2G Latched 65 kHz 130 kHz SOIC−9 (Pb−Free) 2500 / Tape & Reel NCP1249DD65R2G Autorecovery 65 kHz 130 kHz SOIC−9 (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging. Specifications Brochure, BRD8011/D. http://onsemi.com 2 NCP1249C, NCP1249D HV X2 X2 timer BO_bias en TSD Vrem BO_OK Rem Integrated BO sensor FB X2_dis FB_Ipull Vcc and logic management OPP/ LATCH 600−ns time constant OVP gone? Vdd 100% to 25% change power on reset RST 4 Vcc Vref SC VOVP Up counter Vlatch UVLO hiccup Vcc 20 us Upper / lower limit option latch/AR Ct S Q IpFlag, PON reset Q VCC 1 us blanking R Rlimit X2_dis Rst if Vcc < 3 V 65 kHz clock Jitter mod. The BO signal serves as: − a general reset − a reset to the latch mode TIMER Clamp BO_OK S Q Q R Frequency Frequency foldback increase to DRV 130 kHz VFswp Vfold Vskip Rramp vdd HV_leak FB_Ipull RFB /4 SC 4 ms SS The soft−start is activated during: − the startup sequence − the auto−recovery burst mode VSC VFB < 1 V ? setpoint = 250 mV FB/REM FB CS Ip flag VOPP LEB + 250 mV peak current freeze Vlimit + VOPP GND Vlimit Figure 2. Internal Circuit Architecture http://onsemi.com 3 NCP1249C, NCP1249D Table 3. MAXIMUM RATINGS TABLE Symbol Rating Value Unit VCC Power Supply voltage, VCC pin, continuous voltage −0.3 to 30 V VHV High Voltage (HV) Pin (pin 10) –0.3 to 500 V Vpin_x Maximum voltage on low power pins (X2, CS, OPP, Timer) −0.3 to 10 V VFB/REM Maximum voltage on FB/REM pin −0.3 to 5 V VDRV Maximum voltage on drive pin −0.3 to VCC + 0.3 V IOPP Maximum injected current into the OPP pin −2 mA RθJ−A Thermal Resistance Junction−to−Air 211 °C/W TJ,max Maximum Junction Temperature 150 °C Storage Temperature Range −60 to +150 °C ESD Capability, HBM model (All pins except HV) per JEDEC standard JESD22, Method A114E 2 kV ESD Capability, Machine Model per JEDEC standard JESD22, Method A115A 200 V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78. Table 4. ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted) Rating Pin Min Typ Max Unit Minimum voltage for current source operation (VCC = 4 V) 10 − 30 60 V Istart1 Current flowing out of VCC pin (VCC = 0 V) 8, 10 0.2 0.7 1 mA Istart2 Current flowing out of VCC pin (VCC = VCC_ON – 0.5 V) 8, 10 6 10 16 mA VCC_inhibit VCC level for Istart1 to Istart2 transition 8 0.5 1 1.25 V Istart_off Off−state leakage current (VHV = 500 V, VCC = 15 V) 10 − 15 − mA IHV_off*mode_1 HV pin leakage current when off−mode is active (VHV = 141 V) 10 − − 15 mA IHV_off*mode_2 HV pin leakage current when off−mode is active (VHV = 325 V) 10 − − 19 mA VHV_min_off−mode Minimum voltage on HV pin during off−mode (VFB = 0 V, VCC = 0 V) 10 − − 10 V VCC_ON VCC increasing level at which driving pulses are authorized 8 16 18 20 V VCC_OFF VCC decreasing level at which driving pulses are stopped 8 9.5 10 11 V VCC_HYST Hysteresis VCC_ON − VCC_OFF 8 6 − − V VCC_bias VCC level during a fault 8 4.7 5.5 6.5 V ICC1 Symbol HV STARTUP CURRENT SOURCE VHV_min SUPPLY SECTION Internal IC consumption with IFB = 75 mA, fSW = 65 kHz and CL = 0 8 − 1.6 2.6 mA ICC2 Internal IC consumption with IFB = 75 mA, fSW = 65 kHz and CL = 1 nF 8 − 2.3 3.4 mA ICC3 Internal IC consumption with IFB = 75 mA, fSW = 130 kHz and CL = 0 8 − 1.9 2.9 mA ICC4 Internal IC consumption with IFB = 75 mA, fSW = 130 kHz and CL = 1 nF 8 − 3.3 4.4 mA ICC_skip Internal IC consumption while in skip mode 8 660 960 1360 mA ICC_latch Internal IC consumption during Latch*off mode 8 − 350 520 mA Brown−Out turn−on threshold (VHV going up) 10 92 101 110 V BROWN−OUT V_BO_on 2. Guaranteed by design 3. See characterization table for linearity over negative bias voltage – we recommend keeping the level on pin 5 below −300 mV. 4. A 1 MW resistor is connected from pin 4 to the ground for the measurement. http://onsemi.com 4 NCP1249C, NCP1249D Table 4. ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted) Symbol Rating Pin Min Typ Max Unit V_BO_off Brown−Out turn−off threshold (VHV going down) 10 84 93 102 V BO_Timer Timer duration for line cycle drop−out 10 40 − 100 ms Vth_X2 X2 timer disable switch threshold voltage 1 1 1.5 2 V Vth_X2_hyst Hysteresis on the X2 pin 1 − 100 − mV V_X2_clamp X2 input clamp voltage 1 − 4 − V X2_Timer X2 timer duration 1 70 − 140 ms I_X2_leak X2 input leakage current (V_X2 = 2.5 V) 1 − − 0.3 mA I_X2_dis Maximum discharge switch current (VCC = 10 V) 10 6 10 13 mA Tr Output voltage rise−time @ CL = 1 nF, 10−90% of output signal 7 − 40 80 ns Tf Output voltage fall−time @ CL = 1 nF, 10−90% of output signal 7 − 30 70 ns ROH Source resistance 7 − 13 − W ROL Sink resistance 7 − 6 − W Isource Peak source current, VGS = 0 V (Note 2) 7 300 mA Isink Peak sink current, VGS = 12 V (Note 2) 7 500 mA VDRV_low DRV pin level at VCC close to VCC_OFF with a 33 kW resistor to GND 7 8 − − V VDRV_high DRV pin level at VCC= VOVP −0.2 V, DRV unloaded 7 10 12 14 V IIB Input Bias Current @ 0.8 V input level on pin 3 3 Vlimit Maximum internal current setpoint – TJ = 25°C – pin 4 grounded 3 0.744 0.8 0.856 V Vlimit Maximum internal current setpoint – TJ from −40°C to 125°C – pin 4 grounded 3 0.72 0.8 0.88 V Vfold_cs Default internal voltage set point for frequency foldback trip point ≈ 47% of Vlimit 3 475 Vfreeze_cs Internal peak current setpoint freeze (≈31% of Vlimit) 3 250 TDEL Propagation delay from current detection to gate off−state 3 100 TLEB Leading Edge Blanking Duration 3 300 ns TSS Internal soft−start duration activated upon startup, auto−recovery − 4 ms IOPPo Setpoint decrease for pin 5 biased to –250 mV – (Note 3) 3 31.3 % IOOPv Voltage setpoint for pin 5 biased to −250 mV – (Note 3) TJ from −40°C to 125°C 3 IOPPs Setpoint decrease for pin 4 grounded 3 Oscillation frequency, VFB < VFBtrans, pin 4 grounded − BROWN−OUT X2 DISCHARGE CIRCUITRY DRIVE OUTPUT CURRENT COMPARATOR 0.02 0.5 0.55 mA mV mV 150 0.62 0 ns V % INTERNAL OSCILLATOR fOSC_nom 57 65 71 kHz VFBtrans Feedback voltage above which fsw increases 2 fOSC_max Maximum oscillation frequency for VFB above VFBmax − 115 130 3.2 140 kHz V VFBmax Feedback voltage above which fsw is constant 2 3.8 4 4.2 V Dmax Maximum duty ratio − 76 80 84 % 2. Guaranteed by design 3. See characterization table for linearity over negative bias voltage – we recommend keeping the level on pin 5 below −300 mV. 4. A 1 MW resistor is connected from pin 4 to the ground for the measurement. http://onsemi.com 5 NCP1249C, NCP1249D Table 4. ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted) Symbol Rating Pin Min Typ Max Unit fjitter Frequency jittering in percentage of fOSC − ±5 % fswing Swing frequency over the whole frequency range − 240 Hz 17 kW INTERNAL OSCILLATOR FEEDBACK / REMOTE SECTION Rup(FB) Internal pull−up resistor 2 Req Equivalent ac resistor from FB to GND 2 Iratio Pin 2 to current setpoint division ratio 2,3 Vfreeze_FB Feedback voltage below which the peak current is frozen V_REM_off Feedback voltage below which the part enters into off−mode V_REM_on Feedback voltage above which is the off−mode deactivated 2 IFBREM Feedback current that lifts the feedback pin upon off−mode exit 10 15 20 kW 4 − 2 1 V 2 0.4 V 1.5 2 2.5 V 2 2.4 4 μA 1.9 FREQUENCY FOLDBACK Vfold_FB Frequency foldback level on the feedback pin – ≈47% of maximum peak current 2 ftrans Transition frequency below which skip−cycle occurs − Vfold_end End of frequency foldback feedback level, fsw = fmin 2 1.5 V Vskip Skip−cycle level voltage on the feedback pin 2 400 mV Skip hysteresis Hysteresis on the skip comparator (Note 2) 2 30 mV 22 26 V 30 kHz INTERNAL SLOPE COMPENSATION Vramp Internal ramp level @ 25°C (Note 4) 3 2.5 V Rramp Internal ramp resistance to CS pin 3 20 kW Latching level input 4 PROTECTIONS Vlatch 2.7 3 3.3 V Tlatch−blank Blanking time after drive turn off 4 1 ms Tlatch−count Number of clock cycles before latch confirmation − 4 − Tlatch−del OVP detection time constant 4 600 ns VOVL Feedback voltage at which an overload is considered – OPP pin is grounded 2 3.2 V VSC Feedback voltage above which a short−circuit is considered 2 3.9 4.1 4.3 V Timer1 Fault timer duration for a 22 kW resistor from pin 5 to ground − overload 5 350 500 650 ms Timer2 Fault timer duration when VFB > 4.1 V is Timer1/4 – short−circuit condition 5 88 125 162 ms Timer_fault1 Timer duration when pin 5 is shorted to ground – fault condition 5 50 ms Timer_fault2 Timer duration when pin 5 is open – fault condition 5 1000 ms VOVP Latched Over voltage protection on the VCC rail 8 TOVP_del Delay before OVP on VCC confirmation 8 TA−rec_timer Auto−recovery timer duration − TTSD Temperature shutdown TJ going up − 150 °C TTSD(HYS) Temperature shutdown hysteresis − 30 °C 26 1.4 27.5 29 V 20 30 ms − − s TEMPERATURE SHUTDOWN 2. Guaranteed by design 3. See characterization table for linearity over negative bias voltage – we recommend keeping the level on pin 5 below −300 mV. 4. A 1 MW resistor is connected from pin 4 to the ground for the measurement. http://onsemi.com 6 NCP1249C, NCP1249D TYPICAL CHARACTERISTICS 0.9 24.0 23.0 0.8 Istart1 (mA) VHV_min (V) 22.0 21.0 20.0 19.0 0.7 0.6 18.0 17.0 −40 −25 10 5 20 35 50 65 80 95 0.5 −40 −25 110 125 10 5 20 35 50 65 80 95 110125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 3. Minimum Current Source Operation, VHV_min Figure 4. High Voltage Startup Current Flowing Out of VCC Pin, Istart1 13 13 Istart_off (mA) Istart2 (mA) 12 11 12 11 10 9 −40 −25 10 5 20 35 50 65 80 95 10 −40 −25 110 125 10 5 20 35 50 65 80 95 110125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 5. High Voltage Startup Current Flowing Out of VCC Pin, Istart2 Figure 6. Off−state Leakage Current, Istart_off 12.0 14.0 11.5 13.0 Ihv_off−mode_2 (mA) Ihv_off−mode_1 (mA) 11.0 10.5 10.0 9.5 9.0 12.0 11.0 8.5 8.0 −40 −25 10 5 20 35 50 65 80 95 110 125 10.0 −40 −25 10 5 20 35 50 65 80 95 110125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 7. HV Pin Current during Off−mode, IHV_off_mode_1 Figure 8. HV Pin Current during Off−mode, IHV_off_mode_2 http://onsemi.com 7 NCP1249C, NCP1249D TYPICAL CHARACTERISTICS 18.0 10.2 10.1 VCC_OFF (V) VCC_ON (V) 17.8 17.6 17.4 10.0 9.9 17.2 17.0 −40 −25 −10 5 20 35 50 65 80 9.8 −40 −25 −10 95 110 125 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 9. VCC Increasing Level at which Driving Pulses are Authorized, VCC_ON Figure 10. VCC Decreasing Level at which Driving Pulses are Stopped, VCC_OFF 8.0 8.0 7.5 7.0 VCC_bias (V) VCC_HYST (V) 7.8 7.6 7.4 6.5 6.0 5.5 5.0 7.2 4.5 7.0 −40 −25 −10 5 20 35 50 65 80 4.0 −40 −25 −10 95 110 125 20 35 50 65 80 95 110 125 TEMPERATURE (°C) Figure 11. VCC Hysteresis, VCC_HYST Figure 12. VCC Level at Fault Modes, VCC_bias 1.10 400 350 ICC_latch (mA) 1.00 VCC_inhibit (V) 5 TEMPERATURE (°C) 0.90 0.80 300 250 200 0.70 −40 −25 −10 5 20 35 50 65 80 150 −40 −25 −10 95 110 125 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 13. VCC Level for Istart1 to Istart2 Transition, VCC_inhibit Figure 14. Internal IC Consumption During Latch−off Mode, ICC_latch http://onsemi.com 8 NCP1249C, NCP1249D 110.0 95.00 108.0 93.00 V_BO_off (V) V_BO_on (V) TYPICAL CHARACTERISTICS 106.0 104.0 102.0 100.0 91.00 89.00 87.00 −40 −25 −10 5 20 35 50 65 80 85.00 −40 −25 −10 95 110 125 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 15. Brown−Out Turn−on Threshold, V_BO_on Figure 16. Brown−Out Turn−off Threshold, V_BO_off 1.8 4.50 1.7 V_X2_clamp (V) Vth_X2 (V) 1.6 1.5 1.4 1.3 4.00 3.50 1.2 1.1 1.0 −40 −25 −10 5 20 35 50 65 80 3.00 −40 −25 −10 95 110 125 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 17. X2 Timer Disable Switch Threshold, Vth_X2 Figure 18. X2 Input Clamp Voltage, V_X2_clamp 11.0 1.5 10.5 1.4 10.0 V_REM_on (V) IX2_dis (mA) 5 9.5 9.0 1.3 1.2 1.1 8.5 8.0 −40 −25 −10 5 20 35 50 65 80 1.0 −40 −25 −10 95 110 125 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 19. Maximum X2 Cap Discharge Current, I_X2_dis Figure 20. Off−mode Turn−off Threshold, V_REM_on http://onsemi.com 9 NCP1249C, NCP1249D TYPICAL CHARACTERISTICS 0.5 4.0 R_SW_REM (W) V_REM_off (V) 3.0 0.4 0.3 2.0 1.0 5 20 35 50 65 80 0.0 −40 −25 −10 95 110 125 20 35 50 65 80 95 110 125 TEMPERATURE (°C) Figure 21. Off−mode Turn−on Threshold, V_REM_off Figure 22. Internal Remote Pull Down Switch Resistance, R_SW_REM 55 40 50 35 45 40 30 25 35 −40 −25 −10 5 20 35 50 65 80 20 −40 −25 −10 95 110 125 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 23. Output Voltage Rise−time, Tr Figure 24. Output Voltage Fall−time, Tf 16 11 10 15 ROH (W) 9 ROL (W) 5 TEMPERATURE (°C) Tf (ns) Tr (ns) 0.2 −40 −25 −10 8 14 13 7 12 6 5 −40 −25 −10 5 20 35 50 65 80 95 110 125 11 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 25. Source Resistance, ROL Figure 26. Sink Resistance, ROH http://onsemi.com 10 NCP1249C, NCP1249D TYPICAL CHARACTERISTICS 14.0 11.0 13.5 VDRV_high (V) VDRV_low (V) 10.5 10.0 13.0 12.5 12.0 9.5 11.5 5 20 35 50 65 80 11.0 −40 −25 −10 95 110 125 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 27. DRV Pin Level at VCC Close to VCC_OFF, VDRV_low Figure 28. DRV Pin Level at VCC Close to VOVP, VDRV_high 0.85 500.0 0.83 490.0 Vfold_CS (mV) Vlimit (V) 9.0 −40 −25 −10 0.81 0.79 0.77 480.0 470.0 460.0 0.75 −40 −25 −10 5 20 35 50 65 80 95 450.0 −40 −25 −10 110 125 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 29. Maximum Internal Current Set−point, Vlimit Figure 30. Default Internal Voltage Set Point for Frequency Foldback, Vfold_CS 55 250.0 248.0 53 246.0 Vfreeze_CS (mV) 244.0 TDEL (ns) 242.0 240.0 238.0 51 49 236.0 47 234.0 232.0 230.0 −40 −25 −10 5 20 35 50 65 80 95 110 125 45 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 31. Internal Peak Current Set−point Freeze, Vfreeze_CS Figure 32. Propagation Delay from Current Detection to Gate Off−state, TDEL http://onsemi.com 11 NCP1249C, NCP1249D TYPICAL CHARACTERISTICS 330 4.3 4.2 310 Tss (ms) TLEB (ns) 320 300 4.0 290 280 −40 −25 −10 5 20 35 50 65 80 95 3.9 −40 −25 −10 110 125 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 33. Leading Edge Blanking Duration, TLEB Figure 34. Internal Soft−start Duration, TSS 0.600 31.0 30.5 0.580 30.0 IOPPv (V) IOPPo (%) 0.560 0.540 29.5 29.0 0.520 28.5 0.500 −40 −25 −10 5 20 35 50 65 80 95 110 125 28.0 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 35. CS Voltage Setpoint for OPP, IOPPv Figure 36. Set−point Decrease for OPP, IOPPo 71.0 140.0 69.0 135.0 fOSC_max (Hz) fOSC_nom (Hz) 4.1 67.0 65.0 130.0 125.0 63.0 61.0 −40 −25 −10 5 20 35 50 65 80 95 110 125 120.0 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 37. Oscillation Frequency, fOSC_nom Figure 38. Maximum Oscilation Frequency, fOSC_max http://onsemi.com 12 NCP1249C, NCP1249D 80.0 250.0 79.8 240.0 79.6 230.0 fswing (Hz) Dmax (%) TYPICAL CHARACTERISTICS 79.4 79.2 210.0 5 20 35 50 65 80 200.0 −40 −25 −10 95 110 125 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 39. Maximum Duty−cycle, Dmax Figure 40. Swing Frequency, fswing 14.0 4.10 13.5 4.05 Iratio (−) Req (kW) 79.0 −40 −25 −10 13.0 12.5 4.00 3.95 12.0 −40 −25 −10 5 20 35 50 65 80 3.90 −40 −25 −10 95 110 125 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 41. Equivalent ac Resistor from FB to GND, Req Figure 42. FB to Current Set−point Division Ratio, Iratio 2.00 26.5 1.95 26.0 ftrans (Hz) Vfold_FB (V) 220.0 1.90 1.85 25.5 25.0 1.80 −40 −25 −10 5 20 35 50 65 80 95 110 125 24.5 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 43. Frequency Foldback Level, Vfold_FB Figure 44. Transition Frequency Below Which Skip−cycle Occurs, ftrans http://onsemi.com 13 NCP1249C, NCP1249D TYPICAL CHARACTERISTICS 3.10 420.00 415.00 3.08 3.06 Vlatch (V) Vskip (mV) 410.00 405.00 3.04 400.00 3.02 395.00 390.00 −40 −25 −10 5 20 35 50 65 80 95 110 125 3.00 −40 −25 −10 35 50 65 80 95 110 125 TEMPERATURE (°C) Figure 45. Skip−cycle Level Voltage on the Feedback Pin, Vskip Figure 46. Latching Level Input, Vlatch 21.0 20.5 TOVP_del (ms) 27.3 VOVP (V) 20 TEMPERATURE (°C) 27.5 27.1 26.9 26.7 20.0 19.5 19.0 18.5 26.5 −40 −25 −10 5 20 35 50 65 80 18.0 −40 −25 −10 95 110 125 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 47. Over Voltage Protection on VCC Rail, VOVP Figure 48. OVP Detection Time Constant, TOVP_del 580.0 140.0 560.0 135.0 Timer2 (ms) Timer1 (ms) 5 540.0 520.0 130.0 125.0 500.0 480.0 −40 −25 −10 5 20 35 50 65 80 95 110 125 120.0 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 49. Fault Timer Duration − Overload, Timer1 Figure 50. Fault Timer Duration − Short−circuit Condition, Timer2 http://onsemi.com 14 NCP1249C, NCP1249D TYPICAL CHARACTERISTICS 1200 60.0 1180 1160 Timer_fault2 (ms) Timer_fault1 (ms) 55.0 50.0 45.0 1140 1120 1100 1080 1060 1040 1020 5 20 35 50 65 80 1000 −40 −25 −10 95 110 125 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 51. Fault Timer Duration when Pin 5 is Shorted to Ground − Fault Condition, Timer_fault1 Figure 52. Fault Timer Duration when Pin 5 is Open − Fault Condition, Timer_fault2 2.2 2.9 2.1 2.8 ICC2 (mA) ICC1 (mA) 40.0 −40 −25 −10 2.0 1.9 2.7 2.6 1.8 −40 −25 −10 5 20 35 50 65 80 2.5 −40 −25 −10 95 110 125 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 53. Internal IC Consumption, ICC1 Figure 54. Internal IC Consumption, ICC2 3.6 2.2 2.1 ICC4 (mA) ICC3 (mA) 3.5 2.0 3.4 1.9 1.8 −40 −25 −10 5 20 35 50 65 80 95 110 125 3.3 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 55. Internal IC Consumption, ICC3 Figure 56. Internal IC Consumption, ICC4 http://onsemi.com 15 NCP1249C, NCP1249D TYPICAL CHARACTERISTICS 1.1 ICC_skip (mA) 1 0.9 0.8 0.7 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) Figure 57. Internal IC Consumption during Skip Mode, ICC_skip http://onsemi.com 16 NCP1249C, NCP1249D APPLICATION INFORMATION • Current−mode operation with internal slope Introduction The NCP1249 implements a standard current mode architecture where the switch−off event is dictated by the peak current setpoint. This component represents the ideal candidate where low part−count and cost effectiveness are the key parameters, particularly in low−cost ac−dc adapters, open−frame power supplies etc. The NCP1249 brings all the necessary components normally needed in today modern power supply designs, bringing several enhancements such as a non−dissipative OPP, a brown−out protection or peak power excursion for loads exhibiting variations over time. Accounting for the new needs of extremely low standby power requirements, the part includes an automatic X2−capacitor discharge circuitry that prevents the designer from installing power−consuming resistors across the front−end filtering capacitors. The controller is also able to enter a deep sleep mode via combined for feedback/remote pin. • High−Voltage start−up: low standby power results cannot be obtained with the classical resistive start−up network. In this part, a high−voltage current−source provides the necessary current at start−up and turns off afterwards. • Internal Brown−Out protection: a portion of the bulk voltage is internally sensed via the high−voltage pin monitoring (pin 10). When the voltage on this pin is too low, the part stops pulsing. No re−start attempt is made until the controller senses that the voltage is back within its normal range. When the brown−out comparator senses the voltage is acceptable, it sends a general reset to the controller (de−latch occurs) and authorizes to re−start. • X2−capacitors discharge capability: per IEC−950 standard, the time constant of the front−end filter capacitors and their associated discharge resistors must be less than 1 s. This is to avoid electrical stress when the user unplugs the converter and inadvertently touches the power cord terminals. By providing an automatic means to discharge the X2 capacitors, the NCP1249 prevents the designer from installing the discharge resistors, helping to further save power. • Combined feedback/remote control pin: the controller features a combined feedback/remote pin that forces the adapter to enter a deep off mode. When the FB pin is pulled down (slightly below the skip cycle mode), the part obviously stops all drive pulses. The auxiliary voltage disappears and IC goes into sleep mode. As the pull-down signal on the feedback pin is secondary-side driven, a wake-up signal releases the feedback pin and allows a fresh start-up sequence. If a dedicated circuitry is implemented on the secondary side, a self-relaxing mode can be implemented with very low standby power consumption. • • • • • • compensation: implementing peak current mode control at a fixed 65 kHz frequency, the NCP1249 offers an internal ramp compensation signal that can easily by summed up to the sensed current. Sub harmonic oscillations can thus be compensated via the inclusion of a simple resistor in series with the current−sense information. Frequency excursion: when the power demand forces the peak current setpoint to reach the internal limit (0.8 V/Rsense typically), the frequency is authorized to increase to let the converter deliver more power. The frequency excursion stops when 130 kHz are reached. Internal OPP: by routing a portion of the negative voltage present during the on−time on the auxiliary winding to the dedicated OPP pin (pin 5), the user has a simple and non−dissipative means to alter the maximum peak current setpoint as the bulk voltage increases. If the pin is grounded, no OPP compensation occurs. If the pin receives a negative voltage down to –250 mV, then a peak current reduction down to 31.3% typical can be achieved. For an improved performance, the maximum voltage excursion on the sense resistor is limited to 0.8 V. EMI jittering: an internal low−frequency modulation signal varies the pace at which the oscillator frequency is modulated. This helps spreading out energy in conducted noise analysis. To improve the EMI signature at low power levels, the jittering will not be disabled in frequency foldback mode (light load conditions). Frequency foldback capability: a continuous flow of pulses is not compatible with no−load/light−load standby power requirements. To excel in this domain, the controller observes the feedback pin and when it reaches a level of 1.5 V, the oscillator then starts to reduce its switching frequency as the feedback level continues to decrease. When the feedback pin reaches 1 V, the peak current setpoint is internally frozen and the frequency continues to decrease. It can go down to 26 kHz (typical) reached for a feedback level of 450 mV roughly. At this point, if the power continues to drop to 400 mV, the controller enters classical skip−cycle mode. Internal soft−start: a soft−start precludes the main power switch from being stressed upon start−up. In this controller, the soft−start is internally fixed to 4 ms. Soft−start is activated when a new startup sequence occurs or during an auto−recovery hiccup. Latch input: the NCP1249 includes a latch input (pin 4) that can be used to sense an overvoltage condition on the adapter. If this pin is brought higher http://onsemi.com 17 NCP1249C, NCP1249D • • than the internal reference voltage Vlatch, then the circuit permanently latches off. The VCC pin is pulled down to a fixed level, keeping the controller latched. The latch reset occurs when the user disconnects the adapter from the mains. VCC OVP: a latched OVP protects the circuit against VCC runaways. The fault must be present at least 20 ms to be validated. Reset occurs when the user disconnects the adapter from the mains. Short−circuit protection: short−circuit and especially over−load protections are difficult to implement when a strong leakage inductance between auxiliary and power windings affects the transformer (the aux winding level does not properly collapse in presence of an output short). Here, every time the internal 0.8−V maximum peak current limit is activated (or less when OPP is used), an error flag is asserted and a time period starts, thanks to the programmable timer. The controller can distinguish between two faulty situations: ♦ There is an extra demand of power, still within the power supply capabilities. In that case, the feedback level is in the vicinity of 3.2−4 V. It corresponds to 0.8 V as the maximum peak current setpoint without ♦ ♦ ♦ OPP. The timer duration is then 100% of its normal value. If the fault disappears, e.g. the peak current setpoint no longer hits the maximum value (e.g. 0.8 V at no OPP), then the timer is reset. The output is frankly shorted. The feedback level is thus pushed to its upper stop (4.5 V) and the timer is reduced to 25% of its normal value. In either mode, when the fault is validated, all pulses are stopped and the controller enters an auto−recovery burst mode, with a soft−start sequence at the beginning of each cycle. Please note the presence of a divider by two which ignores one hiccup cycle over two (double hiccup type of burst). As soon as the fault disappears, the SMPS resumes operation. Please note that some version offers an auto−recovery mode as we just described, some do not and latch off in case of a short circuit. Start−up Sequence The start−up sequence of the NCP1249 involves a high−voltage current source whose input is in pin 10. As this start−up source also performs line sensing for brown−out operation, it is recommended to wire it according to Figure 58 sketch. Vbulk to X2 discharge L1 1 L2 2 10 9 8 3 7 6 5 Ic . 4 Vcc Figure 58. The Startup Resistor can be Connected to the Input Mains for Further Power Dissipation Reduction the IC will work in cold−start case. Let us select a 4.7 mF capacitor at first and experiments in the laboratory will let us know if we were too optimistic for t1. The VCC capacitor being known, we can now evaluate the charging time to bring the VCC voltage from 0 to the VCC_ON of the IC, 18 V typical. This time sequence can actually be split into two events: 0 V to VCC_inhibit and VCC_inhibit to VCC_ON . This is because the HV source is protected from short−circuits on the VCC pin. In case this happens, the source detects that the VCC voltage is less than VCC_inhibit and only delivers Istart1 which is below 1 mA: the die power consumption is maintained to the lowest value. In normal operation, when the voltage has normally reached VCC_inhibit, the source toggles to the full current and charges the VCC capacitor at In this drawing, the high−voltage pin is not connected to the bulk, but to the full−wave rectified ac input. It is important to keep this configuration as the X2 circuitry will also use it. The first step starts with the calculation of the needed VCC capacitor which will supply the controller until the auxiliary winding takes over. Experience shows that this time t1 can be between 5 and 20 ms. Considering that we need at least an energy reservoir for a t1 time of 10 ms, the VCC capacitor must be larger than: C Vcc w (eq. 1) I CC4 t 1 3 m 10 m w w 3.75 mF 18 * 10 V CC_ON * V CC_OFF In this calculation, we adopted the consumption at the highest switching frequency since this is the point at which http://onsemi.com 18 NCP1249C, NCP1249D a larger current, Istart2 . The first time duration involves Istart1 and VCC_inhibit. t start1 + V CC_inhibit C Vcc I start1 + 1 4.7 m [ 6.7 ms 700 m (eq. 2) The second duration involves VCC_ON and Istart2: t start2 + ǒVCC_ON * VCC_inhibitǓCVcc I start2 + (18 * 1) 4.7 m [ 8 ms 10 m (eq. 3) The total start−up time is thus around 14−15 ms. Vcc_bias level. The HV current source maintains VCC at Vcc_bias level until the input voltage is back above V_BO_on . The controller then fully discharges VCC capacitor first to restart internal logic. Standard startup attempt is then placed by the controller. Figure 59. The VCC at Start−up is Made of Two Segments Given the Short−circuit Protection Implemented on the HV Source In case the VCC capacitor must be increased to cope with no−load standby requirements, there is plenty of margin to keep the total start−up sequence duration below 1 s. Assume the VCC capacitor is 100 mF, then the total start−up time would be below 400 ms. Figure 60. Simplified Block Diagram of Brown−out Detection Circuitry Brown−out Circuitry The NCP1249 features, on its HV pin, a true AC line monitoring circuitry – refer to Figure 60. This system includes a minimum start−up threshold and auto−recovery brown−out protection; both of them independent of the input voltage ripple. The thresholds are fixed, but they are designed to fit most of the standard AC−DC converter applications. When the HV pin voltage drops below V_BO_off threshold for more than 50 ms, the brown−out condition is detected and confirmed. Thus the controller stops operation – refer to Figure 61. The VCC capacitor is discharged to The Internal HV BO sensing network is formed by high impedance resistor divider with minimum resistance of 20 MW. This solution reducing power losses during off−mode and thus helps to pass maximum standby power consumption limit. The internal BO network solution provides excellent noise and PCB leakage currents immunity that is hard to achieve when using external resistor divider built from SMT chip resistors. http://onsemi.com 19 NCP1249C, NCP1249D Figure 61. Brown−out Event Detection X2 and VCC Discharge Circuitry consuming X2 timer disable circuitry. The internal X2 timer with typical duration of 100 ms is used to overcome unwanted activation of the X2 discharge switch in case of AC line dropout. The internal X2 discharge switch is activated once the X2 timer elapses. The HV startup current source is enabled in the same time thus the discharge path for X2 capacitor exists – refer to Figure 62. The NCP1249 X2 discharge circuitry uses dedicated pin (X2) together with external charge pump sensing network to detect whether is application plugged into the mains or not. Advantage of this solution is that the internal IC consumption can be reduced to extremely low level by keeping all internal blocks unbiased except simple and low Figure 62. Simplified Block Diagram of X2 and Vcc Capacitor Discharge Circuitry unwanted overheat that could occur in case the X2 pin is opened and the high voltage is present on the HV pin (like during open – short pins testing for instance). The X2 discharge switch is also activated to discharge VCC capacitor when entering into fault mode (latch mode, auto−recovery mode or the HV pin voltage drops below V_BO_off threshold for more than 50 ms), off−mode and also before controller VCC restart. The time duration of X2 capacitors discharging could be calculated by: t+ UC X1,2 I _X2_dis @ C X1,2 (eq. 4) The X2 capacitor discharging process can be interrupted by increasing voltage on X2 pin back above Vth_X2 . The over temperature protection block is active during discharging process to protect controller chip against http://onsemi.com 20 NCP1249C, NCP1249D Feedback/Remote Input duration before the NCP1249 enters off-mode is thus given by value of VCC capacitor, total consumption during skip mode and voltage level on VCC capacitor in the time when flyback controller enters skip mode. The off mode is activated when the remote pin is low and VCC_OFF threshold is crossed i.e. when the skip mode takes so long time that VCC is lost. VCC capacitor is then discharged by internal consumption. Maximum skip mode Figure 63. Simplified Block Diagram of FB/REM Control Input inhibition comparator. At this moment, the high-voltage source is good to go and it refuels the VCC capacitor until a new start-up sequence occurs. If the feedback pin is driven by a dedicated off-mode controller, shortly after the new start-up sequence, the feedback pin will go down again, initiating another off cycle. The resulting output voltage exhibits a large low-frequency ripple, naturally decreasing the overall consumption budget of the converter. Typical VCC and feedback signals while in this mode are drawn in Figure 64. To force the controller entering the off mode, the voltage on the feedback pin has to go below the skip cycle level, 400 mV typically. At this moment, all pulses are blocked and the auxiliary VCC declines down to 0 V at a pace fixed by the VCC capacitor and the controller consumption. When it passes below the VCC_OFF threshold, because the FB pin is still maintained low, the controller does not reactivate the high-voltage start-up source and the circuit remains locked, consuming the least power. The circuit remains off as long as the feedback pin pulled to ground. When the feedback pin is released, an internal current source (IFBREM), pulls the feedback voltage up, above the Figure 64. Combined FB/REM Pin Behavior http://onsemi.com 21 NCP1249C, NCP1249D Operating Status Diagram The NCP1249A/B VCC management behavior is clearly described in status diagram on Figure 65. Efficient operating mode BO Reset Start VCC −> 5V DRV = 0 Extra Low Consumption (VCC > VCC_OFF) & BO & (VFB > V_REM_on) & Latch = 0 BO BO Operation (VCC > V CC_ON ) & BO Charge VCC V CC = V CC_OFF – VCC _max DRV = 1 VCC −> 22V DRV = 0 VFB < V_REM_off & VCC < VCC_OFF REMOTE Discharge VCC −> 5V DRV = 0 VCC = 5V REMOTE Mode VCC = floating DRV = 0 I_REM_bias = 1 VFB 0.7V DRV = 0 DRV = 0 VCC −> 0V HV −> 0V X2 detect = 0 VCC > 1V Figure 65. VCC Management Status Diagram Internal Over Power Protection There are several known ways to implement Over Power Protection (OPP), all suffering from particular problems. These problems range from the added consumption burden on the converter or the skip−cycle disturbance brought by the current−sense offset. A way to reduce the power capability at high line is to capitalize on the negative voltage swing present on the auxiliary diode anode. During the turn−on time, this point dips to −NVin, N being the turns ratio between the primary winding and the auxiliary winding. The negative plateau observed on Figure 66 will have amplitude depending on the input voltage. The idea implemented in this chip is to sum a portion of this negative swing with the 0.8 V internal reference level. For instance, if the voltage swings down to −150 mV during the on time, then the internal peak current set point will be fixed to 0.8 − 0.150 = 650 mV. The adopted principle appears in Figure 67 and shows how the final peak current set point is constructed. Figure 66. The Signal Obtained on the Auxiliary Winding Swings Negative During the On−Time Let’s assume we need to reduce the peak current from 2.5 A at low line, to 2 A at high line. This corresponds to a 20% reduction or a set point voltage of 640 mV. To reach this level, then the negative voltage developed on the OPP pin must reach: V OPP + 640 m * 800 m + −160 mV http://onsemi.com 22 (eq. 5) NCP1249C, NCP1249D Figure 67. The OPP Circuitry Affects the Maximum Peak Current Set Point by Summing a Negative Voltage to the Internal Voltage Reference Let us assume that we have the following converter characteristics: Vout = 19 V Vin = 85 to 265 V rms N1 = Np:Ns = 1:0.25 N2 = Np:Naux = 1:0.18 Given the turns ratio between the primary and the auxiliary windings, the on−time voltage at high line (265 Vac) on the auxiliary winding swings down to: V aux + −N 2V in,max + −0.18 To obtain a level as imposed by (Equation 5), we need to install a divider featuring the following ratio: Div + 0.16 [ 2.4 m 67.5 (eq. 7) If we arbitrarily fix the pull−down resistor ROPPL to 1 kW, then the upper resistor can be obtained by: R OPPU + 67.5 * 0.16 [ 421 kW 0.16ń1 k (eq. 8) If we now plot the peak current set point obtained by implementing the recommended resistor values, we obtain the following curve (Figure 68): 375 + −67.5 V (eq. 6) Peak current setpoint 100% 80% 375 Vbulk Figure 68. The peak current regularly reduces down to 20% at 375 V dc maximum peak reduction is kept to 40%. If the voltage finally forward biases the internal zener diode, then care must be taken to avoid injecting a current beyond –2 mA. Given the value of ROPPU , there is no risk in the present example. Finally, please note that another comparator internally fixes the maximum peak current set point to 0.8 V even if the OPP pin is adversely biased above 0 V. For optimum performance over temperature, we recommend keeping the low−side OPP resistor below 3 kW. The OPP pin is surrounded by Zener diodes stacked to protect the pin against ESD pulses. These diodes accept some peak current in the avalanche mode and are designed to sustain a certain amount of energy. On the other side, negative injection into these diodes (or forward bias) can cause substrate injection which can lead to an erratic circuit behavior. To avoid this problem, the pin is internal clamped slightly below –300 mV which means that if more current is injected before reaching the ESD forward drop, then the http://onsemi.com 23 NCP1249C, NCP1249D Frequency Foldback feedback pin until its level reaches 1 V. Below this value, the peak current freezes to Vfreeze_FB/4 (250 mV or ≈31% of the maximum 0.8 V setpoint) and the only way to further reduce the transmitted power is to diminish the operating frequency down to 26 kHz. This value is reached at a voltage feedback level of 450 mV typically. Below this point, if the output power continues to decrease, the part enters skip cycle for the best noise−free performance in no−load conditions. Figure 69 depicts the adopted scheme for the part. The reduction of no−load standby power associated with the need for improving the efficiency, requires a change in the traditional fixed−frequency type of operation. This controller implements a switching frequency foldback when the feedback voltage passes below a certain level, Vfold_FB, set around 1.9 V. At this point, the oscillator turns into a Voltage−Controlled Oscillator and reduces its switching frequency. The peak current setpoint is following the fsw 0.80 V Vfreeze_FB Vfold_FB 1.0 V 1.9 V Vfold_end Vfold_FB Figure 69. By Observing the Voltage on the Feedback Pin, the Controller Reduces its Switching Frequency for an Improved Performance at Light Load Auto−recovery Short−circuit Protection thus to restart converter operation in case the input line voltage is above V_BO_on threshold. The controller is then checking for the absence of the fault. If the fault is still there, the supply enters another cycle of so−called hiccup. If the fault has disappeared, the power supply resumes operations. Please note that the soft−start is activated during each of the re−start sequence. In case of output short−circuit or if the power supply experiences a severe overloading situation, an internal error flag is raised and starts a countdown timer. If the flag is asserted longer than fault timer duration, the driving pulses are stopped and the VCC capacitor is discharged down to 10 V (VCC_OFF threshold) by controller ICC consumption. At this point, the controller activates 2 s auto−recovery timer that starts to count down the time to new restart attempt. The total restart time from fault confirmation is thus given by sum of two times: VCC capacitor discharge time from given Vcc level (present at fault confirmation event) to VCC_OFF level and 2 s internal auto−recovery timer duration. The VCC capacitor is discharged to VCC_bias level when auto−recovery timer starts counting. The VCC is maintained at VCC_bias level during this operation to keep timer and other internal circuitry running. The VCC capacitor is fully discharged by X2 discharge switch before controller tries for restart from fault condition. The restart from fault condition is caused when auto−recovery timer elapses or VCC is forced below 4 V externally. The HV startup current source is activated to charge the VCC capacitor in fast manner to VCC_ON level and Slope Compensation The NCP1249 includes an internal ramp compensation signal. This is the buffered oscillator clock delivered during the on time only. Its amplitude is around 2.5 V at the maximum authorized duty−ratio. Ramp compensation is a known means used to cure sub harmonic oscillations in CCM−operated current−mode converters. These oscillations take place at half the switching frequency and occur only during Continuous Conduction Mode (CCM) with a duty−ratio greater than 50%. To lower the current loop gain, one usually mixes between 50% and 100% of the inductor downslope with the current−sense signal. Figure 70 depicts how internally the ramp is generated. Please note that the ramp signal will be disconnected from the CS pin, during the off−time. http://onsemi.com 24 NCP1249C, NCP1249D 2.5 V 0V ON latch reset 20k + Rcomp L.E.B CS − Rsense from FB setpoint Figure 70. Inserting a Resistor in Series with the Current Sense Information Brings Slope Compensation and Stabilizes the Converter in CCM Operation In the NCP1249 controller, the oscillator ramp exhibits a 2.5 V swing reached at a 80% duty−ratio. If the clock operates at a 65 kHz frequency, then the available oscillator slope corresponds to: A resistor of the above value will then be inserted from the sense resistor to the current sense pin. We recommend adding a small 100 pF capacitor, from the current sense pin to the controller ground for improved noise immunity. Please make sure both components are located very close to the controller. (eq. 9) V ramp 2.5 S ramp+ + +208kVńs or 208mVńms D max T sw 0.8 15 m Latching Off the Controller In our flyback design, let’s assume that our primary inductance Lp is 770 mH, and the SMPS delivers 19 V with a Np :Ns turns ratio of 1:0.25. The off−time primary current slope Sp is thus given by: Sp + ǒVout ) VfǓ NNp Lp The OPP pin not only allows a reduction of the peak current set point in relationship to the line voltage, it also offers a means to permanently latch−off the part. When the part is latched−off, the VCC pin is internally pulled down to VCC_bias and the part stays in this state until the user un−plugs the converter from the mains outlet or VCC is forced below 4 V externally. The latch detection is made by observing the OPP pin by a comparator featuring a 3 V reference voltage. However, for noise reasons and in particular to avoid the leakage inductance contribution at turn off, a 1 ms blanking delay is introduced before the output of the OVP comparator is checked. Then, the OVP comparator output is validated only if its high−state duration lasts a minimum of 600 ns. Below this value, the event is ignored. Then, a counter ensures that only four successive OVP events have occurred before actually latching the part. There are several possible implementations, depending on the needed precision and the parameters you want to control. The first and easiest solution is the additional resistive divider on top of the OPP one. This solution is simple and inexpensive but requires the insertion of a diode to prevent disturbing the OPP divider during the on−time. (eq. 10) (19 ) 0.8) s + 770 m 4 + 103 kAńs Given a sense resistor of 330 mW, the above current ramp turns into a voltage ramp of the following amplitude: (eq. 11) S sense +S pR sense +103 k 0.33+34 kVńs or 34 mVńms If we select 50% of the downslope as the required amount of ramp compensation, then we shall inject a ramp whose slope is 17 mV/ms. Our internal compensation being of 208 mV/ms, the divider ratio (divratio) between Rcomp and the internal 20 kW resistor is: divratio + 17 m + 0.082 208 m (eq. 12) The series compensation resistor value is thus: (eq. 13) R comp + R ramp divratio + 20 k 0.082 [ 1.64 kW http://onsemi.com 25 NCP1249C, NCP1249D D2 1N4148 R3 5k 11 RoppU 421k Vcc 9 8 OPP 10 C1 100p aux. winding 4 1 ROPPL 1k 5 OVP Vlatch OPP Figure 71. Simple Resistive Divider Brings the OPP Pin Above 3 V in case of a VCC Voltage Runaway Above 18 V First, calculate the OPP network with the above equations. Then, suppose we want to latch off our controller when Vout exceeds 25 V. On the auxiliary winding, the plateau reflects the output voltage by the turns ratio between the power and the auxiliary windings. In case of voltage runaway for our 19 V adapter, the plateau will go up to: V aux,OVP + 25 0.18 + 18 V 0.25 R OVP + In nominal conditions, the plateau establishes to around 14 V. Given the divide−by ratio 6, the OPP pin will swing to 14/6 = 2.3 V during normal conditions, leaving 700 mV for the noise immunity. A 100 pF capacitor can be added to improve it and avoids erratic trips in presence of external surges. Do not increase this capacitor too much otherwise the OPP signal will be affected by the integrating time constant. A second solution for the OVP detection alone, is to use a Zener diode wired as recommended by Figure 72. (eq. 14) Since our OVP comparator trips at a 3 V level, across the 1 kW selected OPP pull−down resistor, it implies a 3 mA current. From 3 V to go up to 18 V, we need an additional 15 V. Under 3 mA and neglecting the series diode forward drop, it requires a series resistor of: D3 15V V latch * V VOP + 18 * 3 + 15 + 5 kW (eq. 15) 3m V OVPńR OPPL 3ń1 k D2 1N4148 11 RoppU 421k Vcc OPP 10 C1 22pF 9 8 aux. winding 4 1 ROPPL 1k 5 Vlatch OVP OPP Figure 72. Zener Diode in Series with a Diode Helps to Improve the Noise Immunity of the System http://onsemi.com 26 NCP1249C, NCP1249D ended and VCC is between VCC_ON and VCC_OFF levels, the controller immediately stops driver pulses. After the temperature falls back below the lower threshold, the VCC capacitor is fully discharged by X2 discharge switch to restart the controller. The TSD protection can be activated at some other cases (charging VCC capacitor − start−up sequence and discharging X2 or VCC capacitors). The TSD protection only interrupts current operating sequence – i.e. the operation sequence continue after the temperature falls back below the lower threshold. The controller is not reset by TSD activation in these cases. In a lot of designs, the adapter must be protected against thermal runaways, e.g. when the temperature inside the adapter box increases beyond a certain value. Figure 73 shows how to implement a simple OTP using an external NTC and a series diode. The principle remains the same: make sure the OPP network is not bothered by the additional NTC hence the presence of this diode. When the NTC resistor will diminish as the temperature increases, the voltage on the OPP pin during the off time will slowly increase and, once it crosses 3 V for 4 consecutive clock cycles, the controller will permanently latch off. In this case, to still trip at a 18 V level, we have selected a 15 V Zener diode. In nominal conditions, the voltage on the OPP pin is almost 0 V during the off time as the Zener is fully blocked. This technique clearly improves the noise immunity of the system compared to that obtained from a resistive string as in Figure 71. Please note the reduction of the capacitor on the OPP pin to 10 pF − 22 pF. This is because of the potential spike going through the Zener parasitic capacitor and the possible auxiliary level shortly exceeding its breakdown voltage during the leakage inductance reset period (hence the internal 1 ms blanking delay at turn off). This spike despite its very short time is energetic enough to charge the added capacitor C1 and given the time constant, could make it discharge slower, potentially disturbing the blanking circuit. When implementing the Zener option, it is important to carefully observe the OPP pin voltage (short probe connections!) and check that enough margin exists to that respect. Internal and External Over Temperature Protection The NCP1249 includes a temperature shutdown protection. When the temperature rises above the high threshold during stable operation − i.e. start−up sequence is NTC D2 1N4148 RoppU 841k Vcc OPP aux. winding ROPPL 2.5k Vlatch full latch OPP Figure 73. The Internal Circuitry Hooked to Pin 1 Can Be Used to Implement Over Temperature Protection (OTP) http://onsemi.com 27 NCP1249C, NCP1249D Back to our 19 V adapter, we have found that the plateau voltage on the auxiliary diode was 13 V in nominal conditions. We have selected an NTC which offers a 470 kW resistor at 25°C and drops to 8.8 kW at 110°C. If our auxiliary winding plateau is 14 V and we consider a 0.6 V forward drop for the diode, then the voltage across the NTC in fault mode must be: V NTC + 14 * 3 * 0.6 + 10.4 V limit at the chosen output power level. Suppose we need a 200 mV decrease from the 0.8 V set point and the on−time swing on the auxiliary anode is −67.5 V, then we need to drop over ROPPU a voltage of: VR Based on the 8.8 kW NTC resistor at 110°C, the current inside the device must be: IR 3 + 2.5 kW 1.2 m (eq. 19) OPPL + 200 m + 80 mA 2.5 k (eq. 20) The ROPPU value is therefore easily derived: (eq. 17) R OPPU + 67.3 + 841 kW 80 m As such, the bottom resistor ROPPL , can easily be calculated: R OPPL + + 67.5 * 0.2 + 67.3 V The current circulating in the pull down resistor ROPPL in this condition will be: (eq. 16) I NTC + 10.4 [ 1.2 mA 8.8 k OPPU (eq. 21) Combining OVP and OTP (eq. 18) The OTP and Zener−based OVP can be combined together as illustrated by Figure 74. Now that the pull−down OPP resistor is known, we can calculate the upper resistor value ROPPU to adjust the power D3 15V D2 1N4148 NTC 11 RoppU 841k Vcc OPP 8 aux. winding 4 10 9 1 ROPPL 2.5k 5 Vlatch OVP OPP Figure 74. With the NTC Back in Place, the Circuit Nicely Combines OVP, OTP and OPP on the Same Pin Filtering the Spikes In nominal VCC/output conditions, when the Zener is not activated, the NTC can drive the OPP pin and trigger the adapter in case of a fault. On the contrary, in nominal temperature conditions, if the loop is broken, the voltage runaway will be detected and acknowledged by the controller. In case the OPP pin is not used for either OPP or OVP, it can simply be grounded. The auxiliary winding is the seat of spikes that can couple to the OPP pin via the parasitic capacitances exhibited by the Zener diode and the series diode. To prevent an adverse triggering of the Over Voltage Protection circuitry, it is possible to install a small RC filter before the detection network. Typical values are those given in Figure 75 and must be selected to provide the adequate filtering function without degrading the stand−by power by an excessive current circulation. http://onsemi.com 28 NCP1249C, NCP1249D D3 15V additional filter D2 1N4148 NTC 11 C1 330pF 2 RoppU 841k Vcc OPP R3 220 9 aux. 4 10 winding 1 ROPPL 2.5k 3 5 Vlatch OVP OPP Figure 75. A Small RC Filter Avoids the Fast Rising Spikes from Reaching the Protection Pin of the NCP1249 in Presence of Energetic Perturbations Superimposed on the Input Line Latching Off with the VCC Pin Peak Power Excursions The NCP1249 hosts a dedicated comparator on the VCC pin. When the voltage on this pin exceeds 27.5 V typically for more than 20 ms, a signal is sent to the internal latch and the controller immediately stops the driving pulses while remaining in a lockout state. The part can be reset when the user disconnects the adapter from the mains. This technique offers a simple and cheaper means to protect the converter against optocoupler failures without using the OPP pin and a Zener diode. There are applications where the load profile heavily changes from a nominal to a peak value. For instance, it is possible that a 30 W ac−dc adapter accepts power excursions up to 60 W in certain conditions. Inkjet printers typically fall in that category of peak power adapters. However, to avoid growing the transformer size, an existing technique consists in freezing the peak current to a maximum value (0.8/Rsense in our case) but authorizes frequency increase to a certain point. This point is internally fixed at 130 kHz. Figure 76. The Feedback Pin Modulates the Frequency up to 130 kHz (Short−Circuit, Maximum Power) or Down to 26 kHz in Frequency Foldback http://onsemi.com 29 NCP1249C, NCP1249D frequency. From 3.2 V up to 4.1 V, the frequency linearly increases from 65 kHz to 130 kHz. Beyond 4.1 V, the frequency is fixed to 130 kHz. The maximum power delivered by the converter depends whether it operates in Discontinuous Conduction Mode (DCM) or in Continuous Conduction Mode (CCM): Figure 76 shows the voltage evolution from almost 0 V to the open−loop level, around 4.5 V. At low power levels or in no−load operation, the feedback voltage stays in the vicinity of 400 mV and ensures skip−cycle operation. In this mode, the peak current is frozen to 31% of its maximum value and the operating frequency is 26 kHz. This freeze lasts as long as VFB stays below 1 V. Beyond 1 V, the peak current is authorized to follow VFB through a ratio of 4. When the power demand goes further up, the feedback pin crosses a level of 1.5 V where the switching frequency linearly increases from 26 kHz up to 65 kHz, a value reached when the feedback voltage exceeds 1.9 V. Beyond 1.9 V, the frequency no longer changes. As VFB still increases, the controller is in a fixed−frequency variable peak current mode control type of operation until the feedback voltage hits 3.2 V. At this point, the maximum current is limited to 0.8 V/Rsense . If VFB further increases, it means the converter undergoes an overload and requires more power from the source. As the peak current excursion is stopped, the only way to deliver more power is to increase the switching P max,DCM + 1 L p f OSC_max I peak,max 2 h 2 (eq. 22) P max,CCM + 1 L p f OSC_max ǒI peak,max 2 * I valley 2Ǔ h (eq. 23) 2 Where Ipeak,max is the maximum peak current authorized by the controller and Ivalley the valley current reached just before a new switching cycle begins. This current is expressed by the following formula: I valley + I peak * V out ) V f NL p t off (eq. 24) In DCM, the valley current is equal to 0. Figure 77. Depending on the Feedback Level, the Timer Will Take Two Different Values: It Will Authorize a Transient Overload, but Will Reduce a Short−Circuit Duration original timer duration is divided by 4. For instance, at start-up, even if the overload timer is programmed to 200 ms, when the feedback voltage jumps to 4.5 V, the controller will wait 50 ms before fault detection occurs (the timer is reset upon start-up). Of course, if the feedback does not stay that long in the region of concern, the timer is reset when returning to a normal level. Figure 75 shows the timer values versus the feedback voltage. Two Levels of Protection Once the feedback voltage asks for the maximum peak current, the controller knows that an overload condition has started. An internal timer is operated as soon as the maximum peak is reached. This timer duration is adjusted by a pull-down resistor to ground. Let’s assume it is set to 200 ms. If the feedback voltage continues its rise, it means that the converter output voltage is going down further, close to a short-circuit situation. When the feedback voltage reaches the open-loop level (above 4.1 V typically), the http://onsemi.com 30 NCP1249C, NCP1249D Figure 78. Depending on the Feedback Level, the Timer will Take Two Different Values: It will Authorize a Transient Overload, but will Reduce a Short−circuit Duration Please note that the overload situation (OVL) is detected when the maximum peak current limit is hit. It can be 3.2 V as indicated in the graph in case of no Over Power Protection (OPP). If you have programmed an OPP level of -200 mV for instance, the OVL threshold becomes(0.8 − 0.2) x 4 = 2.4 V. When the maximum peak current situation is lifted, the converter returns to a normal situation, the timer is reset. The short circuit situation is detected by sensing a feedback voltage beyond 4.1 V. For the sake of the explanation, we have gathered two different events in Figure 79 (VCt is voltage on internal capacitor which defines fault timer duration). Figure 79. When the Feedback Voltage Exits a Fault Region Before Time Completion, the Timer is Reset. On the Contrary, if the Timer Elapses, the Part Enters an Auto−recovery Hiccup or Latches Off Depending on the Operated Version crossed (VFB with no OPP). As the overload lasts less than 200 ms (in this example the timer is set to 200 ms), the feedback returns to its regulation level and resets the timer. In the second case, the overload occurs after regulation but the feedback voltage quickly jumps into the short-circuit area. At this point, the countdown is accelerated as the charging slope changed to a steeper one. The load goes back In the first case, the feedback is pushed to the maximum upon start-up. The timer starts with a charging slope of the short-circuit condition (SC). If the timer would be externally set to 200 ms, the timer duration in this start-up sequence would be 50 ms. As soon as regulation occurs, the timer gets reset. An overload occurs shortly after (OVL). The internal timer immediately starts to count when the 3.2 V level is http://onsemi.com 31 NCP1249C, NCP1249D to an OVL mode and the counter slows down. Finally, back to short circuit again and the timer trips the fault circuitry after completion: all pulses are immediately stopped. The OVL timer is adjusted by wiring a resistor (RTimer) from pin 5 to ground. The below chart shows what value to adopt to fit your timer duration needs. Typically, a 22 kW pull-down resistor will set the OVL duration to 500 ms. In case of the pin short-circuit to ground (safety test), the duration will be reduced to 500/4 or 125 ms. Figure 80. This Curve Shows How to Program the OVL Timer Duration Please note that pin 5 includes a circuitry that manages the timer current in case of pin opening or shortening to ground. In both cases, the timer is set to known value as listed in the parameters sheet. The given duration is that of the OVL timer. http://onsemi.com 32 NCP1249C, NCP1249D PACKAGE DIMENSIONS SOIC−9 NB CASE 751BP ISSUE A 2X 0.10 C A-B D D A 0.20 C 2X 4 TIPS F 0.10 C A-B 10 6 H E 1 5 0.20 C 9X B 5 TIPS L2 b 0.25 A3 L C DETAIL A SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.10mm TOTAL IN EXCESS OF ’b’ AT MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15mm PER SIDE. DIMENSIONS D AND E ARE DETERMINED AT DATUM F. 5. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM F. 6. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. C A-B D M TOP VIEW 9X h X 45 _ 0.10 C 0.10 C M A A1 e C SIDE VIEW DETAIL A SEATING PLANE END VIEW DIM A A1 A3 b D E e H h L L2 M MILLIMETERS MIN MAX 1.25 1.75 0.10 0.25 0.17 0.25 0.31 0.51 4.80 5.00 3.80 4.00 1.00 BSC 5.80 6.20 0.37 REF 0.40 1.27 0.25 BSC 0_ 8_ RECOMMENDED SOLDERING FOOTPRINT* 9X 1.00 PITCH 0.58 6.50 9X 1.18 1 DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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