NCP1252
Current Mode PWM
Controller for Forward and
Flyback Applications
The NCP1252 controller offers everything needed to build cost−
effective and reliable ac−dc switching supplies dedicated to ATX
power supplies. Thanks to the use of an internally fixed timer,
NCP1252 detects an output overload without relying on the auxiliary
Vcc. A Brown−Out input offers protection against low input voltages
and improves the converter safety. Finally a SOIC−8 package saves
PCB space and represents a solution of choice in cost sensitive project.
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OFFLINE CONTROLLER
Features
•
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•
•
•
•
•
•
•
•
•
•
•
•
•
•
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Peak Current Mode Control
Adjustable Switching Frequency up to 500 kHz
Jittering Frequency ±5% of the Switching Frequency
Latched Primary Over Current Protection with 10 ms Fixed Delay
Delay Extended to 150 ms in E Version
Delayed Operation Upon Start−up via an Internal Fixed Timer
(A, B and C versions only)
Adjustable Soft−start Timer
Auto−recovery Brown−Out Detection
UC384X−like UVLO Thresholds
Vcc Range from 9 V to 28 V with Auto−recovery UVLO
Internal 160 ns Leading Edge Blanking
Adjustable Internal Ramp Compensation
+500 mA / –800 mA Source / Sink Capability
Maximum 50% Duty Cycle: A Version
Maximum 80% Duty Cycle: B Version
Maximum 65% Duty Cycle: C Version
Maximum 47.5% Duty Cycle: D & E Versions
Ready for Updated No Load Regulation Specifications
SOIC−8 and PDIP−8 Packages
These are Pb−Free Devices
Typical Applications
• Power Supplies for PC Silver Boxes, Games Adapter...
• Flyback and Forward Converter
8
1
SOIC−8
CASE 751
SUFFIX D
PDIP−8
CASE 626
SUFFIX P
PIN CONNECTIONS
FB
1
SS
BO
VCC
CS
DRV
RT
GND
(Top View)
MARKING DIAGRAMS
8
1
1252x
ALYWX
G
x
A
L, WL
Y, YY
W, WW
G or G
1252AP
AWL
YYWWG
= A, B, C, D or E
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 18 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
April, 2019 − Rev. 8
1
Publication Order Number:
NCP1252/D
NCP1252
Vbulk
Vout
NCP1252
1
8
2
7
3
6
4
5
Vcc
100 nF*
*Minimum recommended
decoupling capacitor value
Figure 1. Typical Application
Table 1. PIN FUNCTIONS
Pin No.
Pin Name
Function
Pin Description
1
FB
Feedback
2
BO
Brown−out input
3
CS
Current sense
Monitors the primary current and allows the selection of the ramp compensation amplitude.
4
RT
Timing element
A resistor connected to ground fixes the switching frequency.
5
GND
−
6
Drv
Driver
7
VCC
VCC
8
SSTART
Soft−start
This pin directly connects to an optocoupler collector.
This pin monitors the input voltage image to offer a Brown−out protection.
The controller ground pin.
This pin connects to the MOSFET gate
This pin accepts voltage range from 8 V up to 28 V
A capacitor connected to ground selects the soft−start duration. The soft
start is grounded during the delay timer
Table 2. MAXIMUM RATINGS TABLE (Notes 1 and 2)
Symbol
Rating
Value
Unit
VCC
Power Supply voltage, Vcc pin, transient voltage: 10 ms with IVcc < 20 mA
30
V
VCC
Power Supply voltage, Vcc pin, continuous voltage
28
V
IVcc
Maximum current injected into pin 7
20
mA
VDRV
Maximum voltage on DRV pin
−0.3 to VCC
V
Maximum voltage on low power pins (except pin 6, 7)
−0.3 to 10
V
RθJA – PDIP8
Thermal Resistance Junction−to−Air – PDIP8
131
°C/W
RθJA – SOIC8
Thermal Resistance Junction−to−Air – SOIC8
169
°C/W
TJ(MAX)
Maximum Junction Temperature
150
°C
TSTG
Storage Temperature Range
−60 to +150
°C
ESDHBM
ESD Capability, HBM model
1.8
kV
ESDMM
ESD Capability, Machine Model
200
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests: Human Body Model 1800 V per JEDEC Standard
JESD22−A114E. Machine Model Method 200 V per JEDEC Standard JESD22−A115A.
2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
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2
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3
s hutdown
Rsense
Vbulk
Rcomp
BO
CS
FB
IBO
Hyst.
Rr amp
Vdd
Vskip
−
+
VBO
LEB
R
2R
Buffered
Ramp
−
Figure 2. Internal Circuit Architecture
+
10 kHz
+
−
UV LO r eset
BOK
1V
(FCS)
−
+
MaxDC
R
Q
Clock
Ct
Grand
Reset
Boot
strap
Active
Clamp
15V
Grand Reset
Fix ed
Delay
120 ms
Soft Start
Status
Vdd
50% with A version
80% with B version
65% with C version
47.5% with D & E versions
15V
30 V
UV LO
Note:
MaxDC
MaxDC
MaxDC
MaxDC
=
=
=
=
Buffered
Ramp
Vcc
management
Fs wing
Jittering
fs w
3.5V
0V
UVLO
reset
Grand Fs w
Reset selection
R
UVLO
SQ
2 bits counter
End
Reset
Set
R
Q
SQ
−
+
Out
Count
Fault Timer
clk
Reset
QS
Q
Soft start
RT
GND
Drv
Vcc
SST ART
Iss
RT
NCP1252
NCP1252
Table 3. ELECTRICAL CHARATERISTICS
(VCC = 15 V, RT = 43 kW, CDRV = 1 nF. For typical values TJ = 25°C, for min/max values TJ = –25°C to +125°C, unless otherwise noted)
Test Condition
Symbol
Min
Typ
Max
Startup threshold at which driving pulses
are authorized
VCC increasing
A, B, C versions
D & E versions
VCC(on)
9.4
13.1
10
14
10.6
14.9
Minimum Operating voltage at which driving pulses
are stopped
VCC decreasing
VCC(off)
8.4
9
9.6
V
A, B and C versions
D & E versions
VCC(HYS)
0.9
4.5
1.0
5.0
−
−
V
VCC < VCC(on) & VCC increasing
from zero
ICC1
−
−
100
mA
Internal IC consumption, controller switching
Fsw =100 kHz, DRV = open
ICC2
0.5
1.4
2.2
mA
Internal IC consumption, controller switching
Fsw =100 kHz, CDRV = 1 nF
ICC3
2.0
2.7
3.5
mA
Current Sense Voltage Threshold
VILIM
0.92
1
1.08
V
Leading Edge Blanking Duration
tLEB
−
160
−
ns
Characteristics
Unit
SUPPLY SECTION AND VCC MANAGEMENT
Hysteresis between VCC(on) and VCC(min)
Start−up current, controller disabled
V
CURRENT COMPARATOR
Input Bias Current
(Note 3)
Ibias
−
0.02
−
mA
Propagation delay
From CS detected to gate
turned off
tILIM
−
70
150
ns
Internal Ramp Compensation Voltage level
@ 25°C (Note 4)
Vramp
3.15
3.5
3.85
V
Internal Ramp Compensation resistance to CS pin
@ 25°C (Note 4)
Rramp
−
26.5
−
kW
Oscillator Frequency
RT = 43 kW & DRV pin = 47 kW
fOSC
92
100
108
kHz
Oscillator Frequency
RT = 8.5 kW & DRV pin = 47 kW
fOSC
425
500
550
kHz
Frequency Modulation in percentage of fOSC
(Note 3)
fjitter
−
±5
−
%
Frequency modulation Period
(Note 3)
Tswing
−
3.33
−
ms
Maximum operating frequency
(Note 3)
fMAX
500
−
−
kHz
DCmaxA
45.6
48
49.6
%
Maximum duty−cycle – B version
DCmaxB
76
80
84
%
Maximum duty−cycle – C version
DCmaxC
61
65
69
%
Maximum duty−cycle – D & E versions
DCmaxD
44.2
45.6
47.2
%
FBdiv
−
3
−
−
Rpull−up
−
3.5
−
kW
INTERNAL OSCILLATOR
Maximum duty−cycle – A version
FEEDBACK SECTION
Internal voltage division from FB to CS setpoint
Internal pull−up resistor
FB pin maximum current
FB pin = GND
IFB
1.5
−
−
mA
ZFB
−
40
−
kW
FB pin = open
VFBOL
−
6.0
−
V
(Note 3)
Vf
−
0.75
−
V
DRV Source resistance
RSRC
−
10
30
W
DRV Sink resistance
RSINK
−
6
19
W
tr
−
26
−
ns
Internal feedback impedance from FB to GND
Open loop feedback voltage
Internal Diode forward voltage
DRIVE OUTPUT
Output voltage rise−time
VCC = 15 V, CDRV = 1 nF,
10 to 90%
3. Guaranteed by design
4. Vramp, Rramp Guaranteed by design
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4
NCP1252
Table 3. ELECTRICAL CHARATERISTICS
(VCC = 15 V, RT = 43 kW, CDRV = 1 nF. For typical values TJ = 25°C, for min/max values TJ = –25°C to +125°C, unless otherwise noted)
Characteristics
Test Condition
Symbol
Min
Typ
Max
Unit
VCC = 15 V, CDRV = 1 nF,
90 to 10%
tf
−
22
−
ns
VCC = 25 V
RDRV = 47 kW, CDRV = 1 nF
VCL
−
15
18
V
−
50
500
mV
Vskip
0.2
0.3
0.4
V
Vskip(reset)
−
Vskip+
Vskip(HY
−
V
DRIVE OUTPUT
Output voltage fall−time
Clamping voltage (maximum gate voltage)
High−state voltage drop
VCC = VCC(min) + 100 mV, RDRV VDRV(clamp)
= 47 kW, CDRV = 1 nF
CYCLE SKIP
Skip cycle level
Skip threshold Reset
S)
Skip threshold Hysteresis
Vskip(HYS)
−
25
−
mV
ISS
8.8
10
11
mA
VSS
3.5
4.0
4.5
V
SSdelay
100
120
155
ms
FCS
0.9
1
1.1
V
SOFT START
SS pin = GND
Soft−start charge current
Soft start completion voltage threshold
Internal delay before starting the Soft start when
VCC(on) is reached
For A, B and C versions only
− No delay for D & E versions
PROTECTION
Current sense fault voltage level triggering the
timer
Timer delay before latching a fault (overload or
short circuit) − A/B/C/D versions
When CS pin > FCS
Tfault
10
15
20
ms
Timer delay before latching a fault (overload or
short circuit) − E version
When CS pin > FCS
Tfault
120
155
200
ms
VBO
0.974
1
1.026
V
IBO
8.8
8.6
10
10
11.2
11.2
mA
Brown−out voltage
Internal current source generating the Brown−out
hysteresis
−5°C ≤ TJ ≤ +125°C
−25°C ≤ TJ ≤ +125°C
3. Guaranteed by design
4. Vramp, Rramp Guaranteed by design
Table 4. SELECTION TABLE
NCP1252
Start−up Delay
Duty Ratio Max
VCC Start (Typ.)
Fault Timer (Typ.)
Fault
A
Yes
50%
10 V
15 ms
Latched
B
Yes
80%
10 V
15 ms
Latched
C
Yes
65%
10 V
15 ms
Latched
D
No
47.5%
14 V
15 ms
Latched
E
No
47.5%
14 V
150 ms
Latched
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NCP1252
SUPPLY VOLTAGE HYSTERESIS LEVEL (V)
10.2
10.0
VCC(on)
9.8
9.6
9.4
9.2
VCC(off)
9.0
8.8
−40 −20
0
20
40
60
80
100
120
1.15
1.10
1.05
1.00
0.95
0.90
−40 −20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 3. Supply Voltage Threshold vs.
Junction Temperature (A, B and C Versions)
Figure 4. Supply Voltage Hysteresis vs.
Junction Temperature (A, B and C Versions)
15.0
14.5
14.0
13.5
13.0
−40 −20
0
20
40
60
80
100
120
6.0
5.5
5.0
4.5
4.0
−40 −20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 5. Supply Voltage VCC(ON) Threshold vs.
Junction Temperature (D Version)
Figure 6. Supply Voltage Hysteresis vs.
Junction Temperature (D Version)
50
120
5
SUPPLY CURRENT ICC3 (mA)
STARTUP CURRENT ICC1 (mA)
1.20
TEMPERATURE (°C)
SUPPLY VOLTAGE HYSTERESIS LEVEL (V)
UNDER VOLTAGE LOCK OUT LEVEL (V)
UNDER VOLTAGE LOCK OUT LEVEL (V)
TYPICAL CHARACTERISTICS
40
30
20
10
0
−40
−20
0
20
40
60
80
100
4
3
2
1
0
−40
120
−20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. Start−up Current (ICC1) vs. Junction
Temperature
Figure 8. Supply Current (ICC3) vs. Junction
Temperature
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NCP1252
TYPICAL CHARACTERISTICS
1.08
2
1
10
15
20
25
1.06
1.04
1.02
1.00
0.98
0.96
0.94
0.92
−40
30
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 9. Supply Current (ICC3) vs. Supply
Voltage
Figure 10. Current Sense Voltage Threshold
vs. Junction Temperature
300
250
200
150
100
50
0
−40 −20
0
20
40
60
80
100
120
300
250
200
150
100
50
0
10
15
20
25
TEMPERATURE (°C)
SUPPLY VOLTAGE Vcc (V)
Figure 11. Leading Edge Blanking Time vs.
Junction Temperature
Figure 12. Leading Edge Blanking Time vs.
Supply Voltage
160
160
140
140
120
100
80
60
40
20
0
−40
−20
SUPPLY VOLTAGE Vcc (V)
LEADING EDGE BLANKING TIME (ns)
LEADING EDGE BLANKING TIME (ns)
0
PROPAGATION DELAY (ns)
CURRENT SENSE VOLTAGE
THRESHOLD (V)
3
PROPAGATION DELAY (ns)
SUPPLY CURRENT ICC3 (mA)
4
−20
0
20
40
60
80
100
120
100
80
60
40
20
0
120
30
10
15
20
25
30
TEMPERATURE (°C)
SUPPLY VOLTAGE Vcc (V)
Figure 13. Propagation Delay from CS to DRV
vs. Junction Temperature
Figure 14. Propagation Delay from CS to DRV
vs. Supply Voltage
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NCP1252
108
OSCILLATOR FREQUENCY @ Rt = 43 kW (kHz)
OSCILLATOR FREQUENCY @ Rt = 43 kW (kHz)
TYPICAL CHARACTERISTICS
106
104
102
100
98
96
94
92
−40 −20
0
20
40
60
80
100
120
TEMPERATURE (°C)
108
106
104
102
100
98
96
94
92
10
20
25
30
SUPPLY VOLTAGE Vcc (V)
Figure 15. Oscillator Frequency vs. Junction
Temperature
SWITCHING FREQUENCY, FSW (kHz)
15
Figure 16. Oscillator Frequency vs. Supply
Voltage
500
450
400
350
300
250
200
150
100
50
0
0
20
40
60
80
100
Rt RESISTOR (kW)
Figure 17. Oscillator Frequency vs. Oscillator
Resistor
84
MAXIMUM DUTY CYCLE (%)
MAXIMUM DUTY CYCLE (%)
49
48
47
46
45
−40 −20
0
20
40
60
80
100
83
82
81
80
79
78
77
76
−40
120
−20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 18. Maximum Duty−cycle, A Version vs.
Junction Temperature
Figure 19. Maximum Duty−cycle, B Version vs.
Junction Temperature
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NCP1252
TYPICAL CHARACTERISTICS
47.0
MAXIMUM DUTY CYCLE (%)
68
67
66
65
64
63
62
DRIVE SINK AND SOURCE RESISTANCE (W)
61
−40
−20
0
20
40
60
80
100
46.5
46.0
45.5
45.0
44.5
44.0
−40
120
−20
0
60
80
100
120
Figure 20. Maximum Duty−cycle, C Version vs.
Junction Temperature
Figure 21. Maximum Duty−cycle, D Version vs.
Junction Temperature
20
12
10
ROH
8
6
ROL
4
2
0
−40 −20
0
20
40
60
80
100
18
16
14
12
10
−40
120
−20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 22. Drive Sink and Source Resistances
vs. Junction Temperature
Figure 23. Drive Clamping Voltage vs.
Junction Temperature
1.0
SKIP CYCLE THRESHOLD (V)
20
DRIVE CLAMPING VOLTAGE (V)
40
TEMPERATURE (°C)
14
18
16
14
12
10
20
TEMPERATURE (°C)
DRIVE CLAMPING VOLTAGE (V)
MAXIMUM DUTY CYCLE (%)
69
10
15
20
25
30
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
−40
−20
0
20
40
60
80
100
120
TEMPERATURE (°C)
SUPPLY VOLTAGE Vcc (V)
Figure 24. Drive Clamping Voltage vs. Supply
Voltage
Figure 25. Skip Cycle Threshold vs. Junction
Temperature
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NCP1252
TYPICAL CHARACTERISTICS
5.0
SOFT START COMPLETION VOLTAGE THRESHOLD (V)
SOFT START CURRENT (mA)
11
10
9
8
−40
−20
0
20
40
60
80
100
4.5
4.0
3.5
3.0
−40
120
−20
0
20
1.08
1.06
1.04
1.02
1.00
0.98
0.96
0.94
20
40
60
80
100
120
BROWN OUT VOLTAGE THRESHOLD (V)
1.10
0
80
100
120
Figure 27. Soft Start Completion Voltage
Threshold vs. Junction Temperature
1.10
1.08
1.06
1.04
1.02
1.00
0.98
0.96
0.94
0.92
0.90
10
15
20
25
TEMPERATURE (°C)
SUPPLY VOLTAGE Vcc (V)
Figure 28. Brown Out Voltage Threshold vs.
Junction Temperature
Figure 29. Brown Out Voltage Threshold vs.
Supply Voltage
12.0
11.5
11.0
10.5
10.0
9.5
9.0
8.5
8.0
−40
−20
0
20
40
60
80
100
120
TEMPERATURE (°C)
INTERNAL BROWN OUT CURRENT SOURCE (mA)
INTERNAL BROWN OUT CURRENT SOURCE (mA)
BROWN OUT VOLTAGE THRESHOLD (V)
Figure 26. Soft Start Current vs. Junction
Temperature
−20
60
TEMPERATURE (°C)
TEMPERATURE (°C)
0.92
0.90
−40
40
12.0
11.5
11.0
10.5
10.0
9.5
9.0
8.5
8.0
10
Figure 30. Internal Brown Out Current Source
vs. Junction Temperature
15
20
25
SUPPLY VOLTAGE Vcc (V)
Figure 31. Internal Brown Out Current Source
vs. Supply Voltage
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30
30
NCP1252
Application Information
Introduction
The NCP1252 hosts a high−performance current−mode
controller specifically developed to drive power supplies
designed for the ATX and the adapter market:
• Current Mode operation: implementing peak
current−mode control topology, the circuit offers
UC384X−like features to build rugged power supplies.
• Adjustable switching frequency: a resistor to ground
precisely sets the switching frequency between 50 kHz
and a maximum of 500 kHz. There is no
synchronization capability.
• Internal frequency jittering: Frequency jittering
softens the EMI signature by spreading out peak energy
within a band ±5% from the center frequency.
• Wide Vcc excursion: the controller allows operation
up to 28 V continuously and accepts transient voltage
up to 30 V during 10 ms with IVCC < 20 mA
• Gate drive clamping: a lot of power MOSFETs do not
allow their driving voltage to exceed 20 V. The
controller includes a low−loss clamping voltage which
prevents the gate from going beyond 15 V typical.
• Low startup−current: reaching a low no−load standby
power represents a difficult exercise when the
controller requires an external, lossy, resistor connected
to the bulk capacitor. The start−up current is guaranteed
to be less than 100 mA maximum, helping the designer
to reach a low standby power level.
• Short−circuit protection: by monitoring the CS pin
voltage when it exceeds 1 V (maximum peak current),
the controller detects a fault and starts an internal
digital timer. On the condition that the digital timer
elapses, the controller will permanently latch−off. This
allows accurate overload or short−circuit detection
which is not dependant on the auxiliary winding. Reset
occurs when: a) a BO reset is sensed, b) VCC is cycled
down to VCC(min) level. If the short circuit or the fault
disappear before the fault timer ends, the fault timer is
reset only if the CS pin voltage level is below 1 V at
least during 3 switching frequency periods. This delay
before resetting the fault timer prevents any false or
missing fault or over load detection.
• Adjustable soft−start: the soft−start is activated upon
a start−up sequence (VCC going−up and crossing
•
•
•
•
VCC(on)) after a minimum internal time delay of 120 ms
(SSdelay). But also when the brown−out pin is reset
without in that case timer delay. This internal time
delay gives extra time to the PFC to be sure that the
output PFC voltage is in regulation. The soft start pin is
grounded until the internal delay is ended. Please note
that SSdelay is present only for A, B and C versions.
Shutdown: if an external transistor brings the BO pin
down, the controller is shut down, but all internal
biasing circuits are alive. When the pin is released, a
new soft−start sequence takes place.
Brown−Out protection: BO pin permanently monitors
a fraction of the input voltage. When this image is
below the VBO threshold, the circuit stays off and does
not switch. As soon the voltage image comes back
within safe limits, the pulses are re−started via a
start−up sequence including soft−start. The hysteresis is
implemented via a current source connected to the BO
pin; this current source sinks a current (IBO) from the
pin to the ground. As the current source status depends
on the brown−out comparator, it can easily be used for
hysteresis purposes. A transistor pulling down the BO
pin to ground will shut−off the controller. Upon release,
a new soft−start sequence takes place.
Internal ramp compensation: a simple resistor
connected from the CS pin to the sense resistor allows
the designer to inject ramp compensation inside his
design.
Skip cycle feature: When the power supply loads are
decreasing to a low level, the duty cycle also decreases
to the minimum value the controller can offer. If the
output loads disappear, the converter runs at the
minimum duty cycle fixed by the propagation delay and
driving blocks. It often delivers too much energy to the
secondary side and it trips the voltage supervisor. To
avoid this problem, the FB is allowed to impose the min
tON down to ~ Vf and it further decreases down to
Vskip, zero duty cycle is imposed. This mode helps to
ensure no−load outputs conditions as requested by
recently updated ATX specifications. Please note that
the converter first goes to min tON before going to zero
duty cycle: normal operation is thus not disturbed. The
following figure illustrates the different mode of
operation versus the FB pin level.
www.onsemi.com
11
NCP1252
FB level
VFBOL = 6.0 V
Normal Operation:
DCmin < DC < DCmaxA/B/C
Vf = 0.75 V
Operation @ Ton_min
DC = DCmin
Vskip = 0.3 V
Skip: DC = 0%
Time
Figure 32. Mode of Operation versus the FB Pin Level
Startup Sequence:
the soft start is allowed. When the soft start is allowed the SS
pin is released from the ground and the current source
connected to this pin sources its current to the external
capacitor connected on SS pin. The voltage variation of the
SS pin divided by 4 gives the same peak current variation on
the CS pin.
The following figures illustrate the different startup cases.
The startup sequence is activated when Vcc pin reaches
VCC(on) level. Once the startup sequence has been activated
the internal delay timer (SSdelay) runs (except D version).
Only when the internal delay elapses the soft start can be
allowed if the BO pin level is above VBO level. If the BO pin
threshold is reached or as soon as this level will be reached
VCC pin
VCC pin
VCC(on)
VCC(on)
Time
BO pin
Time
BO pin
VBO
VBO
Time
Time
SS pin
SS pin
120 ms: Internal
delay
120 ms: Internal
delay
DRV pin
Soft start
Time
DRV pin
Soft start
Time
No
pulse
CASE #1
Time
CASE #2
Time
Figure 33. Different Startup Sequence Case #1 & #2 − (For A, B and C versions)
With the Case #2, at the end of the internal delay, the BO
pin level is below the VBO threshold thus the soft start
sequence can not start. A new soft start sequence will start
only when the BO pin reaches the VBO threshold.
With the Case #1, when the VCC pin reaches the VCC(on)
level, the internal timer starts. As the BO pin level is above
the VBO threshold at the end of the internal delay, a soft start
sequence is started.
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12
NCP1252
VCC pin
VCC pin
VCC(on)
VCC(on)
Time
BO pin
Time
BO pin
VBO
VBO
SS pin
Time
SS pin
Time
DRV pin
Time
Soft start
SS capacitor is
discharged
DRV pin
Time
Time
CASE #3
Time
CASE #4
Figure 34. Controller Shuts Down with the Brown Out Pin
Soft Start:
When the BO pin is grounded, the controller is shut down
and the SS pin is internally grounded in order to discharge
the soft start capacitor connected to this pin (Case #3). If the
BO pin is released, when its level reaches the VBO level a
new soft start sequence happens.
As illustrated by the following figure, the rising voltage on
the SS pin voltage divided by 4 controls the peak current
sensed on the CS pin. Thus as soon as the CS pin voltage
becomes higher than the SS pin voltage divided by 4 the
driver latch is reset.
Clock
Rcomp
S
CS
LEB
Rse nse
Soft Start
Status
Vdd
Iss
R
Fixe d
Delay
120 ms
UVLO
+
−
SS
1/4
Soft start
Grand Reset
Figure 35. Soft Start Principle
www.onsemi.com
13
Q
Q
DRV
NCP1252
The following figure illustrates a soft start sequence.
Soft Start pin
(2 V/div)
TSS = 13 ms
VSS = 4 V
CS pin
(0.5 V/div)
Time
(4 ms/div)
Figure 36. Soft Start Example
Brown−Out Protection
By monitoring the level on BO pin, the controller protects
the forward converter against low input voltage conditions.
When the BO pin level falls below the VBO level, the
controllers stops pulsing until the input level goes back to
normal and resumes the operation via a new soft start sequence.
The brown−out comparator features a fixed voltage
reference level (VBO). The hysteresis is implemented by
using the internal current connected between the BO pin and
the ground when the BO pin is below the internal voltage
reference (VBO).
S
Vbulk
RB O u p
R
BO
BOK
−
+
shutdown
Q
Q
RB Olo
VBO
Grand
Reset
UVLO r eset
IBO
Figure 37. BO Pin Setup
ǒ
The following equations show how to calculate the
resistors for BO pin.
First of all, select the bulk voltage value at which the
controller must start switching (Vbulkon) and the bulk
voltage for shutdown (Vbulkoff) the controller.
Where:
• Vbulkon = 370 V
• Vbulkoff = 350 V
• VBO = 1 V
• IBO = 10 mA
When BO pin voltage is below VBO (internal voltage
reference), the internal current source (IBO) is activated. The
following equation can be written:
V bulkON + R BOup I BO )
Ǔ
V BO
) V BO
R BOlo
(eq. 1)
When BO pin voltage is higher than VBO, the internal
current source is now disabled. The following equation can
be written:
V BO +
V bulkoffR BOlo
R BOlo ) R BOup
(eq. 2)
From Equation 2 it can be extracted the RBOup:
R BOup +
ǒ
Ǔ
V bulkoff * V BO
R BOlo
V BO
(eq. 3)
Equation 3 is substituted in Equation 1 and solved for
RBOlo, yields:
www.onsemi.com
14
NCP1252
R BOlo +
ǒ
Ǔ
V BO V bulkon * V BO
*1
I BO V bulkoff * V BO
Short Circuit or Over Load Protection:
(eq. 4)
A short circuit or an overload situation is detected when
the CS pin level reaching its maximum level at 1 V. In that
case the fault status is stored in the latch and allows the
digital timer count. If the digital timer ends then the fault is
latched and the controller permanently stops the pulses on
the driver pin.
If the fault is gone before ending the digital timer, the
timer is reset only after 3 switching controller periods
without fault detection (or when the CS pin < 1 V during at
least 3 switching periods).
If the fault is latched the controller can be reset if a BO
reset is sensed or if VCC is cycled down to VCC(off). The fault
timer is typically set to 15 ms for A/B/C and D versions but
is extended to 150 ms for the E version.
RBOup can be also written independently of RBOlo by
substituting Equation 4 into Equation 3 as follow:
R BOup +
V bulkon * V bulkoff
I BO
(eq. 5)
From Equation 4 and Equation 5, the resistor divider value
can be calculated:
ǒ
Ǔ
R BOlo + 1 370 * 1 * 1 + 5731 W
10 m 350 * 1
R BOup + 370 * 350 + 2.0 MW
10 m
Fault timer: 15 ms
CS pin
(500 mV/div)
Short Circuit
12 Vout
(5 V/div)
Time
(4 ms/div)
Figure 38. Short Circuit Detection Example
Shut Down
Continuous Conduction Mode (CCM) with a duty−cycle
close to and above 50%. To lower the current loop gain, one
usually injects between 50 and 100% of the inductor
downslope. Figure 39 depicts how internally the ramp is
generated:
The compensation is derived from the oscillator via a
buffer. A switch placed between the buffered internal
oscillator ramp and Rramp disconnects the compensation
ramp during the OFF time DRV signal.
There is one possibility to shut down the controller; this
possibility consists of grounding the BO pin as illustrated in
Figure 37.
Slope Compensation
Slope compensation is a known mean to cure
subharmonic oscillations. These oscillations take place at
half of the switching frequency and occur only during
www.onsemi.com
15
NCP1252
Vdd
FB
Clock
2R
S
R
Buffered
Ramp
DRV
path
Q
Q
R
Rramp
LEB
+
Rsense
CS
−
Rcomp
Ccs
Figure 39. Ramp Compensation Setup
In the NCP1252, the internal ramp swings with a slope of:
S int +
V ramp
F
DC max SW
A few line of algebra determined Rcomp:
R comp + R ramp
(eq. 6)
(V out ) V f) N s
R
L out
N p sense
(eq. 7)
where:
• Vout is output voltage level
• Vf the freewheel diode forward drop
• Lout, the secondary inductor value
• Ns/Np the transformer turn ratio
• Rsense: the sense resistor on the primary side
Assuming the selected amount of ramp compensation to
be applied is δcomp, then we must calculate the division ratio
to scale down Sint accordingly:
Ratio +
R sensed comp
S int
(eq. 9)
The previous ramp compensation calculation does not
take into account the natural primary ramp created by the
transformer magnetizing inductance. In some case
illustrated here after the power supply does not need
additional ramp compensation due to the high level of the
natural primary ramp.
The natural primary ramp is extracted from the following
formula:
In a forward application the secondary−side downslope
viewed on a primary side requires a projection over the sense
resistor Rsense. Thus:
S sense +
Ratio
1 * Ratio
S natural +
V bulk
R
L mag sense
(eq. 10)
Then the natural ramp compensation will be:
d natural_comp +
S natural
S sense
(eq. 11)
If the natural ramp compensation (δnatural_comp) is higher
than the ramp compensation needed (δcomp), the power
supply does not need additional ramp compensation. If not,
only the difference (δcomp−δnatural_comp) should be used to
calculate the accurate compensation value.
(eq. 8)
Thus the new division ratio is:
if d natural_comp t d comp å Ratio +
S int
(eq. 12)
• Vbulk = 350 V, minimum input voltage at which the
Then Rcomp can be calculated with the same equation used
when the natural ramp is neglected (Equation 9).
•
•
•
•
•
Ramp Compensation Design Example:
•
•
•
•
•
S sense(d comp * d natural_comp)
2 switch−Forward Power supply specification:
Regulated output: 12 V
Lout = 27 mH
Vf = 0.7 V (drop voltage on the regulated output)
Current sense resistor : 0.75 W
Switching frequency : 125 kHz
power supply works.
Duty cycle max: DCmax = 84%
Vramp = 3.5 V, Internal ramp level.
Rramp = 26.5 kW, Internal pull−up resistance
Targeted ramp compensation level: 100%
Transformer specification:
− Lmag = 13 mH
− Ns/Np = 0.085
www.onsemi.com
16
NCP1252
Internal ramp compensation level
S int +
V ramp
F å S int + 3.5 125 kHz + 520 mV ń ms
0.84
DC max sw
Secondary−side downslope projected over the sense resistor is:
S sense +
(V out ) V f) N s
(12 ) 0.7)
R
å S sense +
0.085
L out
N p sense
27 @ 10 −6
0.75 + 29.99 mV ń ms
Natural primary ramp:
S natural +
V bulk
R
å S natural + 350 −3 0.75 + 20.19 mV ń ms
L mag sense
13 @ 10
Thus the natural ramp compensation is:
d natural_comp +
S natural
å d natural_comp + 20.19 + 67.3%
29.99
S sense
Here the natural ramp compensation is lower than the desired ramp compensation, so an external compensation should be
added to prevent sub−harmonics oscillation.
Ratio +
S sense(d comp * d natural_comp)
S int
å Ratio +
29.99 @ (1.00 * 0.67)
+ 0.019
520
We can know calculate external resistor (Rcomp) to reach the correct compensation level.
R comp + R ramp
Ratio å R
0.019 + 509 W
3
comp + 26.5 @ 10
1 * 0.019
1 * Ratio
Thus with Rcomp = 510 W, 100% compensation ramp is applied on the CS pin.
The following example illustrates a power supply where the natural ramp offers enough ramp compensation to avoid external
ramp compensation.
2 switch−Forward Power supply specification:
• Regulated output: 12 V
• Duty cycle max: DCmax = 84%
• Lout = 27 mH
• Vramp = 3.5 V, Internal ramp level.
• Vf = 0.7 V (drop voltage on the regulated output)
• Rramp = 26.5 kW, Internal pull−up resistance
• Current sense resistor: 0.75 W
• Targeted ramp compensation level: 100%
• Switching frequency: 125 kHz
• Transformer specification:
− Lmag = 7 mH
• Vbulk = 350 V, minimum input voltage at which the
− Ns/Np = 0.085
power supply works.
Secondary−side downslope projected over the sense resistor is:
S sense +
(V out ) V f) N s
(12 ) 0.7)
R
å S sense +
0.085
L out
N p sense
27 @ 10 −6
0.75 + 29.99 mV ń ms
The natural primary ramp is:
S natural +
V bulk
R
å S natural + 350 −3 0.75 + 37.5 mV ń ms
L mag sense
7 @ 10
And the natural ramp compensation will be:
d natural_comp +
S natural
å d natural_comp + 37.5 + 125%
29.99
S sense
So in that case the natural ramp compensation due to the magnetizing inductance of the transformer will be enough to prevent
any sub−harmonics oscillation in case of duty cycle above 50%.
www.onsemi.com
17
NCP1252
Table 5. ORDERING INFORMATION
Version
Marking
Shipping†
NCP1252APG
A
1252AP
50 Units / Rail
NCP1252ADR2G
A
1252A
2500 / Tape & Reel
NCP1252BDR2G
B
1252B
2500 / Tape & Reel
NCP1252CDR2G
C
1252C
2500 / Tape & Reel
NCP1252DDR2G
D
1252D
2500 / Tape & Reel
NCP1252EDR2G
E
1252E
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
www.onsemi.com
18
NCP1252
PACKAGE DIMENSIONS
8 LEAD PDIP
CASE 626−05
ISSUE P
D
A
E
H
8
5
1
4
E1
NOTE 8
b2
c
B
END VIEW
TOP VIEW
WITH LEADS CONSTRAINED
NOTE 5
A2
A
e/2
NOTE 3
L
SEATING
PLANE
A1
C
D1
M
e
8X
SIDE VIEW
b
0.010
eB
END VIEW
M
C A
M
B
M
NOTE 6
www.onsemi.com
19
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.355 0.400
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
9.02
10.16
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
NCP1252
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
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coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
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