NCP1253ASN65T1G

NCP1253 Controller, Current Mode PWM, for Offline Power Supplies The NCP1253 is a highly integrated PWM controller capable of delivering a rugged and high performance offline power supply in a tiny TSOP−6 package. With a supply range up to 28 V, the controller hosts a jittered 65 kHz or 100 kHz switching circuitry operated in peak current mode control. When the power on the secondary side starts to decrease, the controller automatically folds back its switching frequency down to a minimum level of 26 kHz. As the power further goes down, the part enters skip cycle while limiting the peak current. To avoid sub harmonic oscillations in CCM operation, adjustable slope compensation is available via the series inclusion of a simple resistor in the current sense signal. Besides the auto−recovery timer−based short−circuit protection, an Over Voltage Protection on the VCC pin protects the whole circuitry in case of optocoupler destruction or adverse open loop operation. Features • Fixed−Frequency 65 kHz or 100 kHz Current−Mode Control www.onsemi.com MARKING DIAGRAM TSOP−6 CASE 318G STYLE 13 1 53xAYWG G 1 53 x A Y W G = Specific Device Code = A, 2, C, or D = Assembly Location = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) Operation • Frequency Foldback Down to 26 kHz and Skip−Cycle in Light Load • • • • • • • • Conditions Adjustable Ramp Compensation Internally Fixed 4 ms soft−start Timer−based Auto−Recovery or Latched Short−Circuit Protection Frequency Jittering in Normal and Frequency Foldback Modes Latched OVP on VCC Up to 28 V VCC Operation Extremely Low No−load Standby Power These are Pb−Free Devices Typical Applications PIN CONNECTIONS GND 1 6 DRV FB 2 5 VCC NC 3 4 CS (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. • Ac−dc Converters for TVs, Set−top Boxes and Printers • Offline Adapters for Notebooks and Netbooks © Semiconductor Components Industries, LLC, 2014 December, 2014 − Rev. 1 1 Publication Order Number: NCP1253/D NCP1253 Vbulk Vout . . . NCP1253 1 6 2 5 3 4 ramp comp. Figure 1. Typical Application Schematic PIN FUNCTION DESCRIPTION Pin No. Pin Name Function 1 GND − Description 2 FB Feedback pin 3 NC Non−connected pin 4 CS Current sense + ramp compensation 5 VCC Supplies the controller – protects the IC 6 DRV Driver output The controller ground. Hooking an optocoupler collector to this pin will allow regulation. The pin is electrically inert and can be grounded if necessary This pin monitors the primary peak current but also offers a means to introduce slope compensation. This pin is connected to an external auxiliary voltage. An OVP comparator monitors this pin and offers a means to latch the converter in fault conditions. The driver’s output to an external MOSFET gate. OPTIONS Controller Frequency OCP Latched OCP Auto−Recovery NCP1253ASN65T1G 65 kHz Yes No NCP1253BSN65T1G 65 kHz No Yes NCP1253ASN100T1G 100 kHz Yes No NCP1253BSN100T1G 100 kHz No Yes ORDERING INFORMATION Package Marking OCP Protection Switching Frequency (kHz) NCP1253ASN65T1G 53A Latch 65 NCP1253BSN65T1G 532 Auto Recovery 65 NCP1253ASN100T1G 53C Latch 100 NCP1253BSN100T1G 53D Auto Recovery 100 Device Package Shipping† TSOP−6 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 2 NCP1253 IpFlag BO Vcc logic management and fault timer UVLO vdd 20us time constant VOVP power on reset S Q Q Rlim Vcc vdd R Power on 65 kHz 100 kHz clock reset Frequency modulation Clamp S Q Q R Frequency foldback Drv Vfold Vskip Rramp 4 ms SS VDD The soft−start is activated during: Vlimit IpFlag − the startup sequence − the auto−recovery burst mode RFB / 4.2 VFB < 1.05 V ? setpoint = 250 mV FB 250 mV peak current freeze CS LEB GND Figure 2. Internal Circuit Architecture www.onsemi.com 3 NCP1253 MAXIMUM RATINGS TABLE Symbol VCC Rating Power Supply voltage, Vcc pin, continuous voltage Maximum voltage on low power pins CS, and FB Value Unit 28 V −0.3 to 10 V RqJ−A Thermal Resistance Junction−to−Air 360 °C/W TJ,max Maximum Junction Temperature 150 °C −60 to +150 °C 2 kV 200 V Storage Temperature Range ESD Capability, Human Body Model, all pins ESD Capability, Machine Model Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. This device series contains ESD protection and exceeds the following tests: Human Body Model 2000 V per JESD22, Method A114E. Machine Model Method 200 V per JESD22, Method A115A. 2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78. ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted) Rating Pin Min Typ Max Unit VCC increasing level at which driving pulses are authorized 5 16 18 20 V VCC(min) VCC decreasing level at which driving pulses are stopped 5 8.2 8.8 9.4 V VCCHYST Hysteresis VCCON−VCC(min) 5 6 − − V Clamped VCC when latched off @ ICC = 500 mA 5 − 7 − V ICC1 Start−up current 5 − − 15 mA ICC2 Internal IC consumption with IFB = 50 mA, FSW = 65 kHz and CL = 0 5 − 1.4 2.2 mA ICC3 Internal IC consumption with IFB = 50 mA, FSW = 65 kHz and CL = 1 nF 5 − 2.1 3.0 mA ICC2 Internal IC consumption with IFB = 50 mA, FSW = 100 kHz and CL = 0 5 − 1.7 2.5 mA ICC3 Internal IC consumption with IFB = 50 mA, FSW = 100 kHz and CL = 1 nF 5 − 3.1 4.0 mA ICCstby Internal IC consumption while in skip mode (VCC = 12 V, driving a typical 6 A/600 V MOSFET) 5 ICCLATCH Current flowing into VCC pin that keeps the controller latched – TJ = 0 to 125°C 5 32 mA ICCLATCH Current flowing into VCC pin that keeps the controller latched – TJ = −40°C to 125°C 5 40 mA Symbol VCCON VZENER mA 550 DRIVE OUTPUT Tr Output voltage rise−time @ CL = 1 nF, 10−90% of output signal 6 − 40 − ns Tf Output voltage fall−time @ CL = 1 nF, 10−90% of output signal 6 − 30 − ns ROH Source resistance 6 − 13 − W ROL Sink resistance 6 − 6 − W Peak source current, VGS = 0 V (Note 3) 6 300 mA Peak sink current, VGS = 12 V (Note 3) 6 500 mA VDRVlow DRV pin level at VCC close to VCC(min) with a 33 kW resistor to GND 6 8 − − V VDRVhigh DRV pin level at VCC= 28 V – DRV unloaded 6 10 12 14 V Isource Isink 3. Guaranteed by design CURRENT COMPARATOR mA IIB Input Bias Current @ 0.8 V input level on pin 4 4 VLimit1 Maximum internal current setpoint – TJ = 25 °C 4 0.744 0.8 0.856 V VLimit2 Maximum internal current setpoint – TJ = −40° to 125 °C 4 0.72 0.8 0.88 V www.onsemi.com 4 0.02 NCP1253 ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted) Symbol Rating Pin Min Typ Max Unit Default internal voltage set point for frequency foldback trip point – 45% of Vlimit 4 357 mV Internal peak current setpoint freeze (≈31% of Vlimit) 4 250 mV TDEL Propagation delay from current detection to gate off−state 4 100 TLEB Leading Edge Blanking Duration 4 300 ns TSS Internal soft−start duration activated upon startup, auto−recovery − 4 ms CURRENT COMPARATOR Vfold Vfreeze 150 ns INTERNAL OSCILLATOR fOSC Oscillation frequency (65 kHz version) − 61 65 71 kHz fOSC Oscillation frequency (100 kHz version) − 92 100 108 kHz Dmax Maximum duty−ratio − 76 80 84 % fjitter Frequency jittering in percentage of fOSC − ±5 % fswing Swing frequency − 240 Hz Feedback Section Rup Internal pull−up resistor 2 20 kW Req Equivalent ac resistor from FB to GND 2 16 kW Iratio Pin 2 to current setpoint division ratio − 4.2 Feedback voltage below which the peak current is frozen 2 1.05 V 1.5 V Vfreeze(FB) FREQUENCY FOLDBACK Vfold Frequency foldback level on the feedback pin – ≈45% of maximum peak current − Ftrans Transition frequency below which skip−cycle occurs − Vfold,end End of frequency foldback feedback level, Fsw = Fmin Vskip Skip hysteresis 22 26 30 kHz 350 mV Skip−cycle level voltage on the feedback pin − 300 mV Hysteresis on the skip comparator − 30 mV INTERNAL SLOPE COMPENSATION Vramp Internal ramp level @ 25°C (Note 4) 4 2.5 V Rramp Internal ramp resistance to CS pin 4 20 kW 4. A 1 MW resistor is connected from pin 4 to the ground for the measurement. PROTECTIONS VOVP Latched Overvoltage Protection on the VCC rail 5 TOVPdel Delay before OVP confirmation on the VCC rail 5 Internal auto−recovery fault timer duration − Timer 24 25.5 27 100 130 V ms 20 160 ms Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 5 NCP1253 TYPICAL CHARACTERISTICS 100 kHz 65 kHz Figure 3. Dmax vs. Junction Temperature Figure 4. Fosc vs. Junction Temperature Figure 5. Ftrans vs. Junction Temperature Figure 6. ICC1 vs. Junction Temperature 100 kHz 100 kHz 65 kHz 65 kHz Figure 7. ICC2 vs. Junction Temperature Figure 8. ICC3 vs. Junction Temperature www.onsemi.com 6 NCP1253 TYPICAL CHARACTERISTICS Figure 9. VLimit vs. Junction Temperature Figure 10. VCC(ON) vs. Junction Temperature Figure 11. VCC(min) vs. Junction Temperature Figure 12. VCC(Hyst) vs. Junction Temperature Figure 13. ICCLatch vs. Junction Temperature Figure 14. TLEB vs. Junction Temperature www.onsemi.com 7 NCP1253 TYPICAL CHARACTERISTICS Figure 15. TDEL vs. Junction Temperature Figure 16. TSS vs. Junction Temperature Figure 17. Vfold vs. Junction Temperature Figure 18. Vfold(FB) vs. Junction Temperature Figure 19. Vfold_end vs. Junction Temperature Figure 20. Vskip vs. Junction Temperature www.onsemi.com 8 NCP1253 Figure 21. Vfreeze vs. Junction Temperature Figure 22. Vfreeze(FB) vs. Junction Temperature Figure 23. Timer vs. Junction Temperature Figure 24. VOVP vs. Junction Temperature www.onsemi.com 9 NCP1253 APPLICATION INFORMATION Introduction The NCP1253 implements a standard current mode architecture where the switch−off event is dictated by the peak current setpoint. This component represents the ideal candidate where low part−count and cost effectiveness are the key parameters, particularly in low−cost ac−dc adapters, open−frame power supplies etc. Capitalizing on the NCP1200 series success, the NCP1253 brings all the necessary components normally needed in today modern power supply designs, bringing several enhancements such as a VCC OVP or an adjustable slope compensation signal. • Current−mode operation with internal ramp compensation: implementing peak current mode control at a fixed 65 kHz or 100 kHz frequency, the NCP1253 offers an internal ramp compensation signal that can easily by summed up to the sensed current. Sub harmonic oscillations can thus be compensated via the inclusion of a simple resistor in series with the current−sense information. • Low startup current: reaching a low no−load standby power always represents a difficult exercise when the controller draws a significant amount of current during start−up. Thanks to its proprietary architecture, the NCP1253 is guaranteed to draw less than 15 mA maximum, easing the design of low standby power adapters. • EMI jittering: an internal low−frequency modulation signal varies the pace at which the oscillator frequency is modulated. This helps spreading out energy in conducted noise analysis. To improve the EMI signature at low power levels, the jittering will not be disabled in frequency foldback mode (light load conditions). • Frequency foldback capability: a continuous flow of pulses is not compatible with no−load/light−load standby power requirements. To excel in this domain, the controller observes the feedback pin and when it reaches a level of 1.5 V, the oscillator then starts to reduce its switching frequency as the feedback level continues to decrease. When the feedback pin reaches 1.05 V, the peak current setpoint is internally frozen and the frequency continues to decrease. It can go down to 26 kHz (typical) reached for a feedback level of 350 mV roughly. At this • • • point, if the power continues to drop, the controller enters classical skip−cycle mode. Internal soft−start: a soft−start precludes the main power switch from being stressed upon start−up. In this controller, the soft−start is internally fixed to 4 ms. Soft−start is activated when a new startup sequence occurs or during an auto−recovery hiccup. Latched OVP on Vcc: it is sometimes interesting to implement a circuit protection by sensing the VCC level. This is what NCP1253 does by monitoring its VCC pin. When the voltage on this pin exceeds 25.5 V typical, the pulses are immediately stopped and the part latches off. When the user cycles the VCC down or the converter recovers from a brown−out event, the circuit is reset and the part enters a new start−up sequence. Short−circuit protection: short−circuit and especially over−load protections are difficult to implement when a strong leakage inductance between auxiliary and power windings affects the transformer (the aux winding level does not properly collapse in presence of an output short). Here, every time the internal 0.8 V maximum peak current limit is activated, an error flag is asserted and a time period starts, thanks to an internal timer. When the fault is validated, all pulses are stopped and the controller enters an auto−recovery burst mode, with a soft−start sequence at the beginning of each cycle. As soon as the fault disappears, the SMPS resumes operation. Please note that some version offers an auto−recovery mode as we just described, some do not and latch off in case of a short circuit. Start−up Sequence The NCP1253 start−up voltage is made purposely high to permit large energy storage in a small VCC capacitor value. This helps to operate with a small start−up current which, together with a small Vcc capacitor, will not hamper the start−up time. To further reduce the standby power, the start−up current of the controller is extremely low, below 15 mA. The start−up resistor can therefore be connected to the bulk capacitor or directly to the mains input voltage if you wish to save a few more mW. www.onsemi.com 10 NCP1253 R3 100k R2 100k D2 1N4007 D1 1N4007 R1 200k Cbulk 22uF input mains D6 1N4148 D5 1N4935 Vcc D4 1N4007 D3 1N4007 C1 4.7uF aux. C3 47uF Figure 25. The Startup Resistor Can Be Connected to the Input Mains for Further Power Dissipation Reduction V ac,rmsǸ2 The first step starts with the calculation of the needed VCC capacitor which will supply the controller until the auxiliary winding takes over. Experience shows that this time t1 can be between 5 and 20 ms. Considering that we need at least an energy reservoir for a t1 time of 10 ms, the Vcc capacitor must be larger than: CV CC w I CCt 1 VCC on * VCC min w 3m 10m 9 I CVCC,min + VCC OnC VCC 2.5 w 18 4.7m V ac,rmsǸ2 (eq. 1) R start−up v w 3.3 mF 2.5 w 34 mA * VCC on (eq. 3) R start−up To make sure this current is always greater than 49 mA, the maximum value for Rstart−up can be extracted: Let us select a 4.7 mF capacitor at first and experiments in the laboratory will let us know if we were too optimistic for t1. The VCC capacitor being known, we can now evaluate the charging current we need to bring the Vcc voltage from 0 to the VCCon of the IC, 18 V typical. This current has to be selected to ensure a start−up at the lowest mains (85 V rms) to be less than 3 s (2.5 s for design margin): I charge w p p * VCC on I CVCC,min 85 v 1.414 p * 18 49m (eq. 4) v 413 kW This calculation is purely theoretical, considering a constant charging current. In reality, the take over time can be shorter (or longer!) and it can lead to a reduction of the Vcc capacitor. This brings a decrease in the charging current and an increase of the start−up resistor, for the benefit of standby power. Laboratory experiments on the prototype are thus mandatory to fine tune the converter. If we chose the 400k resistor as suggested by Equation 4, the dissipated power at high line amounts to: (eq. 2) If we account for the 15 mA that will flow inside the controller, then the total charging current delivered by the start−up resistor must be 49 mA. If we connect the start−up network to the mains (half−wave connection then), we know that the average current flowing into this start−up resistor will be the smallest when VCC reaches the VCCon of the controller: If we account for the 15 mA that will flow inside the controller, then the total charging current delivered by the start−up resistor must be 49 mA. If we connect the start−up network to the mains (half−wave connection then), we know that the average current flowing into this start−up resistor will be the smallest when VCC reaches the VCCon of the controller: P Rstart,max + V ac,peak 2 4R start−up + ǒ320 4 Ǹ2Ǔ 400k 2 + 105k (eq. 5) 1.6Meg + 66 mW Now that the first VCC capacitor has been selected, we must ensure that the self−supply does not disappear when in no−load conditions. In this mode, the skip−cycle can be so deep that refreshing pulses are likely to be widely spaced, inducing a large ripple on the VCC capacitor. If this ripple is too large, chances exist to touch the VCCmin and reset the controller into a new start−up sequence. A solution is to grow this capacitor but it will obviously be detrimental to the start−up time. The option offered in Figure 25 elegantly www.onsemi.com 11 NCP1253 solves this potential issue by adding an extra capacitor on the auxiliary winding. However, this component is separated from the VCC pin via a simple diode. You therefore have the ability to grow this capacitor as you need to ensure the self−supply of the controller without jeopardizing the start−up time and standby power. In this case, the current is no longer made of 5 ms “holes” and the part can be maintained at a low input voltage. Experiments show that these 2 MW resistor help to maintain the latch down to less than 50 Vrms, giving an excellent design margin. Standby power with this approach was also improved compared to Figure 25 solution. Please note that these resistors also ensure the discharge of the X2−capacitor up to a 0.47 mF type. The de−latch of the SCR occurs when the injected current in the VCC pin falls below the minimum stated in the data−sheet (32 mA at room temp). Triggering the SCR The latched−state of the NCP1253 is maintained via an internal thyristor (SCR). When the voltage on the Vcc pin exceeds the internal latch voltage, the SCR is fired and immediately stops the output pulses. When this happens, all pulses are stopped and VCC is discharged to a fix level of 7 V typically: the circuit is latched and the converter no longer delivers pulses. To maintain the latched−state, a permanent current must be injected in the part. If too low of a current, the part de−latches and the converter resumes operation. This current is characterized to 32 mA as a minimum but we recommend including a design margin and select a value around 60 mA. The test is to latch the part and reduce the input voltage until it de−latches. If you de−latch at Vin = 70 Vrms for a minimum voltage of 85 Vrms, you are fine. If it precociously recovers, you will have to increase the start−up current, unfortunately to the detriment of standby power. The most sensitive configuration is actually that of the half−wave connection proposed in Figure 25. As the current disappears 5 ms for a 10 ms period (50 Hz input source), the latch can potentially open at low line. If you really reduce the start−up current for a low standby power design, you must ensure enough current in the SCR in case of a faulty event. An alternate connection to the above is shown below (Figure 26): 1 Meg N L1 Frequency Foldback The reduction of no−load standby power associated with the need for improving the efficiency, requires a change in the traditional fixed−frequency type of operation. This controller implements a switching frequency foldback when the feedback voltage passes below a certain level, Vfold, set around 1.5 V. At this point, the oscillator enters frequency foldback and reduces its switching frequency. The peak current setpoint is following the feedback pin until its level reaches 1.05 V. Below this value, the peak current freezes to Vfold/4.2 (250 mV or 31% of the maximum 0.8−V setpoint) and the only way to further reduce the transmitted power is to diminish the operating frequency down to 26 kHz. This value is reached at a feedback voltage level of 350 mV typically. Below this point, if the output power continues to decrease, the part enters skip cycle for the best noise−free performance in no−load conditions. depicts the adopted scheme for the part. 1 Meg Vcc Figure 26. The Full−wave Connection Ensures Latch Current Continuity as well as a X2−Discharge Path. www.onsemi.com 12 NCP1253 Frequency Peak current setpoint Fsw FB VCS max 65 kHz max 0.8 V [0.36 V min 26 kHz [0.25 V min VFB 350 mV Vfold,end 1.5 V Vfold Vfreeze Vfold 3.4 V 1.05 V VFB 3.4 V 1.5 V Figure 27. By Observing the Voltage on the Feedback Pin, the Controller Reduces its Switching Frequency for an Improved Performance at Light Load Auto−recovery Short−Circuit Protection to the resistive starting network. When VCC reaches VCCON, the controller attempts to re−start, checking for the absence of the fault. If the fault is still there, the supply enters another cycle of so−called hiccup. If the fault has disappeared, the power supply resumes operations. Please note that the soft−start is activated during each of the re−start sequence. In case of output short−circuit or if the power supply experiences a severe overloading situation, an internal error flag is raised and starts a countdown timer. If the flag is asserted longer than 100 ms, the driving pulses are stopped and VCC falls down as the auxiliary pulses are missing. When it crosses VCC(min), the controller consumption is down to a few mA and the VCC slowly builds up again thanks 15.9 4.32 14.8 9.90 3.35 6.05 vcc in volts 23.6 3.89 ilprim in amperes Plot1 vdrv in volts 1 vcc 2 vdrv 3 ilprim 1 Vcc (t ) VDRV (t ) 2.38 2 −2.72 −2.12 1.41 ILp (t ) SS −11.5 −8.13 445m 3 500u 1.50m 2.50m time in seconds 3.50m 4.50m Figure 28. An Auto−Recovery Hiccup Mode is Entered in Case a Faulty Event Longer Than 100 ms is Acknowledged by the Controller Ramp compensation CCM−operated current−mode converters. These oscillations take place at half the switching frequency and occur only during Continuous Conduction Mode (CCM) with a duty−cycle greater than 50%. To lower the current loop gain, one usually injects between 50% and 100% of the inductor downslope. The NCP1253 includes an internal ramp compensation signal. This is the buffered oscillator clock delivered during the on time only. Its amplitude is around 2.5 V at the maximum duty−cycle. Ramp compensation is a known means used to cure sub harmonic oscillations in www.onsemi.com 13 NCP1253 2.5 V 0V ON latch reset 20k Rcomp + L.E.B CS − Rsense from FB setpoint Figure 29. Inserting a Resistor in Series with the Current Sense Information Brings Ramp Compensation and Stabilizes the Converter in CCM Operation S sense + S PR sense + 103k In the NCP1253 controller, the oscillator ramp features a 2.5 V swing. If the clock operates at a 65 kHz frequency, then the available oscillator slope corresponds to: S ramp + V ramp,peakD max T SW 2.5 0.8 + 15m If we select 50% of the downslope as the required amount of ramp compensation, then we shall inject a ramp whose slope is 17 mV/ms. Our internal compensation being of 133 mV/ms, the divider ratio (divratio) between Rcomp and the internal 20 kW resistor is: (eq. 6) In our flyback design, let’s assume that our primary inductance Lp is 770 mH, and the SMPS delivers 19 V with a Np :Ns ratio of 1:0.25. The off−time primary current slope Sp is thus given by: N SP + P LP + (19 ) 0.8) 770m divratio + 17m + 0.127 133m (eq. 9) The series compensation resistor value is thus: R comp + R rampdivratio + 20k (eq. 7) 4 (eq. 8) + 34 kVńs or 34 mVńms + 133 kVńs or 133 mVńms ǒV out ) V fǓ N s 0.33 0.127 [ 2.5 kW (eq. 10) A resistor of the above value will then be inserted from the sense resistor to the current sense pin. We recommend adding a small 100 pF capacitor, from the current sense pin to the controller ground for improved noise immunity. Please make sure both components are located very close to the controller. + 103 kAńs Given a sense resistor of 330 mW, the above current ramp turns into a voltage ramp of the following amplitude: www.onsemi.com 14 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSOP−6 CASE 318G−02 ISSUE V 1 SCALE 2:1 D H ÉÉ ÉÉ 6 E1 1 NOTE 5 5 2 L2 4 GAUGE PLANE E 3 L b SEATING PLANE C DETAIL Z e DIM A A1 b c D E E1 e L L2 M c A 0.05 M DATE 12 JUN 2012 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D AND E1 ARE DETERMINED AT DATUM H. 5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE. A1 DETAIL Z MIN 0.90 0.01 0.25 0.10 2.90 2.50 1.30 0.85 0.20 0° MILLIMETERS NOM MAX 1.00 1.10 0.06 0.10 0.38 0.50 0.18 0.26 3.00 3.10 2.75 3.00 1.50 1.70 0.95 1.05 0.40 0.60 0.25 BSC 10° − STYLE 1: PIN 1. DRAIN 2. DRAIN 3. GATE 4. SOURCE 5. DRAIN 6. DRAIN STYLE 2: PIN 1. EMITTER 2 2. BASE 1 3. COLLECTOR 1 4. EMITTER 1 5. BASE 2 6. COLLECTOR 2 STYLE 3: PIN 1. ENABLE 2. N/C 3. R BOOST 4. Vz 5. V in 6. V out STYLE 4: PIN 1. N/C 2. V in 3. NOT USED 4. GROUND 5. ENABLE 6. LOAD STYLE 5: PIN 1. EMITTER 2 2. BASE 2 3. COLLECTOR 1 4. EMITTER 1 5. BASE 1 6. COLLECTOR 2 STYLE 6: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. EMITTER 5. COLLECTOR 6. COLLECTOR STYLE 7: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. N/C 5. COLLECTOR 6. EMITTER STYLE 8: PIN 1. Vbus 2. D(in) 3. D(in)+ 4. D(out)+ 5. D(out) 6. GND STYLE 9: PIN 1. LOW VOLTAGE GATE 2. DRAIN 3. SOURCE 4. DRAIN 5. DRAIN 6. HIGH VOLTAGE GATE STYLE 10: PIN 1. D(OUT)+ 2. GND 3. D(OUT)− 4. D(IN)− 5. VBUS 6. D(IN)+ STYLE 11: PIN 1. SOURCE 1 2. DRAIN 2 3. DRAIN 2 4. SOURCE 2 5. GATE 1 6. DRAIN 1/GATE 2 STYLE 12: PIN 1. I/O 2. GROUND 3. I/O 4. I/O 5. VCC 6. I/O STYLE 13: PIN 1. GATE 1 2. SOURCE 2 3. GATE 2 4. DRAIN 2 5. SOURCE 1 6. DRAIN 1 STYLE 14: PIN 1. ANODE 2. SOURCE 3. GATE 4. CATHODE/DRAIN 5. CATHODE/DRAIN 6. CATHODE/DRAIN STYLE 15: PIN 1. ANODE 2. SOURCE 3. GATE 4. DRAIN 5. N/C 6. CATHODE STYLE 16: PIN 1. ANODE/CATHODE 2. BASE 3. EMITTER 4. COLLECTOR 5. ANODE 6. CATHODE STYLE 17: PIN 1. EMITTER 2. BASE 3. ANODE/CATHODE 4. ANODE 5. CATHODE 6. COLLECTOR GENERIC MARKING DIAGRAM* RECOMMENDED SOLDERING FOOTPRINT* 6X 0.60 XXXAYWG G 1 6X 3.20 XXX A Y W G 0.95 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98ASB14888C TSOP−6 1 IC 0.95 XXX MG G = Specific Device Code =Assembly Location = Year = Work Week = Pb−Free Package STANDARD XXX = Specific Device Code M = Date Code G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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