PWM Controller, Input
Current Mode, Ultra Wide
NCP12700
The NCP12700 is a fixed frequency, peak current mode, PWM
controller containing all of the features necessary for implementing
single−ended power converter topologies. The device features a high
voltage startup capable of operating over a wide input range and
supplying at least 15 mA to provide temporary bias to VCC during
system startup. The device contains a programmable oscillator
capable of operating from 100 kHz to 1 MHz and integrates slope
compensation to prevent subharmonic oscillations. The controller
offers an adjustable soft−start, input voltage UVLO protection, and an
adjustable Over−Power Protection circuit which limits the total power
capability of the circuit as the input voltage increases, easing the
system thermal design. The UVLO pin also features a shutdown
comparator which allows for an external signal to disable switching
and bring the controller into a low quiescent state.
The NCP12700 contains a suite of protection features including
cycle−by−cycle peak current limiting, timer−based overload
protection, and a FLT pin which can be interfaced with an NTC and an
auxiliary winding to provide system thermal protection and output
over−voltage protection. All protection features place the device into a
low quiescent fault mode and recovery from fault mode is dependent
on the device option.
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1
WQFN10
MT SUFFIX
CASE 511DV
MARKING DIAGRAMS
12700x
ALYWG
G
10
700x
ALYW
Common General Features
•
•
•
•
•
•
•
•
•
•
•
Wide Input Range (9 – 120/200 V; MSOP10/WQFN10)
Startup Regulator Circuit with 15 mA Capability
Current Mode Control with Integrated Slope Compensation
Suitable for Flyback or Forward Converters
Single Resistor Programmable Oscillator
1 A / 2.8 A Source / Sink Gate Driver
User Adjustable Soft−Start Ramp
Input Voltage UVLO with Hysteresis
Shutdown Threshold for External Disable
Skip Cycle Mode for Low Standby Power
This is a Pb−Free Device
Fault Protection Features
12700 or 700 = Specific Device Code
x
= A, B or C
A
= Assembly Site
L
= Wafer Lot Number
YW
= Assembly Start Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
• Single−ended Power Converters including CCM/DCM
•
•
•
•
Protection
• Output OVP Fault Interface
• Fault Auto−recovery Mode with 1 s Auto−recovery
Period
November, 2020 − Rev. 3
1
Typical Applications
• User Adjustable Over−Power Protection
• Overload Protection with 30 ms Overload Timer
• NTC−Compatible Fault Interface for Thermal
© Semiconductor Components Industries, LLC, 2018
MSOP
DN SUFFIX
CASE 846AE
1
Flyback and Forward Converters
Telecommunications Power Converters
Industrial Power Converter Modules
Transportation & Railway Power Modules
Power over Ethernet Powered Devices (PoE PD)
Publication Order Number:
NCP12700/D
NCP12700
VOUT
VIN
UVLO VIN
FLT
VCC
SS
DRV
RT
GND
COMP CS
FEEDBACK
WITH
ISOLATION
Figure 1. Typical Application Circuit for Vin = 12 − 160 V
VIN
VOUT
UVLO VIN
FLT
VCC
SS
DRV
RT
GND
COMP CS
FEEDBACK
WITH
ISOLATION
Figure 2. Typical Application Circuit for Vin = 9 − 18 V
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2
NCP12700
V CC
HV Startup
VIN
9
10
VCC
LOGIC
VCCON
VCC(OVP)
VCC(UVLO)
VDD VDRV
Regulation
Over−Power
Protection
UVLO
ICS(OPP)
SHDN
UVLO
Detection
1
C CC
INTERNAL
REGULATOR
VCCON
ENABLE
FAULT
7
GND
3
SS
START
MAIN
LOGIC
STOP
VDD
ISS
ENABLE
IUVLO(HYS)
START
SS_END
TSD
TSD
VSS
SS
CONTROL
START
D MAX
RT
VDD
I FLT
OSC
4
CLK
FAULT
TSD
SS_END
SHDN
OVLD
VDD
FAULT
Logic
2
FLT
8
DRV
VCC(OVP)
VCC(UVLO)
ICS(OPP)
DMAX
CS
LEB
Block
6
VDD
STOP
OVLD
Slope
Comp
DRV
VDRV
5k
COMP
PWM
LOGIC
1/6
5
CLK
S
Q
R
VCOMP(skip)
VCOMP(skip_hys)
V SS
1/6
Figure 3. Block Diagram
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3
UVLO
FLT
SS
RT
COMP
VIN
PINOUTS
VIN
VCC
DRV
GND
CS
DRV
GND
CS
EP
SS
RT
COMP
UVLO
FLT
VCC
NCP12700
(Top Views)
Table 1. PIN FUNCTION DESCRIPTION
MSOP10
WQFN10
Pin Name
Pin Description
1
9
UVLO
The UVLO pin is the input to the Standby and UVLO comparators. A resistor divider between
the power supply input voltage and ground is connected to the UVLO pin to set the input voltage level at which the controller will be enabled. UVLO Hysteresis is set by a 5 mA pull−down
current source. An externally supplied pull−down signal can also be used to disable the controller. The UVLO pin is also used to determine the Over−Power Protection current supplied to
the CS pin.
2
10
FLT
The FLT pin is the input to a window comparator which provides an upper and lower fault
threshold. When either threshold is tripped, the controller enters the fault mode which can be a
permanent latch off or a minimum 1 s auto−recovery period. A precision current source is output from the FLT pin allowing an NTC to ground to be placed at the pin for system Over−temperature protection. The upper threshold can be used for output over−voltage protection
sensed through the auxiliary winding or as a general purpose fault.
3
1
SS
The SS pin sets the soft−start ramp of the peak current limit when the controller is enabled. An
internal 15 mA current source and an external capacitor to ground are used to control the ramp
rate. Typical soft start capacitor values will be in the range of 10 nF to 100 nF.
4
2
RT
The RT pin sets the oscillator frequency in the controller. This pin requires a resistor to ground
located close to the IC. Typical RT values are in the range of 10 kW – 100 kW.
5
3
COMP
6
4
CS
7
5
GND
This pin is the controller ground. For the WQFN package the exposed pad (EP) should be
connected to GND.
8
6
DRV
The DRV pin is a high current output used to drive the external MOSFET gate. DRV has
source and sink capability of 1 A and 2.8 A, respectively.
9
7
VCC
The VCC pin provides bias to the controller. An external decoupling capacitor to ground in the
range of 1 – 10 mF is recommended.
10
8
VIN
The VIN pin is the input to the high voltage startup regulator. The regulator is capable of sourcing > 15 mA to temporarily bias VCC while the application is starting up.
The COMP pin provides the compensated error voltage for the PWM and Skip comparators.
An internal 5 kW pull−up resistor is connected to the COMP pin and can be used to bias the
transistor of an opto−coupler.
The CS pin is the current sense input for the PWM and Current Limit comparators. The comparator input is held low for 60 ns after the DRV goes high to prevent leading edge current
spikes from tripping the comparators. An external low pass filter is recommended for improved
noise immunity. The external filter resistor is also used to determine the amount of Over−Power Protection applied to the current sense.
ORDERING INFORMATION
Package
VCS(LIM)
OTP Fault
OVP Fault
Shipping†
NCP12700ADNR2G
MSOP10
495 mV
Latch
Latch
4000 / Tape & Reel
NCP12700BDNR2G
MSOP10
495 mV
Autorecovery
Autorecovery
4000 / Tape & Reel
NCP12700CDNR2G
(In Development)
MSOP10
250 mV
Autorecovery
Autorecovery
4000 / Tape & Reel
NCP12700BMTTXG
WQFN10
495 mV
Autorecovery
Autorecovery
3000 / Tape & Reel
NCP12700CMTTXG
(In Development)
WQFN10
250 mV
Autorecovery
Autorecovery
3000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
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4
NCP12700
Table 2. MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VIN(MAX)
120
200
V
IIN(MAX)
50
mA
Supply Voltage
VCC(MAX)
−0.3 to 30
V
Supply Current
ICC(MAX)
50
mA
DRV Voltage (Note 1)
VDRV(MAX)
−0.3 V to VDRV(high)
V
DRV Current (Peak)
IDRV(MAX)
3.25
A
FLT Voltage
VFLT(MAX)
VCC + 1.25
V
FLT Current
IFLT(MAX)
10
mA
Max Voltage on Signal Pins
VSIG(MAX)
−0.3 to 5.5
V
Max Current on Signal Pins
ISIG(MAX)
10
mA
High Voltage Startup Voltage
(MSOP10)
(WQFN10)
High Voltage Startup Current
Thermal Resistance Junction−to−Air (Note 2)
(MSOP10)
(WQFN10)
RθJ−A
165
51
°C/W
Junction−to−Top Thermal Characterization Parameter
(MSOP10)
(WQFN10)
YJ−C
10
12
°C/W
TJMAX
150
°C
PD
Internally Limited
W
TSTG
−55 to 150
°C
TJ
−40 to 125
°C
Maximum Junction Temperature
Maximum Power Dissipation
(MSOP10)
(WQFN10)
Storage Temperature Range
Operating Temperature Range
ESD Capability (Note 3)
Human Body Model per JEDEC Standard JESD22−A114E
Charge Device Model per JEDEC Standard JESD22−C101E
V
2000
1000
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Maximum driver voltage is limited by the driver clamp voltage, VDRV(high), when VCC exceeds the driver clamp voltage. Otherwise, the
maximum driver voltage is VCC.
2. Per JEDEC specification JESD51.7 using two 1 oz copper planes with board size = 80x80x1.6 mm
3. This device series contains ESD protection and exceeds the following tests:
Human Body Model 2000 V per JEDEC Standard JESD22−A114E
Charge Device Model TBD per JEDEC Standard JESD22−C101E
4. This device contains latch−up protection and has been tested per JEDEC JESD78D, Class I and exceeds +/−100 mA (TBD).
Table 3. RECOMMENDED OPERATING CONDITIONS
Rating
VIN Voltage
(MSOP10)
(WQFN10)
Supply Voltage − All
Operating Temperature Range
Symbol
Value
Unit
VIN
9 – 100
12 – 160
V
VCC
9 – 20 V
V
TJ
−40 to 125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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5
NCP12700
Table 4. ELECTRICAL CHARACTERISTICS (VIN = 12 V, VCC = 12 V, VCOMP = Open, VFLT = Open, CDRV = 1 nF, RT = 49.9k, VCS
= 0 V, VSS = Open, VUVLO = 1.2, for typical values TJ = 25°C, for min/max values, TJ is – 40°C to 125°C, unless otherwise noted)
Characteristics
Test Condition
Symbol
Min
Typ
Max
Unit
VCC = Open, ICC = 5 mA
VCC(REG)
7.6
8
8.4
V
VIN = 9 V, VCC = 7 V
IVIN(SRC)
15
VCC = VCC(off) + 100 mV
IVIN(LIM)
Off−State Leakage Current (xMTTXG)
VCC = Open, VIN = 160 V, VUVLO = 0
IVIN(OFF)
100
mA
Off−State Leakage Current (xDNR2G)
VCC = Open, VIN = 120 V, VUVLO = 0
IVIN(OFF)
100
mA
Supply Voltage
Startup Threshold
VCC increasing
VCC(on)
Minimum Operating Voltage
VCC decreasing
VCC(off)
HIGH VOLTAGE STARTUP REGULATOR
Regulated Voltage
Current Source Capability
Current Source Limit
mA
30
mA
SUPPLY CIRCUIT
V
VCC(REG) –
350 mV
6.2
6.5
VCC(REG) –
100 mV
6.8
Supply Over−Voltage Protection
VCC(OVP)
28
V
VCC OVP Detection Filter Delay
tVCCOVP
3
ms
(DLY)
Startup Delay
Measured from VCC(ON) to SS
tON(Dly)
VUVLO = 0 V
VUVLO = 0.7 V
CDRV = Open, VCOMP = 2 V
VFLT = 0 V
ICC(SHDN)
ICC(STBY)
ICC(EN)
ICC(FLT)
−
−
−
−
NCP12700CDNR2G
Other parts
VCS(LIM)
Step VCS from 0 – 0.6 V
tCS(DLY)
Short Circuit Protection (SCP) Current
Limit Threshold
NCP12700CDNR2G
Other parts
VSCP(LIM)
Propagation Delay From Short Circuit
Limit to DRV Low
VCS = 0.75 V
tSCP(DLY)
Short Circuit Counter
VCS = 0.75 V
NSCP
Supply Current
SHDN
STBY
Enable
Fault
25
ms
−
−
−
−
50
750
4
500
mA
mA
mA
mA
235
465
250
495
265
525
mV
−
−
75
ns
CURRENT SENSE
Current Limit Comparator Threshold
Propagation Delay From Current
Sense Limit to DRV Low
312.5
625
−
−
mV
75
ns
4
CS Leading Edge Blanking (LEB)
tLEB(CS)
75
100
125
ns
SCP Leading Edge Blanking
tLEB(SCP)
45
60
75
ns
−
55
W
24
30
36
ms
35
83
50
102
65
123
CS LEB Pull−down Resistance
Overload Timer Duration
Applied Slope Compensation @ Current Limit Comparator
RPD(LEB)
VCS = 0.6 V
tCS(OVLD)
VCOMP = Open; Measured at D80%
NCP12700CDNR2G
Other parts
VSLP(ILIM)
Duty Cycle Where Slope Compensating Ramp Begins
D40%
40
VCOMP = 2 V
KPWM
6
VCOMP = 2 V, Step from CS 0– 0.4 V
tPWM(Dly)
−
mV
%
COMP SECTION
PWM to COMP Gain Through Resistor
Divider
PWM Propagation Delay to DRV Low
COMP Open Pin Voltage
VCOMP(open)
4
75
4.7
ns
V
COMP Output Current
VCOMP = 0
ICOMP
0.84
1
1.2
mA
Maximum Duty Cycle
VCOMP = Open
DMAX
76
80
84
%
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NCP12700
Table 4. ELECTRICAL CHARACTERISTICS (VIN = 12 V, VCC = 12 V, VCOMP = Open, VFLT = Open, CDRV = 1 nF, RT = 49.9k, VCS
= 0 V, VSS = Open, VUVLO = 1.2, for typical values TJ = 25°C, for min/max values, TJ is – 40°C to 125°C, unless otherwise noted)
Characteristics
Test Condition
Symbol
Min
Typ
Max
Unit
COMP SECTION
COMP Skip Threshold
VCOMP(skip)
300
mV
COMP Skip Hysteresis
VCOMP
(skip_hys)
25
mV
Minimum Duty Cycle
Applied Slope Compensation @ PWM
Comparator
VCOMP = 0
DMIN
VCOMP = 2 V; Measured at D80%
NCP12700CDNR2G
Other parts
VSLP(PWM)
0
30
77
40
98
50
117
%
mV
SOFT START
Soft−Start Open Pin Voltage
VSS(open)
Soft−Start End Threshold
VSS(end)
2.85
3
3.15
V
VSS = 3 V
ISS
12
15
18
mA
NCP12700CDNR2G
Other parts
KSS
100
W
Soft−Start Current
Soft−Start to CS Divider
Soft−Start Discharge Resistance
5.0
V
12
6
RSS(DIS)
OSCILLATOR
FOSC1
185
200
215
kHz
RT = 100 kW
FOSC2
95
100
105
kHz
Oscillator Frequency 3
RT = 20 kW
FOSC3
450
500
550
kHz
Oscillator Frequency 4
RT = 9.09 kW
FOSC4
Standby Threshold
VUVLO increasing
VSTBY(th)
0.35
0.5
0.65
V
Reset Threshold
VUVLO decreasing
VRST(th)
0.3
0.45
0.6
V
Standby Hysteresis
VUVLO decreasing
VSTBY(HYS)
Oscillator Frequency 1
Oscillator Frequency 2
1000
kHz
UNDER−VOLTAGE LOCKOUT (UVLO)
Standby Detection RC Filter
tSTBY(DLY)
UVLO Threshold
VUVLO increasing
VUVLO(th)
UVLO Threshold Hysteresis
VUVLO decreasing
VUVLO(HYS)
UVLO Hysteresis Current
UVLO Detection Delay Filter
50
VUVLO = VUVLO(th) − 20 mV
mV
5
765
800
ms
830
15
IUVLO(HYS)
4.5
tUVLO(DLY)
0.5
5
mV
mV
5.5
mA
1
ms
OVER−POWER PROTECTION (OPP)
VOPP(START)
UVLO Voltage Above Which OPP Applied
OPP Gain
Maximum Current (Operating Point)
Maximum Current
1
V
Gm(OPP)
135
150
165
mA / V
VUVLO = 2.33 V
ICS(OPP1)
180
200
220
mA
VUVLO = 4 V
ICS
(OPP_MAX)
200
mA
VOPP(0%)
0.8
V
VOPP(100%)
2
V
COMP Threshold Voltage Above
Which OPP is Applied
COMP Threshold Voltage For 100%
OPP
GATE DRIVE
DRV Rise Time
VDRV = 1.2 V to 10.8 V
tDRV(rise)
6
10
15
ns
DRV Fall Time
VDRV = 10.8 V to 1.2 V
tDRV(fall)
2.5
4
10
ns
VDRV = 6 V
IDRV(SRC)
DRV Source Current
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7
1.0
A
NCP12700
Table 4. ELECTRICAL CHARACTERISTICS (VIN = 12 V, VCC = 12 V, VCOMP = Open, VFLT = Open, CDRV = 1 nF, RT = 49.9k, VCS
= 0 V, VSS = Open, VUVLO = 1.2, for typical values TJ = 25°C, for min/max values, TJ is – 40°C to 125°C, unless otherwise noted)
Characteristics
Test Condition
Symbol
Min
Typ
Max
Unit
VDRV = 6 V
IDRV(SNK)
DRV Clamp Voltage
VCC = 20 V, RDRV = 10 kW
VDRV(clamp)
10
Minimum DRV Voltage
VCC = VCC(OFF) + 100 mV,
RDRV = 10 kW
VDRV(MIN)
6
Fault Source Current
IFLT
80
85
90
mA
OTP Fault Threshold
VFLT(OTP)
0.47
0.5
0.53
V
OTP Detection Filter Delay
tOTP(DLY)
10
20
30
ms
OTP Fault Recovery Threshold
VFLT(REC)
0.846
0.9
0.954
V
OVP Fault Threshold
VFLT(OVP)
2.8
3
3.2
V
OVP Detection Filter Delay
tOVP(DLY)
3
5
7
ms
VFLT(CLAMP)
1.13
1.35
1.57
V
GATE DRIVE
DRV Sink Current
2.8
12
A
14
V
V
FAULT PROTECTION
Fault Clamp Voltage
VFLT = Open
Fault Clamp Resistance
RFLT(CLAMP)
Auto−recovery Timer
1.6
kW
tAR
0.8
1
1.2
s
TSHDN
150
165
180
°C
THERMAL SHUTDOWN
Thermal Shutdown
Thermal Shutdown Hysteresis
TSHDN(hys)
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8
25
°C
NCP12700
Application Information
Figure 4 details the operation of the startup regulator.
When VIN is applied, the regulator will immediately begin
sourcing current to charge VCC. Initially the startup will
supply approximately 10 mA. Once VCC builds up to ~ 3 V,
the control loop for the HV regulator will activate and the
source current will be regulated to 30 mA until VCC reaches
the VCC(REG) level of 8 V. The HV startup is a linear
regulator which can continue to supply and regulate VCC at
8 V. The recommended VCC capacitance to ensure stability
of the regulator is 1 – 10 mF.
While the VCC voltage is below the VCC(ON) threshold the
controller will remain in a low quiescent state to allow for
rapid charging of VCC and fast startup of the application.
Once the VCC voltage reaches the VCC(ON) threshold,
approximately 200 mV below the VCC(REG) level, the
controller will exit the low quiescent state and begin
delivering drive pulses. While the output voltage is building
up, the startup regulator will continue to supply the current
necessary to maintain VCC at the VCC(REG) level. For low
input voltage applications, the startup regulator has been
designed to guarantee a minimum of 15 mA source
capability with 2 V of headroom.
In typical applications an auxiliary winding will be used
to provide bias to VCC once the converter is switching. This
allows for the most efficient operation of the system. Once
the auxiliary winding pulls the VCC voltage above
VCC(REG), the HV regulator will shut off. In normal
operation the VCC voltage can be biased above the voltage
at VIN and can support voltages up to 28 V. A VCC OVP
protection feature will trigger at 28 V, disabling switching of
the converter to prevent the auxiliary winding voltage from
damaging the controller.
The NCP12700 is a fixed frequency, peak current mode,
PWM controller containing all of the features necessary for
implementing single−ended power converter topologies.
The device features an ultra−wide range, high voltage
startup regulator capable of regulating VCC across an input
voltage range of 9 – 120 V (xDNR2G) or 9 – 200 V
(xMTTXG). The controller is designed for high speed
operation including a programmable oscillator capable of
operating from 100 kHz to 1 MHz and total propagation
delays less than 75 ns in the PWM path. The NCP12700
integrates slope compensation to prevent subharmonic
oscillations and an Input Voltage Compensation /
Over−Power Protection (OPP) feature that limits the
converter power delivery capability across input voltage,
easing system thermal design. The controller offers an
adjustable soft−start, input voltage UVLO protection, and a
suite of protection features including cycle−by−cycle
current limit and a FLT pin with a NTC interface for system
thermal protection. The UVLO pin also features a shutdown
comparator which allows for an externally applied
pull−down signal to disable switching and bring the
controller into a low quiescent state.
Ultra−Wide Range HV Startup Regulator
The NCP12700 features a high voltage startup regulator
capable of operating across input voltage ranges of 9−120 V
(xDNR2G) or 9−200 V (xMTTXG). The ultra−wide range
capability of the regulator allows for direct connection of
VIN to the converter input voltage without requiring
external components. The regulator’s input voltage
capabilities support a wide range of industrial, medical,
telecom, and transportation applications.
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9
NCP12700
VCC
VIN = 12 V
VCC(REG)
VCC(ON)
VCC(OFF)
VCC = 3 V
Output
Voltage
IVIN
IVIN = 30 mA
IVIN = ICC
IVIN ~ 10 mA
time
Figure 4. Startup Timing Diagram
When input voltage is initially applied to the converter the
device will be in a shutdown/reset (SHDN) state until the
UVLO voltage crosses the VSTBY(th) threshold of 0.5 V. In
the SHDN state the device consumption will be limited to
the ICC(SHDN) value of 50 mA. When the UVLO voltage goes
above VSTBY(th) the device transitions into standby mode
and the consumption increases to the ICC(STBY) limit of
750 mA maximum. The low current consumption in the
shutdown and standby modes allow VCC to rapidly charge
to the VCC(ON) threshold.
Once VCC has charged to VCC(ON) the device will enable
drive pulses when the UVLO voltage exceeds the VUVLO(th)
of 0.8 V and disables drive pulses when the UVLO voltage
falls below 0.8 V by VUVLO(HYS). Prior to enabling drive
pulses the device also activates a pull−down current source,
IUVLO(HYS), of 5 mA. The current source works in
combination with VUVLO(HYS) to set the input voltage
hysteresis for enabling and disabling switching operation of
the converter. A resistor, RUVLO(HYS), can be used to
provide additional hysteresis between the enable and disable
thresholds. Equation 1 and Equation 2 can be used to
calculate the necessary component values in the resistor
divider network.
Once the device has begun delivering drive pulses it will
remain active as long as VCC remains above the VCC(OFF)
threshold of 6.5 V. Either the auxiliary winding or the HV
startup regulator will provide the bias necessary to keep VCC
above this level. If VCC does drop below the VCC(OFF)
threshold the controller will inhibit drive pulses, the device
will reset and once again enter a low quiescent state. This
should only occur if the input voltage to the converter has
been removed but can also be an indication of excessive
external loading on VCC.
Input Voltage UVLO Detection
The NCP12700 features line voltage UVLO detection to
ensure that the converter becomes operational only after
meeting a minimum input voltage threshold thereby
protecting the converter from thermal stress at low input
voltages. A functional block diagram of the UVLO
detection circuitry is shown in Figure 5. The input line
voltage is monitored through a resistor divider network
allowing the user to set the thresholds for when to enable and
disable the converter. Typical pull−down resistors in the
divider network will be in the range of 5 – 20 kW and pull−up
resistors will typically be in the range of 50 – 500 kW.
External capacitive filtering on the order of 10 nF is also
advisable.
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10
NCP12700
5 ms
VSTBY(th)
V IN
V RST(th)
S
Q
STBY
R
Q
SHDN
R UVLO1
V UVLO(th)
R UVLO(HYS)
ENABLE
IUVLO(HYS)
UVLO
RUVLO2
Figure 5. UVLO Block Diagram
V IN,START +
ǒ
V UVLO(th) )
ǒ
Ǔ
R UVLO1R UVLO2
) R UVLO(HYS)
R UVLO1 ) R UVLO2
V IN,STOP + ǒV UVLO(th) * V UVLO(HYS)Ǔ
ǒ
Ǔǒ
I UVLO(HYS)
Ǔ
R UVLO1 ) R UVLO2
R UVLO2
Ǔ
R UVLO1 ) R UVLO2
R UVLO2
(eq. 1)
(eq. 2)
Input Voltage Compensation / Over−Power Protection
P + 0.5
L
ǒI 2 P * I 2 VǓ
f SW
input line voltage through the UVLO pin. When the UVLO
voltage crosses the VOPP(START) threshold, typically 1 V, the
OTA begins sourcing a current out of the CS pin. The current
injected out of the CS pin will be according to Equation 4
where the typical transconductance, Gm(OPP), is 150 mA/V
and the maximum current is limited to the ICS(OPP_MAX)
value of 200 mA.
(eq. 3)
In a CCM flyback converter the output power capability
is defined by Equation 3 where IP is the peak transformer
current, IV is the valley or minimum transformer current, L
is the primary inductance, and fSW is switching frequency.
In a DCM flyback converter the valley current becomes 0
and Equation 3 still applies. The peak current capability of
the converter can be impacted by several variables including
input voltage and the operating duty cycle due to the internal
slope compensation in the NCP12700. Managing the peak
current limit over the operating input voltage range will limit
the total power capability and ease system thermal design.
The NCP12700 features the Input Voltage Compensation
/ Over−Power Protection (OPP) circuitry shown in Figure 6.
The Over−Power Protection circuit functions as a
transconductance amplifier which senses an image of the
I CS(OPP) + G m(OPP) @ ǒV UVLO * V OPP(START)Ǔ (eq. 4)
Good SMPS design practice for current mode control
includes a small RC filter in series between the current sense
resistor and the CS pin of the controller. Typical values for
the resistor in the RC filter are 500 – 1 kW. The user can then
limit the peak current capability of the converter by setting
the RCS resistor value and can reduce the peak current
capability of the converter by 20 – 40% with these values.
V IN
V DD
R UVLO1
COMP
UVLO
R UVLO2
DRV
VOPP(START)
ICS(OPP)
CS
RCS
CCS
Figure 6. Over−Power Protection Diagram
www.onsemi.com
11
RSNS
NCP12700
Another aspect of the Over−Power Protection feature is
that the current sourced out of the CS pin is modulated as a
function of the COMP voltage to ensure that the current is
only available when necessary. This is detailed in Figure 7
below with typical values for VOPP(0%) = 0.8 V and
VOPP(100%) = 2 V. The typical values of 0.8 V and 2 V equate
to ~ 27% and 67% of the full load capability of the device,
hence the OPP current should begin being applied at 27%
load and should ramp up to 100% OPP current at 67% load.
V COMP
2V
0.8 V
ICS(OPP)
100%
0
Figure 7. OPP Current Profile vs. COMP Voltage
www.onsemi.com
12
time
NCP12700
PWM Operation
RT Pin & Oscillator
where FOSC is the switching frequency. The curve in
Figure 8 below shows the Oscillator frequency vs. RT
resistor for values between ~10 kW to 100 kW. The
NCP12700 is designed to operate between 100 kHz and
1 MHz but will have tighter tolerance at lower switching
frequencies.
The oscillator in the NCP12700 uses an external resistor
from the RT pin to ground to set the switching frequency of
the converter. The frequency set by the RT resistor follows
F OSC +
1
100
RT
(eq. 5)
10 −12
1,000
900
800
Oscillator Frequency (kHz)
700
600
500
400
300
200
100
0
0
10
20
30
40
50
60
70
80
90
100
RT Resistor Value (kΩ)
Figure 8. Oscillator Frequency vs. RT Resistor Value
Gate Driver (DRV)
PWM Reset Path
The NCP12700 is equipped with a gate driver for driving
the primary side MOSFET. The driver applies VCC up to the
clamped voltage, VDRV(clamp), of 12 V as a high signal and
0 V to the gate of the power MOSFET as a low signal. The
rate of charging and discharging of the gate of the MOSFET
is dependent upon the input capacitance of the MOSFET and
the impedance of the driver. The NCP12700 is equipped
with an IDRV(SRC) pull−up current, typically 1 A, and a pull
down current of IDRV(SNK), typically 2.8 A ensuring fast
turn on/off transitions of the power MOSFET and
minimizing the switching losses.
The NCP12700 is intended for isolated DC−DC
converters where the control loop compensation circuitry is
located on the secondary side of the power converter. The
converter output voltage is compared against a reference
voltage and an error amplifier produces a compensated error
signal which is communicated to the NCP12700 through an
optocoupler. The compensated error signal interfaces with
the COMP pin where it is divided down by a 5R/R voltage
divider and sent to the PWM S/R to modulate the switching
duty cycle. A detailed functional diagram of the PWM path
is shown in Figure 9. The PWM comparator compares the
attenuated error signal from the COMP pin to the current
ramp signal sensed at the CS pin to determine when the drive
pulse should be terminated. This comparator serves as the
primary modulation path for the converter duty cycle.
www.onsemi.com
13
NCP12700
VDD
VSCP(LIM)
t LEB(SCP)
SCP
COMPARATOR
NSCP
Counter
ICS(OPP)
SCP
CS
SLOPE
COMPENSATION
DRV
t CS(OVLD)
OVLD
LEB
CURRENT LIMIT
COMPARATOR
VCS(LIM)
VDD
t LEB(CS)
ISS
SCP DMAX
Soft−Start
COMPARATOR
SS
Switching Disabled
DRV
VDD
1/6
CLK
PWM
LOGIC
S
Q
R
SLOPE
COMPENSATION
PWM
COMPARATOR
5k
5R
COMP
R
SKIP
COMPARATOR
V COMP(skip)
VCOMP(skip_hys)
Figure 9. NCP12700 PWM Path
DRV
V PWM
VSLP
0
D40%
D80%
Figure 10. Slope Compensation Timing Diagram
Slope Compensation
sub−harmonic oscillation the NCP12700 implements an
internal slope compensation circuit which is applied to the
attenuated COMP signal at the input of the PWM
comparator.
The slope compensation timing diagram is shown in
Figure 10. The compensating ramp begins reducing the
In fixed frequency peak current mode control, converters
operating at duty cycles greater than 50% of the switching
period are susceptible to sub−harmonic oscillation,
characterized by successive switching cycles with
alternating wide and narrow pulse−widths. To avoid
www.onsemi.com
14
NCP12700
attenuated COMP voltage when the switching duty cycle is
nominally 40% and reduces the voltage by a peak, VSLP(PK),
at the 80% duty cycle limit. The slope compensating ramp
is synchronized to the duty cycle of the oscillator, effectively
adjusting itself based on the switching frequency, providing
the converter with a compensating dv/dt ramp appropriate
for the particular switching frequency. An image of the slope
compensating ramp is also applied at the input of the Current
Limit comparator to prevent sub−harmonic oscillations
from occurring during overload conditions. The chart below
summarizes the dv/dt of the compensating ramp at some
common operating frequencies.
FSW (kHz)
TSW (ms)
D = 40% (ms)
D = 80% (ms)
VSLP (mV)
Ramp (mV/ms)
100
10.00
4.00
8.00
98 / 40
25 / 10
200
5.00
2.00
4.00
98 / 40
49 / 20
250
4.00
1.60
3.20
98 / 40
61 / 25
330
3.03
1.21
2.42
98 / 40
81 / 33
400
2.50
1.00
2.00
98 / 40
98 / 40
500
2.00
0.80
1.60
98 / 40
123 / 50
Cycle−by−Cycle Current Limit and Overload Protection
pulses and take the device into a Fault mode when the timer
has expired. The 30 ms timer allows the converter to sustain
a short term overload but still protects the converter from
thermal overstress in the event of a continuously applied
overload condition. The overload timer is also an integrating
timer, it will continue ramping up while the Current Limit
Comparator is terminating drive pulses but will begin
ramping down, not reset completely, if the drive pulse is
terminated by another signal such as the PWM comparator.
This operation is depicted in Figure 11.
The NCP12700 implements cycle−by−cycle current
limiting with a dedicated Current Limit Comparator. The
input to the comparator is the primary FET current ramp
sensed at the CS pin. If the sensed voltage exceeds the
current limit threshold, VCS(LIM), then the drive pulse is
terminated. There are device options for VCS(LIM) of
250 mV and 495 mV. The Current Limit Comparator is very
fast with a total propagation delay, tCS(DLY), of 75 ns
maximum ensuring that drive pulses are quickly terminated
minimizing current overshoot in the converter.
The Current Limit comparator also triggers an overload
timer, tCS(OVLD), nominally 30 ms, and will disable drive
VCOMP
V DRV
Overload
Timer
time
t1
t2
t3
t4 t5
t6
Figure 11. Integrating Overload Timer
Short Circuit (SCP) Comparator
secondary side rectifier or a shorted winding in the
transformer it may be possible to sense an abnormally high
current pulse at the CS pin and disable drive pulses to
The NCP12700 also includes a fast Short Circuit
Comparator with a threshold, VSCP(LIM), of 312.5 mV and
625 mV. In certain extreme fault conditions such as a shorted
www.onsemi.com
15
NCP12700
dedicated Skip Comparator which monitors the voltage at
the COMP pin and blanks drive pulses if the COMP voltage
falls below the VCOMP(skip) threshold of 300 mV. To
re−enable new drive pulses, the COMP voltage must exceed
a skip hysteresis, VCOMP(skip_hys) of 25 mV above the
300 mV threshold. The skip hysteresis is designed to
prevent the converter from oscillating in and out of skip
mode due to noise on the COMP pin.
prevent the converter from further damage. If the voltage at
the CS pin rapidly exceeds VSCP(LIM) and the SCP
comparator trips, then the drive pulse will be terminated and
a counter will be incremented. If the SCP comparator trips
on 4 consecutive drive pulses then drive pulses will be
disabled and the controller is put into the Fault mode.
Leading Edge Blanking (LEB)
Converters operating in peak current mode control require
a high quality current ramp signal to ensure stable and clean
PWM operation. In the NCP12700 the current ramp signal
is sensed at the CS pin and is routed through a LEB circuit
which blanks the current sense information for a brief period
after the DRV voltage is delivered to the primary MOSFET.
The LEB prevents noise generated during the switching
transition from terminating drive pulses prematurely. The
blanking is performed by an internal pulldown switch and
series disconnect switch. The internal pulldown switch has
an on resistance, RPD(LEB), specified as 55 ohms maximum.
The pulldown switch is turned on whenever the DRV is low
and remains on for a period of time equal to tLEB(SCP), 60 ns
typical, after the DRV is set high.
After tLEB(SCP) has expired the current ramp signal is
delivered to the SCP comparator allowing it to sense an
abnormal overcurrent situation. A longer series LEB,
tLEB(CS), of 100 ns continues to hold open the signal path to
the CS and PWM comparators. This switch closes when
tLEB(CS) has expired, allowing the CS information to be
delivered to the other two comparators. In addition to the
LEB network, the user of the controller will usually place a
small RC filter in between the current sense components and
the CS pin to provide noise suppression. The resistor value
in the RC filter is typically in the range of 500 – 1 kW, sized
appropriately for the Over−Power protection feature, and
the capacitor value is typically chosen to provide a time
constant for the RC filter of about 50 – 100 ns.
Maximum Duty Cycle
The NCP12700 also includes a maximum duty cycle
clamp which terminates a drive pulse which has been high
for DMAX of the switching period. The default value of
DMAX will be 80%.
Soft Start
The soft start feature in the NCP12700 is implemented
with a dedicated comparator that compares the current ramp
signal from the CS pin against an attenuated soft start ramp
generated at the SS pin. Prior to enabling switching, an
internal pull−down transistor with an on resistance,
RSS(DIS), of 100 W is activated to discharge the external soft
start capacitor and hold the SS pin to GND. Once switching
is enabled the pull−down transistor is released and a current
source, ISS, of 15 mA charges the soft start capacitor forming
the soft start ramp voltage. The soft start ramp voltage is then
divided down by a factor of KSS and fed into the soft start
comparator which resets drive pulses when the CS voltage
exceeds the soft start voltage. The soft start comparator will
continue to reset drive pulses until another comparator
enters the reset path which typically occurs when the
secondary side control loop responds allowing the PWM
comparator to take control.
The NCP12700 monitors the external soft start voltage
and sets a flag when the voltage exceeds 3 V, declaring that
the soft start period has ended. At 3 V, the drive pulse reset
control will have been handed off to either the PWM
comparator or the Current limit comparator. The SS_END
flag is used internally by the controller for fault
management, gating detection of certain faults that may be
erroneously triggered during power up of the converter. This
is shown in the FLT pin block diagram of Figure 12.
Skip Comparator
For a power converter operating at light loads it is
sometimes desired to skip drive pulses in order to maintain
output voltage regulation or improve the light load
efficiency of the system. The NCP12700 features a
To V CC
VDD
IFLT
SS_END
V FLT(OTP)
t OTP(DLY)
V FLT(OTP_HYS)
V FLT(OVP)
t OVP(DLY)
Figure 12. FLT Pin Block Diagram
www.onsemi.com
16
To Fault Logic
NCP12700
Fault (FLT) Pin
Summary of Fault Handling
The FLT pin is intended to provide the system with a NTC
interface for thermal protection and a pull−up fault which
can be coupled to the auxiliary winding to provide output
over−voltage protection. The FLT pin can also be used as a
general purpose fault where it interfaces with a simple
pull−down BJT, open collector comparator, or optocoupler
for monitoring of secondary side faults. The internal
circuitry includes a precision pull−up current source, IFLT, of
85 mA and a window comparator to signal a fault whenever
the pin voltage goes below the OTP fault threshold,
VFLT(OTP), of 0.5 V or above the OVP fault threshold,
VFLT(OVP), of 3 V. Both of the fault comparators also include
a delay filter to prevent noise or glitches from setting the
fault. The over−temperature fault filter, tOTP(DLY), is
nominally 20 ms and the over−voltage fault filter, tOVP(DLY),
is typically 5 ms. An external filter capacitor is also
advisable.
Both faults have an option to permanently latch off the
controller or restart after a 1 s auto−recovery period. The
OVP fault is intended to monitor an auxiliary winding and
when triggered, the controller will disable switching which
will inhibit the aux winding from generating voltage and
allow the controller to restart after the auto−recovery timer
has expired. If the OVP fault comparator is continuously
held above 3 V, the NCP12700 will remain in the fault mode
and not restart.
The OTP fault detection is gated by the SS_END flag to
prevent the comparator from triggering while the external
filter capacitor charges up. Once the SS_END flag is set the
OTP fault can be acknowledged so there is a practical limit
on the size of the filter capacitor. Equation 6 and Equation 7
should assist the user with properly setting the external
capacitance of the fault pin.
The NCP12700 has 6 fault detectors which will place the
device into the fault mode. In the fault mode switching is
inhibited and the controller bias is maintained by the HV
startup regulator. The controller also reduces current
consumption to ICC(FLT), 500 mA maximum, so that the
regulator is not thermally overstressed. The NCP12700
remains in the fault mode until the fault signal has been
cleared and/or the auto−recovery timer has expired. The
fault signal can be cleared when the fault detector senses that
the fault has been removed or by a controller reset which
occurs if VCC drops below VCC(OFF) or the UVLO pin is
pulled below the VRST(th) level. Below is a brief summary
of the different fault detectors and their basic operation.
• Thermal Shutdown (TSD): Thermal shutdown is
declared when the internal junction temperature of the
device exceeds the TSHDN temperature of 165°C. The
thermal shutdown fault is auto−recoverable when the
device junction temperature reduces to TSHDN –
TSHDN(hys) where TSHDN(hys) is typically 25°C.
• Fault OTP: An OTP fault is declared when fault pin
voltage decreases below the VFLT(OTP) threshold of
0.5 V and the OTP filter, tOTP(DLY), expires. The OTP
filter delay is typically 20 ms. The OTP fault is blanked
at startup until the SS_END flag has been set to allow
the external capacitance of the pin to charge up. For the
device to recover from the Fault OTP, the
auto−recovery timer must expire and the voltage at the
fault pin must recover to VFLT(REC) value of 0.9 V.
• Fault OVP: The OVP fault is declared when fault pin
the voltage exceeds the VFLT(OVP) threshold of 3 V and
the OVP filter, tOVP(DLY), expiring. The OVP filter
delay is typically 5 ms. The OVP fault is cleared when
the auto−recovery timer expires. There is no hysteresis
on the OVP fault but if the pin voltage is permanently
held above 3 V, DRV will pulses will be permanently
inhibited.
• Overload (OVLD): The OVLD fault is set when the
overload timer, tOVLD, expires. The overload timer is
an integrating timer which counts up as long as the
Current Limit comparator is terminating DRV pulses.
The typical value for tOVLD is 30 ms. The controller
will recover from the OVLD fault when the
auto−recovery timer expires.
• SCP Fault: The SCP fault occurs when the NSCP
counter has reaches 4 consecutive DRV pulses
terminated by the SCP comparator. The controller will
recover from the SCP fault when the auto−recovery
timer expires.
• VCC OVP: The VCC OVP is set when VCC voltage
exceeds the VCC(OVP) threshold of 28 V and the VCC
OVP filter, tVCC_OVP(DLY), expires. The VCC OVP
filter is typically 3 ms. VCC OVP will permanently latch
the device off so that it remains in the Fault mode
indefinitely until the controller is reset.
t SS_END +
C FLT t
C SS
V SS_END
I SS
I FLT
t SS_END
V FLT(OTP)
(eq. 6)
(eq. 7)
When the OTP fault is triggered the NCP12700 will again
disable drive pulses and transition into a fault mode. The
OTP fault is auto−recoverable based on the auto−recovery
timer and a hysteresis set by the VFLT(REC) threshold of
0.9 V. The auto−recovery timer must expire and the voltage
at the fault pin must exceed 0.9 V. This methodology
guarantees a minimum amount of time for the system to
recover from thermal overstress but will not allow the
converter to restart unless the hysteresis is met. Given the
IFLT and VFLT(OTP) specifications the critical NTC
resistance for declaring a fault is ~ 5.9 kW. The critical
resistance for recovering from the OTP fault becomes ~
10.6 kW. This fault recovery threshold provides for about
~20°C of hysteresis for many NTC resistors.
www.onsemi.com
17
NCP12700
Evaluation Board Designs
DN05109 describes the operation of a 18 – 160 V input
flyback converter delivering 12 V out at 15 W. This
demonstration board switches at 100 kHz and operates in
discontinuous conduction mode across the entire input
voltage range. The key performance specifications are
shown in Table 6.
Two evaluation boards have been developed to highlight
the features of the NCP12700. Detailed schematics,
operating waveforms, and bill of materials are available in
the design notes, DN05108 and DN05109. DN05108
describes the operation of a 9 – 36 V input flyback converter
delivering 12 V out at 15 W. This evaluation board switches
at 200 kHz and operates in both continuous and
discontinuous conduction modes. The key performance
specifications are shown in Table 5 below.
Table 6. WIDE RANGE FLYBACK EVALUATION
BOARD SPECIFICATIONS
Evaluation Board # 2
Table 5. LOW VOLTAGE FLYBACK EVALUATION
BOARD SPECIFICATIONS
Evaluation Board # 1
Vin
9 − 36 V Operating
Vo
12 V − 1.25 A
Po
15 W
< 30 ms
Full Load Efficiency
> 87 %
Transient Response
< 250 ms
Over Power Protection
120% − 150%
Over Voltage Protection
16 VDC Max
No Load Output Ripple
200 mVpp Max
No Load Power Dissipation
120 mW Max
Input Current in SHDN
< 1 mA
18 − 160 V Operating
Vo
12 V − 1.25 A
Po
15 W
Specifications
Specifications
Startup time
Vin
Startup time
< 20 ms
Full Load Efficiency
> 85 %
Transient Response
< 250 ms
Over Power Protection
115% − 155%
Over Voltage Protection
16 VDC Max
No Load Output Ripple
150 mVpp Max
No Load Power Dissipation
500 mW Max
Input Current in SHDN
< 1 mA
www.onsemi.com
18
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WQFN10 4x3, 0.8P
CASE 511DV
ISSUE C
1
SCALE 2:1
DATE 15 JUL 2019
GENERIC
MARKING DIAGRAM*
XXXXXX
XXXXXX
ALYWG
G
XXXXX = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON30094G
WQFN10 4x3, 0.8P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
MSOP10, 3x3
CASE 846AE
ISSUE A
SCALE 1:1
A
10
E
PIN ONE
INDICATOR
D
6
ÉÉ
ÉÉ
e
1
F
B
q
E1
L
L2
L1
DETAIL A
5
10X
TOP VIEW
b
0.08
C B
M
S
A
S
DETAIL A
A
A1
0.10 C
C
c
END VIEW
SEATING
PLANE
SIDE VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
10X
10X 0.29
0.85
C
DATE 20 JUN 2017
NOTES:
1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 MM IN
EXCESS OF MAXIMUM MATERIAL CONDITION.
4. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH,
PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15
MM PER SIDE. DIMENSION E DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 MM PER SIDE.
DIMENSIONS D AND E ARE DETERMINED AT DATUM F.
5. DATUMS A AND B TO BE DETERMINED AT DATUM F.
6. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE
SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE
BODY.
MILLIMETERS
MIN
NOM
MAX
−−−
−−−
1.10
0.00
0.05
0.15
0.75
0.85
0.95
0.17
−−−
0.27
0.13
−−−
0.23
2.90
3.00
3.10
4.75
4.90
5.05
2.90
3.00
3.10
0.50 BSC
0.40
0.70
0.80
0.95 REF
0.25 BSC
0°
−−−
8°
DIM
A
A1
A2
b
c
D
E
E1
e
L
L1
L2
q
GENERIC
MARKING DIAGRAM*
10
5.35
XXXX
AYWG
G
1
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
XXXX
A
Y
W
G
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present and may be in
either location. Some products may not
follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34098E
MSOP10, 3X3
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
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