NCP1288
Controller, Fixed Frequency,
Current Mode, for Flyback
Converters
The NCP1288 is a new generation of the NCP12xx fixed−frequency
current−mode controllers featuring a high−voltage startup current,
pin−to−pin compatible with the previous generation.
Due to its proprietary Soft−Skip™ mode combined with frequency
foldback, the controller exhibits excellent efficiency in light load
condition while still achieving very low standby power consumption.
This Soft−Skip feature also dramatically reduces the risk of acoustic
noise, which enables the use of inexpensive transformers and
capacitors in the clamping network.
Internal frequency jittering, ramp compensation, and a versatile
latch input make this controller an excellent candidate for converters
where ruggedness and components cost are the key constraints.
In addition, the controller includes a new high voltage circuitry that
combines a startup current source and a brown−out / line OVP detector
able to sense the input voltage either from the rectified ac line or the dc
filtered bulk voltage.
Finally, due to a careful design, the precision of critical parameters
is well controlled over the entire temperature range (−40°C to+125°
C), enabling easier design and increased safety (e.g. $5% for
the peak current limit, $7% for the oscillator).
Features
•
•
•
•
•
•
• Timer−Based Overload Protections with Auto−
•
•
•
•
•
•
•
•
Recovery (Option B) or Latched (Option A) Operation
High−Voltage Current Source with Built−in Brown−out
and Line Overvoltage Protections
Fixed−Frequency Current−Mode Operation with
Built−in Ramp Compensation
Frequency Jittering for a Reduced EMI Signature
Adjustable Overpower Compensation
Latch−off Input for Severe Fault Conditions, with
Direct Connection of an NTC for Overtemperature
Protection (OTP)
Protection Against Winding Short−Circuit
Frequency Foldback transitioning into Soft−Skip for
Improved Performance in Standby
65 kHz Oscillator (100 kHz and 133 kHz Versions
Available Upon Request)
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MARKING
DIAGRAM
8
SOIC−7
CASE 751U
1
88Xff
ALYWX
G
88Xff = Specific Device Code
X = A or B
ff = 65, 00, or 33
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 38 of this data sheet.
VCC Operation up to 28 V
Increased Precision on Critical Parameters
±1.0 A Peak Drive Capability
4.0 ms Soft−Start
Internal Thermal Shutdown with Hysteresis
These Devices are Pb−Free, Halogen Free/BFR Free
and are RoHS Compliant*
Typical Applications
•
•
•
•
ac−dc Adapters for Notebooks, LCD, and Printers
Offline Battery Chargers
Consumer Electronic Power Supplies
Auxiliary/Housekeeping Power Supplies
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2011
July, 2011 − Rev. 3
1
Publication Order Number:
NCP1288/D
NCP1288
1
Latch
2
FB
3
4
HV
8
CS
VCC
6
GND
DRV
5
Figure 1. Pinout
TYPICAL APPLICATION EXAMPLE
VOUT
VIN
(dc)
LATCH
HV
FB
NCP1288
CS
VCC
GND
DRV
Figure 2. Typical Application
PIN FUNCTION DESCRIPTION
Pin N5
Pin Name
Function
Pin Description
1
LATCH
Latch−off Input
Pull the pin up or down to latch−off the controller. An internal current source allows
the direct connection of an NTC for over temperature detection
2
FB
Feedback
3
CS
Current Sense
4
GND
–
5
DRV
Drive Output
6
VCC
VCC Input
8
HV
High−Voltage Pin
A pull−down optocoupler controls the output regulation.
Senses the primary current for current−mode operation, and provides a mean for
overpower compensation adjustment.
IC ground
Drives an external MOSFET
This supply pin accepts up to 28 Vdc
Connects to the bulk capacitor or the rectified AC line to perform the functions of
start−up current source and brown−out / line overvoltage detections
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2
NCP1288
SIMPLIFIED INTERNAL BLOCK SCHEMATIC
Brown−out
+
INTC
INTC
BO
HV stop
blanking
+
−
OVM
tLatch(OVP)
VOVP
−
+
VDD
HV dc
HV sample
HV
Latch
+
1 kW
−
+
VOTP
S
Q
R
Vclamp
TSD
TSD
blanking
tLatch(OTP)
Dual HV
start−up
current source
Latch
TSD HV current
Reset
VCC
UVLO
management
VDD
Start
Reset
UVLO
VDD
IC Start
Soft−start
end
Brown−out
Reset
FB
Soft−skip ramp
−
+
+
VDD
Reset
VCC
tSSKIP
Vskip
RFB(up)
Skip
KFB
FB
slope
comp.
HV sample
PWM
+
−
V to I
IOPC = 0.5m x
(VHV−125)
Jitter
Skip
FB
Sawtooth
Soft−start
+
−
Stop Foldback
Oscillator
tSSTART
−
+
+
Soft−start Start
ramp
Reset
End
VFB(OPC)
DCMAX
IC Start
IC Stop
S
Soft−start end
blanking
tLEB
CS
+
blanking
Q
R
+
−
VILIM
tBCS
Clamp
DMAX
DRV
ILIMIT
IC stop
GND
UVLO
ILIMIT
DMAX
S
Q
R
+
Latch
Autorecovery
protection
mode only
VCS(stop)
Fault Flag
timer
timer
tfault
PWM
HV stop
Protection
Mode
release
+
−
tautorec
Fault
Brown−out
Reset
Figure 3. Simplified Internal Block Schematic
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3
TSD
NCP1288
MAXIMUM RATINGS
Symbol
Value
Unit
Supply Pin (pin 6) (Note 1)
Voltage range
Current range
Rating
VCCMAX
ICCMAX
–0.3 to 28
$30
V
mA
High Voltage Pin (pin 8) (Note 1)
Voltage range
Current range
VHVMAX
IHVMAX
–0.3 to 500
$20
V
mA
Driver Pin (pin 5) (Note 1)
Voltage range
Current range
VDRVMAX
IDRVMAX
–0.3 to 20
$1500
V
mA
VMAX
IMAX
–0.3 to 10
$10
V
mA
All other pins (Note 1)
Voltage range
Current range
Thermal Resistance
Junction−to−Air, low conductivity PCB (Note 2)
Junction−to−Air, medium conductivity PCB (Note 3)
Junction−to−Air, high conductivity PCB (Note 4)
RqJA
Temperature Range
Operating Junction Temperature
Storage Temperature Range
TJMAX
TSTRGMAX
ESD Capability
Human Body Model (HBM) per JEDEC standard JESD22, Method A114E (All pins except HV)
Machine Model (MM) per JEDEC standard JESD22, Method A115A
162
147
125
−40 to +150
−60 to +150
2000
200
°C/W
°C
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78
2. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 100 mm2 of 1 oz copper traces and heat spreading area. As specified
for a JEDEC 51−1 conductivity test PCB. Test conditions were under natural convection or zero air flow.
3. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 100 mm2 of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51−2 conductivity test PCB. Test conditions were under natural convection or zero air flow.
4. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 650 mm2 of 1 oz copper traces and heat spreading area. As specified
for a JEDEC 51−3 conductivity test PCB. Test conditions were under natural convection or zero air flow.
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4
NCP1288
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VHV = 120 V,
VCC = 11 V unless otherwise noted)
Symbol
Min
Typ
Max
Unit
VHV(min)
−
−
60
V
Istart1
Istart2
0.2
4
0.5
8
0.8
12
mA
Istart(off)
−
25
50
mA
Turn−on threshold level, VCC going up
HV current source stop threshold
VCC(on)
15.0
16.0
17.0
V
UVLO and HV current source restart threshold
VCC(min)
9.5
10.5
11.5
V
Hysteresis between VCC(on) and VCC(min)
VCC(HYS)
5.0
−
−
V
Characteristics
Test Condition
HIGH VOLTAGE CURRENT SOURCE
Minimum voltage for current source operation
Current flowing out of VCC pin @ VHV = 60 V
VCC = 0 V
VCC = VCC(on) − 0.5 V
Off−state leakage current
VHV = 500 V
SUPPLY
Blanking duration on VCC(min) and VCC(off) detection
tUVLO(blank)
7
10
13
ms
VCC decreasing level at which the internal logic resets
VCC(reset)
4.0
5.2
6.5
V
VCC level for ISTART1 to ISTART2 transition
VCC(inhibit)
0.4
0.65
0.9
V
DRV open, VFB = 3 V
ICC1
2.0
2.5
3.0
mA
Cdrv = 1 nF, VFB = 3 V
ICC2
2.3
3.3
4.3
Off mode (skip or before
startup)
Fault mode (fault or latch)
ICC3
0.9
1.2
1.5
ICC4
0.4
0.7
1.0
VHV(start)
VHV(stop)
104
97
112
105
120
113
V
tHV
43
61
79
ms
VHV(OV1)
VHV(OV2)
400
395
430
425
460
455
V
tOV(blank)
−
250
−
ms
Oscillator frequency
fOSC
60
65
70
kHz
Maximum duty ratio
DMAX
75
80
85
%
Internal current consumption (Note 5)
Guaranteed by design
BROWN−OUT AND LINE OVERVOLTAGE
Brown−out threshold voltage
VHV going up
VHV going down
Timer duration for line cycle drop−out
Overvoltage threshold
VHV going up
VHV going down
Blanking duration on line overvoltage detection
OSCILLATOR
Frequency jittering amplitude, in percentage of FOSC
Guaranteed by design
Ajitter
$4
$6
$8
%
Frequency jittering modulation frequency
Guaranteed by design
Fjitter
85
125
165
Hz
Rise time, 10% to 90% of VCC
VCC = VCC(min) + 0.2 V,
CDRV = 1 nF
trise
−
22
34
ns
Fall time, 90% to 10% of VCC
VCC = VCC(min) + 0.2 V,
CDRV = 1 nF
tfall
−
22
34
ns
Current Capability
VCC = VCC(min) + 0.2 V,
CDRV = 1 nF
DRV high, VDRV = 0 V
DRV low, VDRV = VCC
OUTPUT DRIVER
mA
IDRV(source)
IDRV(sink)
−
−
1000
1000
−
−
Clamping Voltage (Maximum Gate Voltage)
VCC = VCCmax – 0.2 V, DRV
high
VDRV(clamp)
11
13.5
16
V
High−State Voltage Drop
VCC = VCC(min) + 0.2 V,
RDRV = 33 kW, DRV high
VDRV(drop)
−
−
1
V
5. Internal supply current only, current in FB pin not included (current flowing through GND pin only).
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5
NCP1288
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VHV = 120 V,
VCC = 11 V unless otherwise noted)
Characteristics
Test Condition
Symbol
Min
Typ
Max
Unit
CURRENT SENSE
Input Bias Current
VCS = 0.7 V
Ibias
−
0.02
−
mA
Maximum Internal Current Setpoint
VFB > 3.5 V
VILIM
0.665
0.7
0.735
V
VCS(stop)
0.95
1.05
1.15
V
tdelay
−
80
110
ns
Leading Edge Blanking Duration for VILIM
tLEB
190
250
310
ns
Leading Edge Blanking Duration for VCS(stop)
tBCS
90
120
150
ns
Scomp(65kHz)
−
−32.5
−
mV / ms
tSSTART
2.8
4.0
5.2
ms
KOPC
−
0.5
−
mA / V
IOPC(125)
IOPC(162)
IOPC(325)
IOPC(max)
−
−
−
102
0
52
104
120
−
−
−
138
mA
FB voltage above which IOPC is applied
VFB(OPC)
1.50
1.65
1.80
V
FB voltage below which IOPC = 0
VFB(OPCE)
−
1.25
−
V
tWD
25
35
45
ms
Threshold for Immediate Fault Protection Activation
Propagation Delay from VILIM detection to DRV off
VCS = VILIM
Slope of the Compensation Ramp
Soft−Start Duration
1st
From
pulse to
VCS = VILIM
OVERPOWER COMPENSATION
VHV to IOPC Conversion Ratio
Current flowing out of CS pin
VHV = 125 V
VHV = 162 V
VHV = 325 V
VHV = VHV(OV2) − 5 V
Refresh period for dc operation
FEEDBACK
Internal Pull−up Resistor
TJ = 25°C
VFB to Internal Current Setpoint Division ratio
Internal Pull−up Voltage on the FB pin
RFB(up)
15
20
25
kW
KFB
4.7
5.0
5.3
−
VFB(ref)
4.3
5.0
5.7
V
tfault
64
78
98
ms
tautorec
1.0
1.4
1.8
s
OVERCURRENT PROTECTION
Fault Timer Duration
From CS reaching VILIMIT to
DRV stop
Autorecovery Mode Latch−off Time Duration
5. Internal supply current only, current in FB pin not included (current flowing through GND pin only).
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NCP1288
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VHV = 120 V,
VCC = 11 V unless otherwise noted)
Characteristics
Test Condition
Symbol
Min
Typ
Max
Unit
VFB(fold)
1.3
1.4
1.5
V
fOSC(min)
21
27
31
kHz
VFB(endfold)
−
1.0
−
V
Vskip(in)
Vskip(out)
0.63
0.72
0.7
0.80
0.77
0.88
V
FREQUENCY FOLDBACK
Feedback Voltage Threshold below which frequency
foldback starts
Minimum Switching Frequency
VFB = Vskip(in) + 0.2 V
Threshold below which the frequency foldback is
finished and the controller switches at fOSC(min)
SKIP CYCLE MODE
Feedback Voltage Thresholds for Skip Mode
VFB going down
VFB going up
Soft−Skip Duration
From 1st pulse to VCS =
VFB(fold) / KFB
tSSKIP
−
100
−
ms
High Threshold
VLatch going up
VOVP
2.37
2.5
2.63
V
Low Threshold
VLatch going down
VOTP
0.76
0.8
0.84
V
Current Source for Direct NTC Connection
During normal operation
During soft−start
VLatch = 0 V
INTC
INTC(SSTART)
78
156
91
182
104
208
Blanking Duration on High Latch Detection
tLatch(OVP)
40
55
70
ms
Blanking Duration on Low Latch Detection
tLatch(OTP)
−
400
−
ms
Vclamp0(Latch)
Vclamp1(Latch)
1.0
1.8
1.2
2.3
1.4
2.8
V
TTSD
135
150
165
°C
TTSD(HYS)
20
30
40
°C
LATCH−OFF INPUT
Clamping Voltage
ILatch = 0 mA
ILatch = 1 mA
mA
TEMPERATURE SHUTDOWN
Temperature Shutdown
TJ going up
Temperature Shutdown Hysteresis
TJ going down
5. Internal supply current only, current in FB pin not included (current flowing through GND pin only).
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7
NCP1288
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
−50
Vinhibit, INHIBIT THRESHOLD VOLTAGE
(V)
VCC, SUPPLY VOLTAGE THRESHOLDS
(V)
TYPICAL PERFORMANCE CHARACTERISTICS
VCC(on)
VCC(min)
VCC(reset)
−25
0
25
50
75
100
125
150
1.0
0.8
0.6
0.4
0.2
0.0
−50
−25
50
75
100
125
Figure 5. Inhibit Threshold Voltage vs.
Junction Temperature
150
10
VCC = 0 V
480
460
440
420
400
380
−25
0
25
50
75
100
125
VCC = VCC(on) − 0.5 V
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
−50
150
−25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 6. Inhibit Current vs. Junction
Temperature
Figure 7. Startup Current vs. Junction
Temperature
40
50
VCC = 10.5 V
IHV = 0.95 X Istart2
35
30
25
20
15
10
5
−25
0
25
50
75
100
125
I(start(off), STARTUP CIRCUIT LEAKAGE CURRENT (A)
VHV(min), MINIMUM STARTUP
VOLTAGE (V)
25
Figure 4. Supply Voltage Thresholds vs.
Junction Temperature
500
0
−50
0
TJ, JUNCTION TEMPERATURE (°C)
Istart2, STARTUP CURRENT(mA)
Istart1, INHIBIT CURRENT (mA)
1.2
TJ, JUNCTION TEMPERATURE (°C)
520
360
−50
1.4
150
VHV = 500 V
45
40
35
30
25
20
15
10
5
0
−50
TJ, JUNCTION TEMPERATURE (°C)
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
Figure 9. Startup Circuit Leakage Current vs.
Junction Temperature
Figure 8. Minimum Startup Voltage vs.
Junction Temperature
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8
150
NCP1288
TYPICAL PERFORMANCE CHARACTERISTICS
130
VHV, LINE OVERVOLTAGE CIRCUIT
THRESHOLDS (V)
450
115
VHV(start)
110
105
VHV(stop)
100
95
90
85
ICC, OPERATING SUPPLY CURRENT (mA)
80
−50
−25
0
25
50
75
100
125
150
445
440
VHV(OV1)
435
430
425
VHV(OV2)
420
415
410
−50
−25
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
Figure 10. Brown−Out Circuit Thresholds vs.
Junction Temperature
Figure 11. Line Overvoltage Circuit Thresholds
vs. Junction Temperature
4.00
3.75
3.50
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
−50
ICC2
ICC1
ICC3
ICC4
−25
0
25
50
75
100
125
150
85
80
75
70
65
60
55
50
45
−50
−25
81.5
81.0
80.5
80.0
79.5
79.0
78.5
−25
0
25
50
75
100
25
50
75
100
125
150
Figure 13. Oscillator Frequency vs. Junction
Temperature
trise, tfall, DRIVER TRANSITIONS TIME
(ns)
82.0
78.0
−50
0
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 12. ICC Supply Currents vs. Junction
Temperature
DMAX, MAXIMUM DUTY RATIO (%)
0
TJ, JUNCTION TEMPERATURE (°C)
fOSC, OSCILLATOR FREQUENCY (kHz)
VHV, BROWN−OUT CIRCUIT
THRESHOLDS (V)
125
120
125
150
40
35
30
25
20
trise
15
10
tfall
5
0
−50
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 15. Driver Transitions Time vs. Junction
Temperature
Figure 14. Maximum Duty Ratio vs. Junction
Temperature
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9
150
NCP1288
1.10
17
1.05
VCS, CURRENT SENSE VOLTAGE
THRESHOLDS (V)
18
16
15
14
13
12
11
10
9
8
−50
−25
0
25
50
75
100
125
150
1.00
VCS(stop)
0.95
0.90
0.85
0.80
0.75
0.70
0.65
VILIM
0.60
−50
−25
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
Figure 16. Driver Clamp Voltage vs. Junction
Temperature
Figure 17. Current Sense Voltage Thresholds
vs. Junction Temperature
320
310
300
290
280
270
260
250
240
230
220
210
200
−50
−25
0
25
50
75
100
125
150
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
−50
−25
TJ, JUNCTION TEMPERATURE (°C)
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
−25
0
25
50
75
100
25
50
75
100
125
150
Figure 19. Current Sense Propagation Delay
vs. Junction Temperature
IOPC(max), OVERPOWER COMPENSATION CURRENT (mA)
6.0
1.5
−50
0
TJ, JUNCTION TEMPERATURE (°C)
Figure 18. Leading Edge Blanking Time vs.
Junction Temperature
tSTART, SOFT−START PERIOD (ms)
0
TJ, JUNCTION TEMPERATURE (°C)
tdelay, CURRENT SENSE PROPAGATION
DELAY (ns)
tLEB, LEADING EDGE BLANKING TIME (ns)
VDRV(clamp), DRIVER CLAMP VOLTAGE
(V)
TYPICAL PERFORMANCE CHARACTERISTICS
125
150
135
130
125
120
115
110
105
100
95
90
−50
TJ, JUNCTION TEMPERATURE (°C)
−25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
Figure 21. Overpower Compensation Current vs.
Junction Temperature
Figure 20. Soft−Start Period vs. Junction
Temperature
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10
NCP1288
1.80
1.75
1.70
1.65
VFB(OPC)
1.60
1.55
1.50
1.45
1.40 VFB(OPCE)
1.35
1.30
1.25
1.20
1.15
1.10
−50 −25
0
41
tWD, OPC WATCHDOG TIME (ms)
VFB(OPC), OPC VOLTAGE THRESHOLDS (V)
TYPICAL PERFORMANCE CHARACTERISTICS
25
50
75
100
125
150
40
39
38
37
36
35
34
33
32
31
30
−50
RFB(up), FB PULL−UP RESISTOR (kW)
4.98
4.96
4.94
4.92
4.90
4.88
4.86
−25
0
25
50
75
100
75
100
125
150
125
150
25
24
23
22
21
20
19
18
17
16
15
−50
−25
TJ, JUNCTION TEMPERATURE (°C)
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
Figure 25. FB Pull−up Resistor vs. Junction
Temperature
96
tfault, OVERLOAD TIMER DURATION
(ms)
VFB(ref), FB PULL−UP VOLTAGE (V)
50
27
26
Figure 24. FB to CS Ratio vs. Junction
Temperature
5.6
5.5
5.4
5.3
5.2
5.1
5.0
4.9
4.8
4.7
4.6
4.5
4.4
4.3
−50
25
Figure 23. OPC Watchdog Time Thresholds vs.
Junction Temperature
5.00
4.84
−50
0
TJ, JUNCTION TEMPERATURE (°C)
Figure 22. OPC FB Thresholds vs. Junction
Temperature
KFB, FB TO CS RATIO
−25
TJ, JUNCTION TEMPERATURE (°C)
−25
0
25
50
75
100
125
150
94
92
90
88
86
84
82
80
78
76
−50
TJ, JUNCTION TEMPERATURE (°C)
−25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
Figure 27. Overload Timer Duration vs. Junction
Temperature
Figure 26. FB Pull−up Voltage vs. Junction
Temperature
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NCP1288
−25
0
25
50
75
100
125
150
tHV, BO DETECTION TIMER DURATION
(ms)
1.54
1.52
1.50
1.48
1.46
1.44
1.42
1.40
1.38
1.36
1.34
1.32
1.30
1.28
1.26
−50
71
70
69
68
67
66
65
64
63
62
61
60
59
58
−50
−25
TJ, JUNCTION TEMPERATURE (°C)
1.55
1.50
1.45
VFB(fold)
1.40
1.35
1.30
1.25
1.20
1.15 VFB(endfold)
1.10
1.05
1.00
0.95
0.90
0.85
0.80
−50 −25
0
25
50
75
100
125
150
30.0
29.5
29.0
28.5
28.0
27.5
27.0
26.5
26.0
25.5
25.0
24.5
24.0
23.5
23.0
−50
Vskip(out)
0.80
0.78
0.76
0.74
Vskip(in)
0.68
0.66
−25
0
25
50
75
100
125
150
tSSKIP, SOFT−SKIP TIMER DURATION (ms)
VSkip, SKIP THRESHOLDS (V)
0.84
0.64
−50
75
100
125
150
−25
0
25
50
75
100
125
150
Figure 31. Minimum Switching Frequency vs.
Junction Temperature
0.86
0.70
50
TJ, JUNCTION TEMPERATURE (°C)
Figure 30. FB Thresholds for Frequency
Foldback vs. Junction Temperature
0.72
25
Figure 29. Brown−Out Detection Timer
Duration vs. Junction Temperature
TJ, JUNCTION TEMPERATURE (°C)
0.82
0
TJ, JUNCTION TEMPERATURE (°C)
Figure 28. Autorecovery Timer Duration vs.
Junction Temperature
fOSC(min), MINIMUM SWITCHING FREQUENCY (ms)
VFB(fold), FB FOLDBACK THRESHOLDS (V)
tautorec, AUTORECOVERY TIMER DURATION (s)
TYPICAL PERFORMANCE CHARACTERISTICS
135
130
125
120
115
110
105
100
95
90
85
80
75
70
−50
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 32. Skip Thresholds vs. Junction
Temperature
Figure 33. Soft−Skip Timer Duration vs.
Junction Temperature
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150
NCP1288
TYPICAL PERFORMANCE CHARACTERISTICS
0.84
VOTP, LATCH OTP THRESHOLD (V)
VOVP, LATCH OVP THRESHOLD (V)
2.54
2.53
2.52
2.51
2.50
2.49
2.48
2.47
2.46
2.45
2.44
2.43
2.42
−50
−25
0
25
50
75
100
125
0.83
0.82
0.81
0.80
0.79
0.78
0.77
0.76
0.75
0.74
−50
150
−25
TJ, JUNCTION TEMPERATURE (°C)
Figure 34. Latch OVP Threshold vs. Junction
Temperature
50
75
100
125
150
66
tlatch(OVP), BLANKING TIME ON OVP
DETECTION (ms)
96
INTC, LATCH OTP CURRENT
SOURCE (mA)
25
Figure 35. Latch OTP Threshold vs. Junction
Temperature
98
94
92
90
88
86
84
82
80
78
76
−50
−25
0
25
50
75
100
125
150
64
62
60
58
56
54
52
50
48
46
−50
−25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 37. Blanking Time on OVP Detection vs.
Junction Temperature
Figure 36. Latch OTP Current Source vs.
Junction Temperature
360
tOV(blank), BLANKING TIME ON LINE
OV DETECTION (ms)
500
tlatch(OTP), BLANKING TIME ON OTP
DETECTION (ms)
0
TJ, JUNCTION TEMPERATURE (°C)
480
460
440
420
400
380
360
340
320
300
−50
−25
0
25
50
75
100
125
150
340
320
300
280
260
240
220
200
180
−50
TJ, JUNCTION TEMPERATURE (°C)
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
Figure 38. Blanking Time on OTP Detection vs.
Junction Temperature
Figure 39. Blanking Time on Line OV
Detection vs. Junction Temperature
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150
NCP1288
TYPICAL PERFORMANCE CHARACTERISTICS
Vclamp(Latch), LATCH PIN CLAMP
VOLTAGE (V)
2.80
2.60
Vclamp1(Latch)
2.40
2.20
2.00
1.80
1.60
1.40
1.20
Vclamp0(Latch)
1.00
0.80
−50
−25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
Figure 40. Latch Pin Clamp Voltage vs. Junction
Temperature
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NCP1288
APPLICATION INFORMATION
Introduction
The NCP1288 includes all of the necessary features to build
a safe and efficient power supply based on a
fixed−frequency flyback converter. It is particularly well
suited for applications where low part count is a key
parameter, without sacrificing safety.
• Current−Mode Operation with slope compensation:
The primary peak current is permanently controlled by
the FB voltage, ensuring maximum safety: the DRV
turn−off event is dictated by the peak current setpoint.
It also ensures that the frequency response of the
system remains first order if in DCM, which eases the
design of the feedback loop. The controller can also be
used in CCM with a wide input voltage range due to its
fixed ramp compensation that prevents the appearance
of sub−harmonic oscillations in most of the
applications.
• Fixed−Frequency Oscillator with Jittering: The
NCP1288 is available in various frequency options to
fit any application. The internal oscillator features a
low−frequency jittering that helps to pass the EMI
requirements by spreading out the energy content of
frequency peaks in quasi−peak and average mode.
• Latched / Autorecovery Timer−Based Overcurrent
Protection: The overcurrent protection depends only
on the FB signal, enabling it to work with any
transformer, even with very poor coupling or high
leakage inductance. The protection is fully latched on
the A version (the power supply has to be unplugged
then restarted in order to resume operation, even if the
overload condition disappears), and autorecovery on the
B version. The timer’s duration is fixed. The controller
also enters the same protection mode if the voltage on
the CS pin reaches 1.5 times the maximum internal
setpoint, which enables to detect winding short circuits.
• High Voltage Startup Current Source with
Brown−Out and Line Overvoltage Detections: Due
to On Semiconductor’s Very High Voltage technology,
the NCP1288 can directly be connected to the high
input voltage. The startup current source ensures a
clean startup while ensuring low losses when it is off.
The high voltage pin also features a high−voltage
sensing circuitry, which is able to turn the controller off
if the input voltage is too low (brown−out condition) or
too high (line overvoltage). This protection works
either with a DC input voltage or a rectified AC input
voltage, and is independent of the high voltage ripple. It
uses a peak detector synchronized with line frequency,
or with the internal watchdog timer if the HV pin is tied
to a dc voltage.
• Adjustable Overpower Compensation: The high
voltage sensed on the HV pin is converted into a
current to add to the current sense voltage an offset
•
•
•
•
•
•
proportional to the input voltage. By choosing the value
of the resistor in series with the CS pin, the amount of
compensation can be adjusted to the application.
Frequency foldback then Soft−Skip mode for light
load operation: In order to ensure a high efficiency in
all load conditions, the NCP1288 implements a
frequency foldback (the switching frequency is lowered
to reduce switching losses) for light load condition; and
a Soft−Skip (disabled in case of fast load transients) for
extremely low load condition.
Extended VCC range: The NCP1288 accepts a supply
voltage as high as 28 V, making the design of the power
supply easier.
Clamped Driver Stage: Despite the high supply
voltage, the voltage on DRV pin is safely clamped
below 16 V; allowing the use of any standard MOSFET,
and reducing the current consumption of the controller.
Dual Latch−off Input: The NCP1288 can be latched
off by an increasing voltage applied to its Latch pin
(typically an overvoltage) or by a decreasing one, and
an NTC can be directly connected to the latch pin
thanks to the precise internal current source.
Soft−Start: At every startup the peak current is
gradually increased during 4 ms to minimize the stress
on power components.
Temperature Shutdown: The NCP1288 is internally
protected against self−heating: if the die temperature is
too high, the controller shuts all circuitries down
(including the HV startup current source), allowing the
silicon to cool down before attempting to restart. This
ensures a safe behavior in case of failure.
Typical Operation
• Startup: The HV startup current source ensures the
•
charging of the VCC capacitor up to the startup
threshold VCC(on), until the input voltage is high
enough (above VHV(start)) to enable the switching. The
controller then delivers pulses, starting with a soft−start
period tSSTART during which the peak current linearly
increases before the current−mode control takes over.
During the soft−start period, the low level latch is
ignored, and the latch current is double, to ensure a fast
pre−charge of the decoupling capacitor on the Latch
pin.
Normal operation: As long as the feedback voltage is
within the regulation range, the NCP1288 runs at a
fixed frequency (with jittering) in current−mode
control, where the peak current (sensed on the CS pin)
is set by the voltage on the FB pin. A fixed ramp
compensation is applied internally to prevent
sub−harmonic oscillations from occurring. The VCC
must be supplied by an external source (such as an
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NCP1288
•
•
•
auxiliary winding), as the startup current source cannot
permanently supply the controller without overheating.
Light load operation: When the FB voltage decreases
below VFB(fold), typically corresponding to a load of
16% of the maximum load (for a DCM design), the
switching frequency starts to decrease down to
fOSC(min). By lowering the switching losses, this feature
helps to improve the efficiency in light load conditions.
The frequency jittering is disabled in light load
operation.
No load operation: When the FB voltage decreases
below Vskip(in), typically corresponding to a load of 1%
of the maximum load, the controller enters Skip mode.
By completely stopping the switching while the
feedback voltage is below Vskip(out), the losses are
further reduced, allowing to minimize the power
dissipation under extremely low load conditions. In
order to avoid audible noise, the peak current is
gradually increased during the tSSKIP duration while
exiting the skip mode (Soft−Skip function). In case of
abrupt load increase during Soft−Skip mode, the
soft−skip portion is bypassed and the peak current
needed for regulation is directly applied.
Overload: The NCP1288 features a timer−based
overload detection, solely dependent on the feedback
•
•
information: as soon as the internal peak current
setpoint hits the VILIM clamp, the internal overload
timer starts to count. When the timer times out, the
controller stops and enter the protection mode,
autorecovery for the B version (the controller initiates a
new start−up after tautorec elapses), or latched for the A
version (the latch is released if a brown−out event
occurs or VCC is reset).
Brown−out: The NCP1288 features on its HV pin a
true AC line monitoring circuitry, which includes a
minimum startup threshold, brown−out protection, and
overvoltage protection. All of these circuits are
autorecovery and operate independently of any ripple
on the input voltage. They can even work with an
unfiltered, rectified AC input. All thresholds are fixed,
but they are designed to fit most of the standard ac−dc
conversion applications.
Latch−off: When the Latch input is pulled up (typically
by an overvoltage condition), or pulled low (typically
by an overtemperature condition, using the provided
current source with an NTC), the controller latches off.
The latch is released when a brown−out condition
occurs, or when VCC decreases below VCC(reset).
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NCP1288
DETAILED DESCRIPTION
High−Voltage Current Source (Dynamic Self−Supply)
with Built−in Brown−out Detection
The NCP1288 HV pin can be connected either to the
rectified bulk voltage, or to the ac line through a rectifier.
Startup
HV
Istart
TSD
Control
IC Start
VCC
+
+
−
VCC(on)
+
R
Q
S
blanking
−
+
UVLO
tUVLO(blank)
VCC(min)
+
−
+
Reset
VCC(reset)
Figure 41. HV Startup Current Source Functional Schematic
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NCP1288
At startup, the current source turns on when the voltage on
the HV pin is higher than VHV(min), and turns off when VCC
reaches VCC(on). It turns on again when VCC reaches
VCC(min). This sequence repeats until the input voltage is
high enough to ensure a proper startup, i.e. when VHV
reaches VHV(start). The switching actually starts the next
time VCC reaches VCC(on), as shown in Figure 5. The current
source is then turned off, saving additional power when the
VCC is supplied externally.
Once the controller has started, if VCC reaches VCC(min)
the switching stops and the protection mode is activated: the
controller must be supplied by an external voltage source.
VHV
VHV(start)
Waits
next
VCC(on)
before
starting
VHV(min)
time
VCC
VCC(on)
VCC(min)
HV
current
source =
Istart1
HV
current
source =
Istart2
VCC(inhibit)
time
DRV
Figure 42. Startup Timing Diagram
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time
NCP1288
Brown−out and Line Overvoltage
To reduce the power dissipation in case the VCC pin is
shorted to GND (in case of VCC capacitor failure, or external
pulldown on VCC to disable the controller), the startup
current is lowered when VCC is below VCC(inhibit).
There are only two conditions for which the current source
doesn’t turn on when VCC reaches VCC(min): the voltage on
HV pin is too low (below VHV(min)), or a thermal shutdown
condition (TSD) has been detected. In all other conditions,
the HV current source always turns on and off to maintain
VCC between VCC(min) and VCC(on).
When the input voltage goes below VHV(stop), a
brown−out condition is detected, and the controller stops.
The HV current source alternatively turns on and off to
maintain VCC between VCC(on) and VCC(min) until the input
voltage is back above VHV(start).
The same situation occurs when an overvoltage is
detected on the ac line, i.e. when the input voltage goes
above VHV(OV): the controller stops, and resumes normal
operation when the overvoltage condition has gone.
HV stop
Brown-out
or AC OVP
detected
Waits next
VCC(on) before
starting
VCC
time
VCC(on)
VCC(min)
time
DRV
Figure 43. Brown−out or Line Overvoltage Timing Diagram
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time
NCP1288
When VHV crosses the VHV(start) threshold, the controller
can start immediately. When it crosses VHV(stop), it triggers
a timer of duration tHV: this ensures that the controller
doesn’t stop in case of line cycle drop−out.
VHV
Brown-out
VHV(start)
VHV(stop)
DRV
time
Starts at next
VCC(ON)
t HV
Figure 44. AC Input Brown−out Timing Diagram
The same scheme is used for the Line OVP, except that this
time the controller must not stop instantaneously when the
input voltage goes above VHV(OV1). In order to be
time
insensitive to spikes and voltage surges a blanking circuit is
inserted after the output of the comparator, with a duration
of tOV(blank).
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NCP1288
Blanked
voltage
surge
VHV
VHV(OV1)
VHV(OV2)
time
OVP
detected
HV
timer
starts
HV
timer
restarts
One Shot
Restarts at
VCC(on)
t HV
time
DRV
Figure 45. AC Input Line Overvoltage Timing Diagram
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time
NCP1288
Oscillator with Maximum Duty Ratio and Frequency
Jittering
In order to improve the EMI signature, the switching
frequency jitters around its nominal value, with a
triangle−wave shape.
The NCP1288 includes an oscillator that sets the
switching frequency with an accuracy of $7%. The
maximum duty ratio of the DRV pin is 80% (typical), with
an accuracy of $7%.
fOSC
fOSC + Ajitter
Nominal fOSC
fOSC - Ajitter
1 / Fjitter
Time
Figure 46. Frequency Jittering
This driver has a typical current capability of ±1.0 A.
Clamped Driver
The supply voltage for the NCP1288 can be as high as
28 V, but most of the MOSFETs that will be connected to the
DRV pin cannot tolerate a gate−to−source voltage greater
than 20 V on their gate. The driver pin is therefore clamped
safely below 16 V.
VCC
Clamp
DRV signal
DRV
Figure 47. Clamped Driver
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NCP1288
CURRENT−MODE CONTROL WITH OVERPOWER COMPENSATION AND SOFT−START
Current Sensing
one input of the PWM comparator through the LEB block.
On the other input the FB voltage divided by KFB sets the
threshold: when VCS reaches this threshold, the output
driver is turned off.
The maximum value for the peak current, VILIM, is set by
a dedicated comparator.
NCP1288 is a current−mode controller, which means that
the FB voltage sets the peak current flowing in the
inductance and the MOSFET. This is done through a PWM
comparator: the current is sensed across a resistor and the
resulting voltage is applied to the CS pin. VCS is applied to
VDD
KFB
+
−
RFB(up)
PWM
Jitter
Soft−start
+
−
Oscillator
Soft−start ramp
Start
tSSTART
Reset
FB
DCMAX
IC Start
IC Stop
S
Q
R
blanking
tLEB
CS
+
−
+
VILIM
IC stop
UVLO
blanking
tBCS
+
−
+
Protection
Mode
VCS(stop)
Fault
Figure 48. Current Sense Block Schematic
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HV stop
Latch
TSD
DRV Stage
NCP1288
because of the LEB and propagation delay) until it reaches
VILIM (after a duration of tSSTART), or until the FB loop
imposes a setpoint lower than the one imposed by the
soft−start (the 2 comparators outputs are OR’ed).
Each time the controller is starting, i.e. the controller was
off and starts, or restarts, when VCC reaches VCC(on), a
soft−start is applied: the current sense setpoint is linearly
increased from 0 (the minimum level can be higher than 0
VFB
VFB(fault)
Time
Soft-start ramp
VFB takes
over soft-start
VILIM
tSSTART
Time
CS Setpoint
VILIMI
Figure 49. Soft−Start
Under some conditions, like a winding short−circuit for
instance, not all the energy stored during the on time is
transferred to the output during the off time, even if the on
time duration is at its minimum (imposed by the propagation
delay of the detector added to the LEB duration). As a result,
the current sense voltage keeps on increasing above VILIM,
because the controller is blind during the LEB blanking
Time
time. Dangerously high current can grow in the system if
nothing is done to stop the controller. In order to protect
against this, an additional comparator is included, that
senses when VCS reaches VCS(stop) ( = 1.5 x VILIM ). As soon
as this comparator toggles, the controller immediately enters
the protection mode (latched or autorecovery according to
the chosen option).
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NCP1288
Compensation for Overpower Detection
Unfortunately, due to the inherent propagation delay of
the logic, the actual peak current is higher at high input
voltage than at low input voltage, as shown in Figure 50.
This leads to a significant difference in the maximum output
power delivered by the power supply.
The power delivered by a flyback power supply is
proportional to the square of the peak current:
P OUT +
1
@ h @ L P @ F SW @ I P
2
2
(eq. 1)
(in discontinuous conduction mode).
IP
IP to be
compensated
ILIMIT
High
Line
Low
Line
time
tdelay
tdelay
Figure 50. Line Compensation for True Overpower Protection
To compensate this and have an accurate overpower
protection, an offset proportional to the input voltage is
added to the CS signal by turning on an internal current
source (IOPC): by adding an external resistor (ROPC) in
series between the sense resistor and the CS pin, a voltage
offset is created across it by the current. The compensation
can be adjusted by changing the value of the ROPC resistor.
Since in light load conditions this offset is in the same
order of magnitude as the current sense signal, it must be
removed. Therefore the compensation current is only added
when the FB voltage is higher than VFB(OPC), as shown in
Figure 52.
VDD
V to I
HV Sensing
HV
IOPC = 0.5m x
(VHV − 125)
+
FB
−
+
VFB(OPC)
blanking
To CS
block
CS
t LEB
ROPC
Rsense
Figure 51. Schematic Overpower Compensation Circuit
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NCP1288
IOPC
VHV
VFB
VFB(fold)
VFB(OPC)
Figure 52. Overpower Compensation Current Relation to Feedback Voltage and Input Voltage
capacitor, its voltage never crosses the brown-out threshold,
and the watchdog timer tWD is used to generate the sampling
and reset events (Figure 54). Note that depending on the
relative speeds at which the HV and VCC voltages appear at
start-up, the correct overpower compensation current may
be delayed by one cycle.
A peak detector continuously senses the ac input, and its
output is periodically sampled and reset, in order to follow
closely the input voltage variations. The sample and reset
events are controlled by the brown-out comparator when the
HV pin is connected to the AC line input (as shown in Figure
53). In the case the HV pin is connected to the DC-link
V HV
BO threshold
time
Peak
detector
Reset
Reset
Reset
t wd
Reset
Reset
time
I OPC
Sample
Sample
Sample
Sample
Reset
time
Figure 53. Overpower Compensation Current with the HV pin connected to an ac voltage
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NCP1288
V HV
BO threshold
time
t wd
t wd
t wd
Peak
detector
Reset
time
I OPC
Sample
Sample
Reset
Sample
t wd
time
Figure 54. Overpower Compensation Current with the HV pin connected to a dc voltage
Feedback with Slope Compensation
to VILIM is 3.5 V. There is a pullup resistor of 20 kW
(typical) from FB pin to the internal reference VFB(ref).
The ratio from the FB voltage to the current sense setpoint
is typically 5. This means that the FB voltage corresponding
VDD
20 kW
FB
K FB
slope
comp.
+
Oscillator
PWM
−
blanking
CS
t LEB
Figure 55. FB Circuitry
In order to allow the NCP1288 to operate in CCM with a
duty cycle above 50%, a fixed slope compensation is
internally applied to the current−mode control. The slope
appearing on the internal voltage setpoint for the PWM
comparator is −32.5 mV/ms typical for the 65 kHz version
(and respectively −50 mV/ms and −67 mV/ms for the
100 kHz and 133 kHz versions).
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NCP1288
OVERCURRENT PROTECTION WITH FAULT TIMER
Classical Overcurrent Protection
controller is either latched off (latched protection,
Version A), or it enters an autorecovery mode (Version B).
The timer is reset when the CS setpoint goes back below
VILIM before the timer elapses. The fault timer is also started
if the driver signal is reset by the max duty ratio.
When an overcurrent occurs on the output of the power
supply, the feedback loop asks for more power than the
controller can deliver, and the CS setpoint reaches VILIM.
When this event occurs, an internal tfault timer is started:
once the timer times out, DRV pulses are stopped and the
FB
+
−
/5
Fault Flag
PWM
R
Q
S
timer
tfault
Protection
Mode
Autorecovery
protection
mode only
blanking
CS
Reset DRV
release
timer
tLEB
+
+
−
Brown−out
Reset
VILIM
DC MAX
DRV
Figure 56. Timer−Based Overcurrent Protection
In autorecovery mode, the controller tries to restart after
tautorec. If the fault has gone, the supply resumes operation;
if not, the system starts a new burst cycle (see Figure 57).
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t autorec
NCP1288
Fault
disappears
Output Load Overcurrent
applied
Max Load
Fault Flag
time
Fault
timer
starts
VCC
time
VCC(on)
VCC(min)
Restart
At VCC(on)
(new burst
cycle if Fault
DRV
time
still present)
Controller
stops
Fault timer
time
tfault
tfault
tautorec
Figure 57. Autorecovery Timer−Based Protection Mode
http://onsemi.com
29
time
NCP1288
In the latched version (Figure 58), the controller can
restart only if a brown−out or a VCC reset occurs. In a real
application this can only happen if the power supply is
unplugged from the mains line.
Output Load
No restart
when fault
disappears
Overcurrent
applied
Max Load
Fault Flag
time
Fault
timer
starts
VCC
time
VCC(on)
VCC(min)
DRV
time
Controller
latches off
Fault timer
time
tfault
tfault
Figure 58. Latched Timer−Based Overcurrent Protection
http://onsemi.com
30
time
NCP1288
If VCC reaches VCC(min) before the timer has elapsed, the
controller enters protection mode anyway (in both
protection mode versions). Here is the example with the
latched version:
Output Load
No restart
when fault
disappears
Overcurrent
applied
Max Load
time
Fault Flag
Fault
timer
starts
time
VCC
VCC(on)
VCC(min)
time
DRV
Controller
latches off
time
Fault Timer
tfault
time
tfault
Figure 59. Overcurrent Protection Mode Triggered by VCC
http://onsemi.com
31
NCP1288
LOW LOAD OPERATION
Frequency Foldback
whatever the nominal switching frequency option is. The
current−mode control is still active while the oscillator
frequency decreases, but the frequency jittering is off.
Note that the frequency foldback is disabled if the
controller runs at its maximum duty cycle.
In order to improve the efficiency in light load conditions,
the frequency of the internal oscillator is linearly reduced
from its nominal value down to fOSC(min). This frequency
foldback starts when the voltage on FB pin goes below
VFB(fold), and is complete before VFB reaches Vskip(in),
fOSC
Nominal fOSC
Skip
fOSC(min)
FB
Vskip(in)
VFB(fold)
Figure 60. Frequency Foldback when the FB Voltage Decreases
Skip Cycle Mode with Soft−Skip
+
−
+
Soft−skip ramp
Reset
tSSKIP
Sawtooth
Oscillator
DCMAX
Vskip
FB
CS
S
Q
R
K FB
blanking
tLEB
DRV stage
−
+
+
−
Figure 61. Skip Cycle with Soft−Skip Schematic
the controller restarts with a short Soft−Skip duration
(tSSKIP). The soft−skip imposes the peak current from nearly
0, in a voltage−mode manner: it doesn’t have the same
behavior as the startup soft−start which is current−mode
driven.
When VFB reaches Vskip(in) while decreasing, the skip
mode is activated: the driver stops, and the internal
consumption of the controller is decreased. While VFB is
below Vskip(out), the controller remains in this state. When
VFB crosses Vskip(out), the DRV pin starts to pulse again, and
http://onsemi.com
32
NCP1288
VFB
VFB(fold)
Vskip(out)
Vskip(in)
Exits
skip
Time
Enters
skip
Enters
skip
DRV
Exits
soft-skip
Exits
skip
Time
CS setpoint
Soft-skip
Softskip
Figure 62. Skip Cycle with Soft−Skip Timing Diagram
If during the Soft−Skip duration the FB voltage goes
above VFB(fold), the Soft−Skip ends instantaneously, and the
peak current follows the setpoint imposed by the
Time
current−mode control. This transient load detection feature
avoids large output voltage drops if a load transient occurs
while the controller is in soft−skip mode.
http://onsemi.com
33
NCP1288
Latch−off Input
VDD
+
−
+
INTC
blanking
tLatch(OVP)
VOVP
INTC
Latch
+
1 kW
−
+
blanking
tLatch(OTP)
S
Q
R
Latch
VOTP
Vclamp
Brown−out
Reset
Soft−start
end
Figure 63. Latch Detection Schematic
Reset occurs when a brown−out condition is detected or
the VCC is cycled down to a VCC(reset), which in a real
application can only happen if the power supply is
unplugged from the AC line.
Upon startup, the internal references take some time
before reaching their nominal values; and one of the
comparators could toggle inadvertantly. Therefore the
internal logic ignores the latch signal before the controller is
ready to start. Once VCC reaches VCC(on), the latch pin High
latch state is enabled and the DRV switching starts only if it
is allowed; whereas the Low latch (typically sensing an
overtemperature) is taken into account only after the
soft−start is finished. In addition, the NTC current is doubled
during the soft−start period, to speed up the charging of the
Latch pin capacitor.
The Latch pin is dedicated to the latch−off function. It
includes two thresholds that define a working window,
between a high latch and a low latch. Within these 2
thresholds; the controller is allowed to run; but as soon as
either the low or the high threshold is crossed, the controller
is latched off. The lower threshold is intended to be used
with an NTC thermistor, with the internal current source
INTC providing the necessary bias current.
An active clamp prevents the voltage from reaching the
high threshold if it is only pulled up by the ILatch current. To
reach the high threshold, the pullup current has to be higher
than the pulldown capability of the clamp (typically 1.5 mA
at VOVP).
To avoid any false triggering, noise spikes shorter than
tLatch(OVP) or tLatch(OTP) respectively are blanked, and only
longer events can actually latch the controller.
http://onsemi.com
34
NCP1288
VCC
VCC(on)
VCC(min)
Start-up
initiated by
VCC(on)
Internal Latch Signal
Noise spike
ignored
(tLatch blanking)
Latch signal
high during
pre-start phase
time
time
DRV
Latch-off
Switching
allowed (no
latch event)
Figure 64. Latch−off Function Timing Diagram
Temperature shutdown
time
instantaneously, the HV current source is turned off, and the
internal logic state is reset.
When the temperature falls below the low threshold, the
HV startup current source is enabled, and a regular startup
sequence takes place.
The die includes a temperature shutdown protection with
a turn−off threshold guaranteed between 140°C and 160°C,
and a typical hysteresis of 30°C. When the temperature rises
above the high threshold, the controller stops switching
http://onsemi.com
35
NCP1288
STATE DIAGRAMS
HV Startup Current Source
VCC > VCC(inhibit)
Istart1
No TSD
Istart2
VCC < VCC(inhibit)
TSD
TSD
Stop
TSD
VCC < VCC(min)
VCC > VCC(on)
TSD
Off
Figure 65. HV Startup Current Source State Diagram
http://onsemi.com
36
NCP1288
Controller Operation (Latched Version: A Option)
High Latch
VCC > VCC(on)
Soft−start
Soft-start ends
S Brown-out
S HV OVP
S TSD
S Brown-out
S HV OVP
S TSD
Stopped
S Brown-out
S HV OVP
S TSD
S Brown-out
S VCC reset
S Brown-out
S HV OVP
S TSD
Skip
S High Latch
S Low Latch
S Brown-out
S HV OVP
S TSD
Skip in
Latch
Skip out
Running
Soft−skip
S High Latch
S Low Latch
S Soft-skip ends
S V FB > V FB(fold)
S Fault
S High Latch
S Low Latch
With Fault =
S tfault expires
S VCS > VCS(stop)
S VCC < VCC(min)
Figure 66. Controller Operation State Diagram (Latched Protection)
http://onsemi.com
37
NCP1288
Controller Operation (Autorecovery Version: B Option)
High Latch
VCC > VCC(on)
Soft−start
Soft-start ends
S Brown-out
S HV OVP
S TSD
S t autorec counting
S Brown-out
S HV OVP
S TSD
Stopped
S Brown-out
S HV OVP
S TSD
S Brown-out
S VCC reset
S Fault
S Brown-out
S HV OVP
S TSD
Skip
S High Latch
S Low Latch
S Brown-out
S HV OVP
S TSD
Latch
Skip in
Skip out
Running
Soft−skip
S High Latch
S Low Latch
S Soft-skip ends
S V FB > VFB(fold)
S High Latch
S Low Latch
With Fault =
S tfault expires
S VCS > VCS(stop)
S VCC < VCC(min)
Figure 67. Controller Operation State Diagram (Autorecovery Protection)
Table 1. ORDERING INFORMATION
Part No.
NCP1288BD65R2G
Overload Protection
Switching Frequency
Package
Shipping†
Autorecovery
65 kHz
SOIC−7
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Soft−Skip is a trademark of Semiconductor Components Industries, LLC (SCILLC).
http://onsemi.com
38
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−7
CASE 751U−01
ISSUE E
DATE 20 OCT 2009
SCALE 1:1
−A−
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B ARE DATUMS AND T
IS A DATUM SURFACE.
4. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
5. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5
−B− S
0.25 (0.010)
B
M
M
1
4
G
C
R
X 45 _
J
−T−
SEATING
PLANE
H
0.25 (0.010)
K
M
D 7 PL
M
T B
S
A
DIM
A
B
C
D
G
H
J
K
M
N
S
INCHES
MIN MAX
0.189 0.197
0.150 0.157
0.053 0.069
0.013 0.020
0.050 BSC
0.004 0.010
0.007 0.010
0.016 0.050
0_
8_
0.010 0.020
0.228 0.244
S
GENERIC
MARKING DIAGRAM
SOLDERING FOOTPRINT*
8
1.52
0.060
7.0
0.275
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
1
XXX
A
L
Y
W
G
4.0
0.155
0.6
0.024
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
1.270
0.050
SCALE 6:1
XXXXX
ALYWX
G
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
98AON12199D
DESCRIPTION:
7−LEAD SOIC
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−7
CASE 751U−01
ISSUE E
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6.
7. NOT USED
8. EMITTER
DATE 20 OCT 2009
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. NOT USED
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. NOT USED
8. SOURCE, #1
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5.
6.
7. NOT USED
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6.
7. NOT USED
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. NOT USED
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR (DIE 1)
2. BASE (DIE 1)
3. BASE (DIE 2)
4. COLLECTOR (DIE 2)
5. COLLECTOR (DIE 2)
6. EMITTER (DIE 2)
7. NOT USED
8. COLLECTOR (DIE 1)
STYLE 9:
PIN 1. EMITTER (COMMON)
2. COLLECTOR (DIE 1)
3. COLLECTOR (DIE 2)
4. EMITTER (COMMON)
5. EMITTER (COMMON)
6. BASE (DIE 2)
7. NOT USED
8. EMITTER (COMMON)
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. NOT USED
8. GROUND
STYLE 11:
PIN 1. SOURCE (DIE 1)
2. GATE (DIE 1)
3. SOURCE (DIE 2)
4. GATE (DIE 2)
5. DRAIN (DIE 2)
6. DRAIN (DIE 2)
7. NOT USED
8. DRAIN (DIE 1)
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. NOT USED
8. COMMON CATHODE
DOCUMENT NUMBER:
98AON12199D
DESCRIPTION:
7−LEAD SOIC
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
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