NCP1337ADAPGEVB

DATA SHEET www.onsemi.com PWM Current-Mode Controller for Free Running Quasi-Resonant Operation SOIC−7 D SUFFIX CASE 751U NCP1337 The NCP1337 combines a true current mode modulator and a demagnetization detector which ensures full Borderline/Critical Conduction Mode in any load/line conditions together with minimum drain voltage switching (Quasi−Resonant operation). The transformer core reset detection is done internally, without using any external signal, due to the Soxyless concept. The frequency is internally limited to 130 kHz, preventing the controller to operate above the 150 kHz CISPR−22 EMI starting limit. By monitoring the feedback pin activity, the controller enters skip mode as soon as the power demand falls below a predetermined level. As each restart is softened by an internal Soft−Skipt, and as the frequency cannot go below 25 kHz, no audible noise can be heard. The NCP1337 also features an efficient protective circuitry which, in presence of an overcurrent condition, disables the output pulses and enters a safe burst mode, trying to restart. Once the default has gone, the device auto−recovers. Also included is a bulk voltage monitoring function (known as brown−out protection), an adjustable overpower compensation, and a VCC OVP. The controller immediately restarts after any of these conditions, unless the fault timer has timed out. Finally, an internal 4.0 ms soft−start eliminates the traditional startup stress. MARKING DIAGRAM 8 P1337 ALYWG G 1 A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) PIN CONNECTIONS BO FB CS GND • • • • • • • • • • • • 8 2 3 6 4 5 HV VCC DRV (Top View) Features • • • • 1 Free−Running Borderline/Critical Mode Quasi−Resonant Operation Current−Mode Soft−Skip Mode with Minimum Switching Frequency for Standby Auto−Recovery Short−Circuit Protection Independent of Auxiliary Voltage Overvoltage Protection Brown−Out Protection Two Externally Triggerable Fault Comparators (one for a disable function, and the other for a permanent latch) Internal 4.0 ms Soft−Start 500 mA Peak Current Drive Sink Capability 130 kHz Max Frequency Internal Leading Edge Blanking Internal Temperature Shutdown Direct Optocoupler Connection Dynamic Self−Supply with Levels of 12 V (On) and 10 V (Off) SPICE Models Available for TRANsient and AC Analysis These are Pb−Free Devices ORDERING INFORMATION Device Package Shipping† NCP1337DR2G SOIC−7 (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Typical Applications • • • • AC−DC Adapters for Notebooks, etc. Offline Battery Chargers Consumer Electronics (DVD Players, Set−Top Boxes, TVs, etc.) Auxiliary Power Supplies (USB, Appliances, TVs, etc.) © Semiconductor Components Industries, LLC, 2014 February, 2022 − Rev. 7 1 Publication Order Number: NCP1337/D NCP1337 PIN FUNCTION DESCRIPTION Pin No. Symbol 1 BO Function Description • Brown−out and external triggering • • 2 FB • Sets the peak current setpoint • 3 CS • Current sense input and overpower compensation adjustment • By connecting this pin to the input voltage through a resistor divider, the controller ensures operation at a safe mains level, thanks to a 500 mV brown−out comparator. If an external event brings this pin above 3.0 V, the controller’s output is disabled. If an external event brings this pin above 5.0 V, the controller is permanently latched−off. By connecting an optocoupler or an auxiliary winding to this pin, the peak current setpoint is adjusted accordingly to the output power demand. When the requested peak current setpoint is below the internal standby level, the device enters Soft−Skip mode. This pin senses the primary current and routes it to the internal comparator via an L.E.B. Inserting a resistor in series with the pin allows to control the overpower compensation level. 4 GND IC ground 5 DRV Output driver • To be connected to an external MOSFET. 6 VCC IC supply • • Connected to a tank capacitor (and possibly an auxiliary winding). • Connected to the high−voltage rail, this pin injects a constant current into the VCC bulk capacitor and ensures a clean lossless startup sequence. 8 HV High−voltage pin When VCC reaches 18.6 V, an internal OVP stops the output pulses. VOUT BO +C bulk 1 + VCC NCP1337 8 + 2 3 6 4 5 VCC Rcomp Figure 1. Typical Application Schematic www.onsemi.com 2 NCP1337 + + 5V Q S PERM. LATCH R + DISABLE + - 3V Vdd VBO 500 mV + + TSD S Startup Soxyless + 7.5 ms min period Ton Skip Ton SSkip Clk D R1 SStart OVP 100 mV Vdd 130 mV 5.5 ms blanking Toff TSD BOK + - 35 ms max Toff VCC < 4 V 10 mA BO 8 ms timeout Vdd Ton VCC Q Q Inhib Toff Soxyless demag detection R2 67 ms max Ton Soxyless FB 3V Setpoint 20 kHz Low−pass filter + 500 mV Vdd VBO CS GND FAULT if Zener activated 70 mA x VBO − 35 mA TSD CS comp. 300 ms Soft−Skipt SSkip 4 ms soft−start SStart 12 V 10 V 5V HV + + - PERM. LATCH FAULT Management* 9.5 mA or 600 mA VCC OVP + Ton 4k DRV + 18.6 V 350 ns LEB FAULT 2p (*If FAULT duration > 80 ms = > STOP Restart when 2nd time VCC = VCCon) Figure 2. Internal Circuit Architecture www.onsemi.com 3 NCP1337 MAXIMUM RATINGS Rating Symbol Value Unit VHV −0.3 to 500 V − 20 mA VCCmax −0.3 to 20 V Maximum Current in Pin 6 (VCC) − ±30 mA Maximum VCC Slew Rate (dV/dt) dVCC/dt 9.0 V/ms Maximum Voltage on all Pins except Pin 8 (HV), Pin 6 (VCC) and Pin 5 (DRV) − −0.3 to 10 V Maximum Current into all Pins except Pin 8 (HV), Pin 6 (VCC) and Pin 5 (DRV) − ±10 mA Maximum Current into Pin 6 (DRV) during ON Time and TBLANK − ±1.0 A Maximum Current into Pin 6 (DRV) after TBLANK during OFF Time − ±15 mA Thermal Resistance, Junction−to−Case RqJC 57 °C/W Thermal Resistance, Junction−to−Air, SOIC Version RqJA 178 °C/W Voltage on Pin 8 (HV) when Pin 6 (VCC) is Decoupled to Ground with 10 mF Maximum Current in Pin 8 (HV) Power Supply Voltage, Pin 6 (VCC) and Pin 5 (DRV) Thermal Resistance, Junction−to−Air, DIP Version RqJA 100 °C/W TJMAX 150 °C Operating Temperature Range − −40 to +125 °C Storage Temperature Range − −60 to +150 °C ESD Capability, HBM Model per JESD22, Method A114E (All Pins except HV) − 2.0 kV ESD Capability, Machine Model per JESD22, Method A115A − 200 V Maximum Junction Temperature Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. This device contains latchup protection and exceeds 100 mA per JEDEC standard JESD78. www.onsemi.com 4 NCP1337 ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = 0°C to +125°C, Max TJ = 150°C, VCC = 11 V, unless otherwise noted.) Characteristic Pin Symbol Min Typ Max Unit VCC Increasing Level at which the Controller Starts 6 VCCON 11 12 13 V VCC Decreasing Level at which the Controller Stops 6 VCCMIN 9.0 10 11 V Protection Mode is Activated if VCC reaches this Level whereas the HV Current Source is ON 6 VCCOFF − 9.0 − V VCC Decreasing Level at which the Latch−Off Phase Ends 6 VCCLATCH 3.6 5.0 6.0 V Margin between VCC Level at which Latch Fault is Released and VCCLATCH − VMARGIN 0.3 − − V VCC Increasing Level at which the Controller Enters Protection Mode 6 VCCOVP 17.6 18.6 19.6 V VCC Level below which HV Current Source is Reduced 6 VCCINHIB − 1.5 − V Internal IC Consumption, No Output Load on Pin 5, FSW = 60 kHz 6 ICC1 − 1.2 − mA Internal IC Consumption, 1.0 nF Output Load on Pin 5, FSW = 60 kHz 6 ICC2 − 2.0 − mA Internal IC Consumption, Latch−Off Phase, VCC = 8.0 V 6 ICC3 − 600 − mA Internal IC Consumption in Skip 6 ICCLOW − 600 − mA Minimum Guaranteed Startup Voltage on HV Pin 8 VHVmin − − 55 V High−Voltage Current Source when VCC > VCCINHIB (VCC = 10.5 V, VHV = 60 V) 8 IC1 5.5 9.5 15 mA High−Voltage Current Source when VCC < VCCINHIB (VCC = 0 V, VHV = 60 V) 8 IC2 0.3 0.6 1.1 mA Leakage Current Flowing when the HV Current Source is OFF (VCC = 17 V, VHV = 500 V) 8 IHVLeak − − 90 mA Output Voltage Rise−Time @ CL = 1.0 nF, 10−90% of Output Signal 5 TR − 50 − ns Output Voltage Fall−Time @ CL = 1.0 nF, 10−90% of Output Signal 5 TF − 20 − ns Source Resistance 5 ROH − 20 − W Sink Resistance 5 ROL − 8.0 − W Temperature Shutdown − TSD 130 − − °C Hysteresis on Temperature Shutdown − − − 30 − °C Maximum Internal Current Setpoint (@ IFB = IFB100%) 3 VCSLimit 475 500 525 mV Minimum Internal Current Setpoint (@ IFB = IFBrippleIN) 3 VCSrippleIN − 100 − mV Internal Current Setpoint for IFB = IFBrippleOUT 3 VCSrippleOUT − 130 − mV Propagation Delay from Current Detection to Gate OFF State 3 TDEL − 120 150 ns Leading Edge Blanking Duration 3 TLEB − 350 − Internal Current Offset Injected on the CS Pin during ON Time (Over Power Compensation) @ 1.0 V on Pin 1 and Vpin3 = 0.5 V @ 2.0 V on Pin 1 and Vpin3 = 0.5 V 3 IOPC Maximum ON Time 5 SUPPLY SECTION INTERNAL STARTUP CURRENT SOURCE DRIVE OUTPUT TEMPERATURE SHUTDOWN CURRENT COMPARATOR www.onsemi.com 5 MaxTON ns mA − − 35 105 − − 52 67 82 ms NCP1337 ELECTRICAL CHARACTERISTICS (continued) (For typical values TJ = 25°C, for min/max values TJ = 0°C to +125°C, Max TJ = 150°C, VCC = 11 V, unless otherwise noted.) Characteristic Pin Symbol Min Typ Max Unit FB Current under which FAULT is Detected 2 IFBopen − 40 − mA FB Current for which Internal Setpoint is 100% 2 IFB100% − 50 − mA FB Current above which DRV Pulses are Stopped 2 IFBrippleIN − 220 − mA FB Current under which DRV Pulses are Reauthorized after having reached IFBrippleIN 2 IFBrippleOUT − 205 − mA FB Current above which FB Pin Voltage is not Regulated anymore 2 IFBregMax − 500 − mA FB Pin Voltage when IFBopen < IFB < IFBregMax 2 VFB 2.8 3.0 3.2 V Duration before Entering Protection Mode after FAULT Detection − TFAULT − 80 − ms Internal Soft−Start Duration (Up to VCSLimit) − TSS − 4.0 − ms Internal Soft−Skip Duration (Up to VCSLimit) − TSSkip − 300 − ms Brown−Out Detection Level 1 VBO 460 500 540 mV Current Flowing out of Pin 1 when Brown−Out Comparator has Toggled 1 IBO − 10 − mA Vpin1 Threshold that Disables the Output 1 VDISABLE 2.8 3.0 3.3 V Vpin1 Threshold that Activates the Permanent Latch 1 VLATCH 4.75 5.0 5.25 V Current Threshold for Demagnetization Detection 5 ISOXYth − 210 − mA Max Voltage on DRV Pin During OFF Time after TBLANK (when Sinking 15 mA) 5 VDRVlowMAX − − 1.5 V Min Voltage on DRV Pin During OFF Time after TBLANK (when Sourcing 15 mA) 5 VDRVlowMIN −0.6 − − V Propagation Delay from Demag Detection to Gate ON State (IGATE Slope of 500 A/s) 5 TDMG − 180 220 ns Blanking Window after Gate OFF State before Detecting Demagnetization 5 TBLANK − 5.5 − ms Timeout on Demag Signal 5 TOUT − 8.0 − ms Maximum OFF Time 5 MaxTOFF − 35 42 ms Minimum Switching Period 5 MinPeriod 6.8 7.7 8.5 ms FEEDBACK SECTION BROWN−OUT AND LATCH SECTION DEMAGNETIZATION DETECTION BLOCK Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 6 NCP1337 APPLICATION INFORMATION Introduction The NCP1337 implements a standard current mode architecture where the switch−off time is dictated by the peak current setpoint, whereas the core−reset detection triggers the turn−on event. This component represents the ideal candidate where low part−count is the key parameter, particularly in low−cost AC−DC adapters, consumer electronics, auxiliary supplies, etc. Due to its high−performance, high−voltage technology, the NCP1337 incorporates all the necessary features needed to build a rugged and reliable Switch−Mode Power Supply (SMPS): • Quasi−Resonant Operation: Valley−switching operation is ensured whatever the operating conditions are, due to the internal soxyless circuitry. As a result, there are virtually no primary switch turn−on losses, and no secondary diode recovery losses, and EMI and video noise perturbations are reduced. The converter also stays a first−order system and accordingly eases the feedback loop design. • Dynamic Self−Supply (DSS): Due to its Very High Voltage Integrated Circuit (VHVIC) technology, onsemi’s NCP1337 allows for a direct pin connection to the high−voltage DC rail. A dynamic current source charges up a capacitor and thus provides a fully independent VCC level. As a result, low power applications will not require any auxiliary winding to supply the controller. In applications where this winding is anyway required (see “Power Dissipation” section in the application note), the DSS will simplify the VCC capacitor selection. • Overcurrent Protection (OCP): When the feedback current is below minimum value, a fault is detected. If this fault is present for more than 80 ms, NCP1337 enters an auto−recovery soft burst mode. All pulses are stopped and the VCC capacitor discharges down to 5.0 V. Then, by monitoring the VCC level, the startup current source is activated ON and OFF to create a burst mode. After the current source being activated twice, the controller tries to restart, with a 4.0 ms soft−start. If the fault has gone, • • • • • the SMPS resumes operation. If the fault is still there, the burst sequence starts again. The soft−start, together with a minimum frequency clamp, allow to reduce the noise generated in the transformer in short−circuit conditions. Overvoltage Protection (OVP): By continuously monitoring the VCC voltage level, the NCP1337 stops switching whenever an overvoltage condition is detected. Brown−Out Detection (BO): By monitoring the level on Pin 1 during normal operation, the controller protects the SMPS against low mains condition. When Pin 1 level falls below 500 mV, the controller stops switching until this level goes back and resumes operation, unless the fault timer has timed out. By adjusting the resistor divider connected between the high input voltage and this pin, start and stop levels are programmable. Over Power Compensation (OPC): An internal current source injects out of Pin 3 (CS pin) a current proportional to the voltage applied on Pin 1. As this voltage is an image of the input voltage, by inserting a resistor in series with Pin 3, it is possible to create an offset on the current sense signal that will compensate the effect of the input voltage variation. External Latch Trip Point: By externally forcing a level on Pin 1 (e.g., with a signal coming from a temperature sensor) greater than 3.0 V (but below 5.0 V), it is possible to disable the output of the controller. If the voltage is forced over 5.0 V, the controller is permanently latched−off: to resume normal operation, the VCC voltage should go below 4.0 V, which implies to unplug the SMPS from the mains. Standby Ability: Under low load conditions, NCP1337 enters a Soft−Skip mode: when the CS setpoint becomes lower than 20% of the maximum peak current, output pulses are stopped, then switching is starting again when FB loop forces a setpoint higher than 25%. As this occurs at low peak current, with Soft−Skip activated, and as the TOFF is clamped, noise−free operation is guaranteed, even with a cheap transformer. www.onsemi.com 7 NCP1337 TIMING DIAGRAMS VCC VCCON VCCMIN At startup, a 4.0 ms soft−start is activated. If the current Setpoint is above the fault level, FAULT flag is raised. CS Setpoint Fault VCSstby CS VCSLimit FAULT TIMER 80 ms SS When FAULT is activated, the 80 ms timer starts. When the timer ends, if FAULT is not activated anymore, the controller works normally. Figure 3. Startup Sequence www.onsemi.com 8 NCP1337 Restart on 2nd cycle VCC VCCON VCCMIN VCCLATCH CS Setpoint Overload is removed here Overload Fault When the current setpoint rises above fault level, FAULT flag is activated. CS VCSLimit Output pulses are stopped. FAULT TIMER 80 ms SS When FAULT flag is activated, timer is restarted. 80 ms Fault Timer Normal Startup Figure 4. Overload www.onsemi.com 9 NCP1337 VCC VCCon VCCmin CS Setpoint VCSrippleOUT VCSrippleIN CS (envelope) Min TON Soft−Skip on each re−start Figure 5. Soft−Skip Mode in Standby www.onsemi.com 10 NCP1337 Soxyless The “Valley point detection” is based on the observation of the Power MOSFET Drain voltage variations. When the transformer is fully demagnetized, the Drain voltage evolution from the plateau level down to the VIN asymptote is governed by the resonating energy transfer between the LP transformer inductor and the global capacitance present on the Drain. These voltage oscillations create current oscillation in the parasitic capacitor across the switching Lprim MOSFET (modelized by the Crss capacitance between Gate and Drain): a negative current (flowing out of DRV pin) takes place during the decreasing part of the Drain oscillation, and a positive current (entering into the DRV pin) during the increasing part. The Drain valley corresponds to the inversion of the current (i.e., the zero crossing): by detecting this point, we always ensure a true valley turn−on. TSWING Vswitch Crss Isoxy DRV t Figure 6. Soxyless Concept The current in the Power MOSFET gate is: Igate = Vringing/Zc (with Zc the capacitance impedance) so Igate = Vringing S (2 S p S Fres S Crss) The magnitude of this gate current depends on the MOSFET, the resonating frequency and the voltage swing present on the Drain at the end of the plateau voltage. The dead time TSWING is given by the equation: Tswing + 0.5ńFres + p * ǸLp * Cdrain Drain. This capacitance includes the snubber capacitor if any, the transformer windings stray capacitance plus the parasitic MOSFET capacitances COSS and CRSS). Internal Feedback Circuitry To simplify the implementation of a primary regulation, it is necessary to inject a current into the FB pin (instead of sourcing it out). But to have a precise primary regulation, the voltage present on FB pin must be regulated. Figure 8 gives the FB pin internal implementation: the circuitry combines the functions of a current to voltage converter and a voltage regulator. (eq. 1) (where LP is the primary transformer inductance and CDRAIN the total capacitance present on the MOSFET Vdd FB + 3V + Internal Setpoint - 20 kHz Low−pass Filter Figure 7. Internal Implementation of FB Pin www.onsemi.com 11 NCP1337 time out while the switching is stopped. As a result the controller will go into protection mode, and won’t restart instantaneously. • Permanent Latch (Comparator activated by an external signal): Activated when the voltage on BO pin is above 5.0 V When this comparator is activated, the DRV pulses are stopped, and the DSS is deactivated (only the start−up current source is turned on each time VCC reaches VCCLATCH, maintaining VCC between 5.0 V and 12 V): the controller stays in this position until the VCC voltage is decreased below 4.0 V, i.e., when the power supply is unplugged from the mains (in normal operation, as soon as a voltage is present on the HV pin, VCC is always kept above 5.0 V). The input information is the current injected in FB pin by the feedback loop. The range of current is from 40 mA for overload detection to 220 mA corresponding to VCSrippleIN. In transients, currents from 0 to more than 400 mA may also appear: the circuitry is able to sustain them. To regulate the FB pin voltage, the operational amplifier needs to have a high gain and a wide bandwidth. But the feedback information used internally needs to be filtered, because we don’t want the controller to be sensitive to the switching noise. For this purpose, a 20 kHz filter is added after the shunt regulator, and any reading of the feedback signal (for ripple mode, fault detection, or setpoint elaboration) is done after. Soft Burst Mode (Protection Mode) The NCP1337 features a fault timer to detect an overload completely independently of the VCC voltage. As soon as the feedback loop asks for the maximum power, a fault is detected, and an internal timer is started. When the fault disappears the timer is reset, but if the timer reaches 80 ms, the protection mode is activated. Once this protection is toggled, output pulses are stopped and DSS is deactivated (HV current source turn−on threshold changes from VCCMIN to VCCLATCH). VCC slowly decreases (the current consumption is ICC3), and the HV current source is switched ON when VCC reaches VCCLATCH. As a result VCC increases until VCCON, but the controller does not start as the output is still forced low. VCC decreases again down to VCCLATCH, and a new start−up cycle occurs. On the second attempt, the output is released, and NCP1337 effectively starts, with the soft−start activated. Figure 4 illustrates this behavior. Soft−Skip Mode The soft ripple mode is a skip mode with a large hysteresis on the skip comparator in order to ensure a noise−free and high−efficiency operation in low−load conditions (standby). When internal setpoint is reaching VCSrippleIN = 100 mV (corresponding to 20% of the maximum setpoint), the output pulses are stopped. Then FB loop asks for more power and internal setpoint is increasing: when it reaches VCSrippleOUT = 130 mV (corresponding to 25% of the maximum setpoint), the output starts switching again. Soft−Skip is activated in each activity following a stop period. See Figure 5 for detailed timing diagram. HV Current Source NCP1337 features a DSS, to allow operation without any auxiliary voltage. But to protect the die in case of short−circuit on VCC pin, the current delivered by the HV current source is lowered when VCC voltage is below 1.5 V. In the case the current consumed on the DRV pin is higher than the DSS capability (high Qg MOSFET or failure), the HV current source is switched ON when VCC reaches VCCMIN, but the voltage on VCC pin keep on decreasing. If there is no UVLO threshold to stop the DRV pulses, the gate voltage will become too low and the risk is high to destroy the MOSFET. NCP1337 features an additional comparator, which threshold is 9.0 V: when VCC reaches this level whereas the HV current source is ON, DRV pulses are stopped and the protection mode is activated. The maximum dV/dt that can be applied to the VCC pin is 9.0 V/ms. The supply capacitor is selected to ensure the maximum dV/dt is not exceeded. Safety Features The NCP1337 includes several safety features to help the power supply designer to build a rugged design: • OVP (Overvoltage on VCC): Activated when voltage on pin VCC is higher than 18.6 V • Brown−Out (Undervoltage lockout on bulk voltage): Activated when voltage on pin BO is below 500 mV • Disable (Comparator activated by an external signal): Activated when the voltage on BO pin is higher than 3.0 V but below 5.0 V • TSD (Temperature shutdown): Typically activated when the die temperature is above 150°C, released at 120°C All these events have the same consequence for the controller: the DRV pulses are stopped. When the condition disappears, the controller restarts with the soft−start activated. However, as the fault timer is still active, it can www.onsemi.com 12 NCP1337 Brown−Out The brown−out protection comparator has a fixed reference of 500 mV. When the comparator is activated (i.e., when the input voltage VIN is above the starting level), a 10 mA internal current source is activated and creates an offset across the bottom resistor of the external resistor divider. It gives the minimum hysteresis of the brown−out protection. By adding a series resistor between the divider and the BO pin, it is possible to adjust (increase) the hysteresis. The BO pin also features two additional comparators: the first one (that toggles at 3.0 V) stops the DRV pulses, whereas the second one (that toggles at 5.0 V) permanently latches off the controller (the VCC should be forced below 4.0 V to release the latch). Figure 8 gives the internal implementation of the BO pin. + + 5V - + 3V Vin + Permanent Latch Enable Vdd 10 mA current source activated when VBOK is high 3.3 meg Rhyst BO + 11 k 500 mV + - BOK Figure 8. Internal Implementation of BO Pin Soft−Skip is a trademark of of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. www.onsemi.com 13 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−7 CASE 751U−01 ISSUE E DATE 20 OCT 2009 SCALE 1:1 −A− 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B ARE DATUMS AND T IS A DATUM SURFACE. 4. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 5. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5 −B− S 0.25 (0.010) B M M 1 4 G C R X 45 _ J −T− SEATING PLANE H 0.25 (0.010) K M D 7 PL M T B S A DIM A B C D G H J K M N S INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 S GENERIC MARKING DIAGRAM SOLDERING FOOTPRINT* 8 1.52 0.060 7.0 0.275 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 1 XXX A L Y W G 4.0 0.155 0.6 0.024 = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. 1.270 0.050 SCALE 6:1 XXXXX ALYWX G mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: 98AON12199D DESCRIPTION: 7−LEAD SOIC Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−7 CASE 751U−01 ISSUE E STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. 7. NOT USED 8. EMITTER DATE 20 OCT 2009 STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. NOT USED 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. NOT USED 8. SOURCE, #1 STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. 6. 7. NOT USED 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. 7. NOT USED 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. NOT USED 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR (DIE 1) 2. BASE (DIE 1) 3. BASE (DIE 2) 4. COLLECTOR (DIE 2) 5. COLLECTOR (DIE 2) 6. EMITTER (DIE 2) 7. NOT USED 8. COLLECTOR (DIE 1) STYLE 9: PIN 1. EMITTER (COMMON) 2. COLLECTOR (DIE 1) 3. COLLECTOR (DIE 2) 4. EMITTER (COMMON) 5. EMITTER (COMMON) 6. BASE (DIE 2) 7. NOT USED 8. EMITTER (COMMON) STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. NOT USED 8. GROUND STYLE 11: PIN 1. SOURCE (DIE 1) 2. GATE (DIE 1) 3. SOURCE (DIE 2) 4. GATE (DIE 2) 5. DRAIN (DIE 2) 6. DRAIN (DIE 2) 7. NOT USED 8. DRAIN (DIE 1) STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. NOT USED 8. COMMON CATHODE DOCUMENT NUMBER: 98AON12199D DESCRIPTION: 7−LEAD SOIC Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. 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