DATA SHEET
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Quasi-Resonant Flyback
Controller, High Frequency
1
The NCP1342 is a highly integrated quasi−resonant flyback
controller suitable for designing high−performance off−line power
converters. With an integrated active X2 capacitor discharge feature,
the NCP1342 can enable no−load power consumption below 30 mW.
The NCP1342 features a proprietary valley−lockout circuitry,
ensuring stable valley switching. This system works down to the 6th
valley and transitions to frequency foldback mode to reduce switching
losses. As the load decreases further, the NCP1342 enters quiet−skip
mode to manage the power delivery while minimizing acoustic noise.
To ensure light load performance with high frequency designs, the
NCP1342 incorporates Rapid Frequency Foldback with Minimum
Peak Current Modulation to reduce the switching frequency quickly.
To help ensure converter ruggedness, the NCP1342 implements
several key protective features such as internal brownout detection, a
non−dissipative Over Power Protection (OPP) for constant maximum
output power regardless of input voltage, a latched overvoltage and
NTC−ready overtemperature protection through a dedicated pin, and
line removal detection to safely discharge the X2 capacitors when the
ac line is removed.
Features
•
•
•
•
•
•
•
•
•
•
•
•
1
SOIC−9 NB
D SUFFIX
CASE 751BP
NCP1342
•
•
•
•
•
8
9
Integrated High−Voltage Startup Circuit with Brownout Detection
Integrated X2 Capacitor Discharge Capability
Wide VCC Range from 9 V to 28 V
28 V VCC Overvoltage Protection
Abnormal Overcurrent Fault Protection for Winding Short Circuit or
Saturation Detection
Internal Temperature Shutdown
Valley Switching Operation with Valley−Lockout for Noise−Free
Operation
Frequency Foldback with 25 kHz Minimum Frequency Clamp for
Increased Efficiency at Light Loads
Rapid Frequency Foldback for Fast Reduction of Switching
Frequency at Light Loads
Skip Mode with Quiet−Skip Technology for Highest Performance
During Light Loads
Minimized Current Consumption for No Load Power Below 30 mW
Frequency Jittering for Reduced EMI Signature
Latching or Auto−Recovery Timer−Based Overload Protection
Adjustable Overpower Protection (OPP)
Adjustable Maximum Frequency Clamp
Fault Pin for Severe Fault Conditions, NTC Compatible for OTP
4 ms Soft−Start Timer
SOIC−8 NB
D SUFFIX
CASE 751
MARKING DIAGRAMS
8
9
1342abcde
ALYWf
G
1
1342abcde
ALYWf
G
1
1342abcde = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
f
= Additional Options Code
G
= Pb−Free Package
PIN CONNECTIONS
Fault
FMAX
FB
ZCD/OPP
CS
Fault
1
HV
VCC
DRV
GND
1
HV
FB
VCC
ZCD/OPP
DRV
GND
CS
(Top Views)
ORDERING INFORMATION
See detailed ordering and shipping information on page 3 of
this data sheet.
This document contains information on some products that are still under development.
onsemi reserves the right to change or discontinue these products without notice.
© Semiconductor Components Industries, LLC, 2017
August, 2021 − Rev. 20
1
Publication Order Number:
NCP1342/D
NCP1342
TYPICAL APPLICATION SCHEMATIC
+
+
Vout
NCP1342
HV
Fault
+
L
N
VCC
FB
EMI
Filter
ZCD/OPP DRV
−tº
CS
GND
+
Figure 1. NCP1342 8−Pin Typical Application Circuit
+
NCP1342
+
L
N
EMI
Filter
Fault
FMAX
FB
HV
VCC
ZCD/OPP DRV
−tº
CS
GND
+
Figure 2. NCP1342 9−Pin Typical Application Circuit
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2
+
Vout
NCP1342
Table 1. PART NUMBER DECODE − NCP1342ABCDEF
NCP1342
A
B
OTP/Overload
Device
C
Jitter Frequency/Amplitude
A − AR/AR
A − 1.55 kHz/75 mV
D
E
F*
Quiet−Skip
CS Min
CS Min Shift
Additional
A − 800 Hz
A − 200 mV
A − 400 mV
−
B − Latch/AR
B − 1.55 kHz/92 mV
B − 1.2 kHz
B − 150 mV
B − 350 mV
A
C − AR/Latch
C − 1.55 kHz/55 mV
C − 1.56 kHz
C − 100 mV
C − 300 mV
C
D − Latch/Latch
D − 1.55 kHz/61 mV
D − Disabled
D − 250 mV
D − 250 mV
D
E − Disabled
E
E − AR/None
E − 1.3 kHz/75 mV
F − Latch/None
F − 1.3 kHz/92 mV
F
G − 1.3 kHz/55 mV
G
H − 1.3 kHz/61 mV
H
J − 3.9 kHz/75 mV
K − 3.9 kHz/92 mV
L − 3.9 kHz/55 mV
M − 3.9 kHz/61 mV
N − Disabled
*Not present in all parts. See Table 2 for details.
Table 2. ADDITIONAL PART OPTIONS
F
Description
−
Default Configuration
A
X2 Discharge Disabled, VBO(stop) = 84 V, VBO(start) = 94 V
D
X2 Discharge Disabled, VBO(stop) = 84 V, VBO(start) = 94 V, Resettable Overload Timer
E
X2 Discharge Disabled, Brownout Disabled
F
X2 Discharge Disabled, VCC(off) Triggers Autorecovery Timer (trestart)
G
X2 Discharge Disabled
H
VBO(stop) = 84 V, VBO(start) = 94 V
Table 3. ORDERING INFORMATION
Part Number
NCP1342AMDCCDR2G
Device Marking
Package
1342AMDCC
SOIC−8 NB (Pb−Free)
NCP1342ANDAAD1R2G
1342ANDAA
NCP1342DADBDD1R2G
1342DADBD
NCP1342AMDCDAD1R2G
1342AMDCDA
NCP1342AMAACD1R2G
1342AMAAC
NCP1342ANACED1R2G
1342ANACE
NCP1342ANDBDD1R2G
1342ANDBD
NCP1342BKDCDAD1R2G
1342BKDCDA
NCP1342BMDCDAD1R2G
1342BMDCDA
NCP1342BMDCDD1R2G
NCP1342BMDCDDD1R2G
Shipping
SOIC−9 NB (Pb−Free)
1342BMDCD
1342BMDCDD
NCP1342AMDCDD1R2G
1342AMDCD
NCP1342ANACCED1R2G
1342ANACCE
NCP1342ENACEFD1R2G
1342ENACEF
NCP1342AMDADGD1R2G
1342AMDADG
NCP1342AMDCDHD1R2G
1342AMDCDH
NCP1342ENDCEAD1R2G
(In Development)
1342ENDCEA
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3
2500 / Tape & Reel
NCP1342
FUNCTIONAL BLOCK DIAGRAM
TSD
IFMAX
VDD
FMAX
FMAX
Control
QR_FMAX
BO
X2
Abnormal OCP
OVLD
OVP
OTP
Fault
Management
Fault
Off−Time
Control
ZCD/OPP
Dead−Time
Control
OPP
Control
VFB(open)
OPP
FB
Jitter Ramp
K FB
VCC
t tout
QR_FMAX
R FB
FB
HV
VCC
Valley/FF
Control
FB
VCC(OVP)
X2/BO Detect
+
VCC
Management
Clamp
Quiet−Skip
Control
S
Q
DRV
R
GND
÷
On−Time
Control
V DD
Fault
ICS
V DD
ILIM1
Detect
t LEB1
CS
t LEB2
ILIM2
Detect
8−Pin
OVP
t OVLD
OVLD
OTP
Fault
RFault(clamp)
OPP
V Fault(clamp)
Abnormal OCP
Count 4
9−Pin
OVP/OTP
Detect
IOTP
MPCM
Control
FB
Figure 3. NCP1342 Block Diagram
Table 4. PIN FUNCTIONAL DESCRIPTION
8−Pin
9−Pin
Pin Name
1
1
Fault
The controller enters fault mode if the voltage on this pin is pulled above or below the fault
thresholds. A precise pull up current source allows direct interface with an NTC thermistor.
Function
−
2
FMAX
A resistor to ground sets the value for the maximum switching frequency clamp. If this pin is
pulled above 4 V, the maximum frequency clamp is disabled.
2
3
FB
3
4
ZCD/OPP
4
5
CS
5
6
GND
Ground reference.
6
7
DRV
This is the drive pin of the circuit. The DRV high−current capability (−0.5 /+0.8 A) makes it suitable to effectively drive high gate charge power MOSFETs.
7
8
VCC
This pin is the positive supply of the IC. The circuit starts to operate when VCC exceeds 17 V and
turns off when VCC goes below 9 V (typical values). After start−up, the operating range is 9 V up
to 28 V.
−
9
N/C
Removed for creepage distance.
8
10
HV
This pin is the input for the high voltage startup and brownout detection circuits. It also contains
the line removal detection circuit to safely discharge the X2 capacitors when the line is removed.
Feedback input for the QR Flyback controller. Allows direct connection to an optocoupler.
A resistor divider from the auxiliary winding to this pin provides input to the demagnetization detection comparator and sets the OPP compensation level.
Input to the cycle−by−cycle current limit comparator.
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4
NCP1342
Table 5. MAXIMUM RATINGS
Rating
Symbol
Value
High Voltage Startup Circuit Input Voltage
VHV(MAX)
−0.3 to 700
V
High Voltage Startup Circuit Input Current
IHV(MAX)
20
mA
Supply Input Voltage
VCC(MAX)
−0.3 to 30
V
Supply Input Current
ICC(MAX)
30
mA
Supply Input Voltage Slew Rate
dVCC/dt
1
V/ms
Fault Input Voltage
VFault(MAX)
−0.3 to VCC + 0.7 V
V
Fault Input Current
IFault(MAX)
10
mA
Zero Current Detection and OPP Input Voltage
VZCD(MAX)
−0.3 to VCC + 0.7 V
V
Zero Current Detection and OPP Input Current
IZCD(MAX)
−2/+5
mA
VMAX
−0.3 to 5.5
V
Maximum Input Voltage (Other Pins)
Unit
Maximum Input Current (Other Pins)
IMAX
10
mA
Driver Maximum Voltage (Note 1)
VDRV
−0.3 to VDRV(high)
V
IDRV(SRC)
IDRV(SNK)
500
800
mA
Operating Junction Temperature
TJ
−40 to 125
°C
Maximum Junction Temperature
TJ(MAX)
150
°C
TSTG
–60 to 150
°C
Driver Maximum Current
Storage Temperature Range
Power Dissipation (TA = 25°C, 1 oz. Cu, 42
DR2G Suffix, SOIC−8
D1R2G Suffix, SOIC−9
mm2
Copper Clad Printed Circuit)
Thermal Resistance (TA = 25°C, 1 oz. Cu, 42 mm2 Copper Clad Printed Circuit)
DR2G Suffix, SOIC−8
D1R2G Suffix, SOIC−9
ESD Capability
Human Body Model per JEDEC Standard JESD22−A114F (All pins except HV)
Human Body Model per JEDEC Standard JESD22−A114F (HV Pin)
Charge Device Model per JEDEC Standard JESD22−C101F
Latch−Up Protection per JEDEC Standard JESD78E
PD(MAX)
RqJA
450
330
225
300
2000
800
1000
±100
mW
°C/W
V
V
V
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Maximum driver voltage is limited by the driver clamp voltage, VDRV(high), when VCC exceeds the driver clamp voltage. Otherwise, the
maximum driver voltage is VCC.
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NCP1342
Table 6. ELECTRICAL CHARACTERISTICS: (VCC = 12 V, VHV = 120 V, VFault = open, VFB = 2.4 V, VCS = 0 V, VZCD = 0 V, VFMAX
= 0 V, CVCC = 100 nF , CDRV = 100 pF, for typical values TJ = 25°C, for min/max values, TJ is – 40°C to 125°C, unless otherwise noted)
Characteristics
Conditions
Symbol
Min
Typ
Max
VCC(on)
17.0
18.0
9.0
–
6.5
0.70
18.0
19.0
9.5
–
7.5
1.05
Unit
START−UP AND SUPPLY CIRCUITS
Supply Voltage
Startup Threshold
Discharge Voltage During Line Removal
Minimum Operating Voltage
Operating Hysteresis
Internal Latch / Logic Reset Level
Transition from Istart1 to Istart2
dV/dt = 0.1 V/ms
VCC increasing
VCC decreasing
VCC decreasing
VCC(on) − VCC(off)
VCC decreasing
VCC increasing, IHV = 650 mA
VCC(X2_reg)
VCC(off)
VCC(HYS)
VCC(reset)
VCC(inhibit)
16.0
17.0
8.5
7.5
4.5
0.30
VCC(off) Delay
VCC decreasing
tdelay(VCC_off)
25
32
40
ms
Startup Delay
Delay from VCC(on) to DRV Enable
tdelay(start)
–
–
500
ms
VHV(MIN)
–
–
30
V
Vcc = 0 V
Istart1
0.2
0.5
0.65
mA
Vcc = Vcc(on) – 0.5 V
–40°C to 105°C
–40°C to 125°C
Istart2
2.4
2.0
3.75
3.75
5.0
5.0
VHV = 162.5 V
VHV = 325 V
VHV = 700 V
IHV(off1)
IHV(off2)
IHV(off3)
–
–
–
–
–
–
15
20
50
VCC = VCC(on) – 0.5 V
VFB = 0 V
fsw = 50 kHz, CDRV = open
ICC1
ICC2
ICC3
−
−
−
0.115
0.230
1.0
0.250
0.400
1.5
VCC(OVP)
27
28
29
V
tdelay(VCC_OVP)
25
32
40
ms
tline(removal)
65
100
135
ms
tline(discharge)
21
32
43
ms
tline(detect)
21
32
43
ms
ICC(discharge)
13
18
23
mA
VHV(discharge)
–
–
30
V
107
89
112
94
116
99
93
79
98
84
102
89
9.0
6.0
14
10
–
–
Minimum Voltage for Start−Up Current
Source
Inhibit Current Sourced from VCC Pin
Start−Up Current Sourced from VCC Pin
Start−Up Circuit Off−State Leakage Current
Supply Current
Fault or Latch
Skip Mode (excluding FB current)
Operating Current
V
mA
mA
mA
VCC Overvoltage Protection Threshold
VCC Overvoltage Protection Delay
X2 CAPACITOR DISCHARGE (ALL VERSIONS EXCEPT xxxxxA, xxxxxD, xxxxxE, xxxxxF, xxxxxG)
Line Voltage Removal Detection Timer
Discharge Timer Duration
Line Detection Timer Duration
VCC Discharge Current
VCC = 20 V
HV Discharge Level
BROWNOUT DETECTION (ALL VERSIONS EXCEPT xxxxxE)
System Start−Up Threshold
Other Versions
Versions xxxxxA, xxxxxD, xxxxxH
VHV increasing
VBO(start)
V
Brownout Threshold
Other Versions
Versions xxxxxA, xxxxxD, xxxxxH
VHV decreasing
Hysteresis
Other Versions
Versions xxxxxA, xxxxxD, xxxxxH
VHV increasing
Brownout Detection Blanking Time
VHV decreasing
tBO(stop)
40
70
100
ms
Rise Time
VDRV from 10% to 90%
tDRV(rise)
–
20
40
ns
Fall Time
VDRV from 90% to 10%
tDRV(fall)
–
5
30
ns
VBO(stop)
V
VBO(HYS)
V
GATE DRIVE
2. NTC with R110 = 8.8 kW
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NCP1342
Table 6. ELECTRICAL CHARACTERISTICS: (VCC = 12 V, VHV = 120 V, VFault = open, VFB = 2.4 V, VCS = 0 V, VZCD = 0 V, VFMAX
= 0 V, CVCC = 100 nF , CDRV = 100 pF, for typical values TJ = 25°C, for min/max values, TJ is – 40°C to 125°C, unless otherwise noted)
Characteristics
Conditions
Symbol
Min
Typ
Max
IDRV(SRC)
IDRV(SNK)
–
–
500
800
–
–
Unit
GATE DRIVE
Current Capability
Source
Sink
mA
High State Voltage
VCC = VCC(off) + 0.2 V, RDRV = 10 kW
VCC = 30 V, RDRV = 10 kW
VDRV(high1)
VDRV(high2)
8.0
10
–
12
–
14
V
Low Stage Voltage
VFault = 0 V
VDRV(low)
–
–
0.25
V
VFB(open)
4.8
5.0
5.1
V
KFB
3.7
4.0
4.3
–
VFB = 0.4 V
RFB
17
20
23
kW
VFB decreasing
VFB decreasing
VFB decreasing
VFB decreasing
VFB decreasing
VFB increasing
VFB increasing
VFB increasing
VFB increasing
VFB increasing
V1to2
V2to3
V3to4
V4to5
V5to6
V6to5
V5to4
V4to3
V3to2
V2to1
1.316
1.128
1.034
0.940
0.846
1.410
1.504
1.598
1.692
1.880
1.400
1.200
1.100
1.000
0.900
1.500
1.600
1.700
1.800
2.000
1.484
1.272
1.166
1.060
0.954
1.590
1.696
1.802
1.908
2.120
VFMAX = 0.5 V
VFMAX = 3.5 V
fMAX1
fMAX2
440
61
500
70
560
79
FMAX Disable Threshold
(9−Pin Versions Only)
VFMAX(disable)
3.85
4.00
4.15
V
FMAX Pin Source Current
(9−Pin Versions Only)
IFMAX
9.0
10
11
mA
ton(MAX)
28
32
40
ms
FEEDBACK
Open Pin Voltage
VFB to Internal Current Setpoint Division
Ratio
Internal Pull−Up Resistor
Valley Thresholds
Transition from 1st to 2nd valley
Transition from 2nd to 3rd valley
Transition from 3rd to 4th valley
Transition from 4th to 5th valley
Transition from 5th to 6th valley
Transition from 6th to 5th valley
Transition from 5th to 4th valley
Transition from 4th to 3rd valley
Transition from 3rd to 2nd valley
Transition from 2nd to 1st valley
Maximum Frequency Clamp
(9−Pin Versions Only)
V
Maximum On Time
kHz
DEMAGNETIZATION INPUT
ZCD threshold voltage
VZCD decreasing
VZCD(trig)
35
60
90
mV
ZCD hysteresis
VZCD increasing
VZCD(HYS)
15
25
55
mV
VZCD step from 4.0 V to −0.3 V
tdemag
–
80
250
ns
IQZCD = 5.0 mA
IQZCD = −2.0 mA
VZCD(MAX)
VZCD(MIN)
12.4
−0.9
12.7
−0.7
13
0
tZCD(blank)
600
700
800
ns
While in soft−start
After soft−start complete
t(tout1)
t(tout2)
80
5.1
100
6.0
120
6.9
ms
Current Limit Threshold Voltage
VCS increasing
VILIM1
0.760
0.800
0.840
V
Leading Edge Blanking Duration
DRV minimum width minus
tdelay(ILIM1)
tLEB1
220
265
330
ns
Step VCS 0 V to VILIM1 + 0.5 V,
VFB = 4 V
tdelay(ILIM1)
–
95
175
ns
Demagnetization Propagation Delay
ZCD Clamp Voltage
Positive Clamp
Negative Clamp
Blanking Delay After Turn−Off
Timeout After Last Demagnetization
Detection
V
CURRENT SENSE
Current Limit Threshold Propagation Delay
2. NTC with R110 = 8.8 kW
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NCP1342
Table 6. ELECTRICAL CHARACTERISTICS: (VCC = 12 V, VHV = 120 V, VFault = open, VFB = 2.4 V, VCS = 0 V, VZCD = 0 V, VFMAX
= 0 V, CVCC = 100 nF , CDRV = 100 pF, for typical values TJ = 25°C, for min/max values, TJ is – 40°C to 125°C, unless otherwise noted)
Characteristics
Conditions
Symbol
Min
Typ
Max
Unit
Step VCS 0 V to 0.7 V, VFB = 2.4
tdelay(PWM)
–
125
175
ns
170
115
70
215
200
150
100
250
230
185
130
285
CURRENT SENSE
PWM Comparator Propagation Delay
Minimum Peak Current
Versions xxxAx
Versions xxxBx
Versions xxxCx
Versions xxxDx
VCS(MIN)
mV
Abnormal Overcurrent Fault Threshold
VCS increasing, VFB = 4 V
VILIM2
1.125
1.200
1.275
V
Abnormal Overcurrent Fault Blanking
Duration
DRV minimum width minus
tdelay(ILIM2)
tLEB2
80
110
140
ns
Step VCS 0 V to VILIM2 + 0.5 V,
VFB = 4 V
tdelay(ILIM2)
–
80
175
ns
nILIM2
–
4
–
tOPP(delay)
–
95
175
ns
tOPP(blank)
220
280
330
ns
ICS
0.7
1.0
1.5
mA
3.5
1.43
1.2
−
3.9
1.55
1.3
−
4.2
1.68
1.4
−
82
65
52
45
−
92
75
61
55
−
102
85
70
65
−
2.8
4.0
5.0
120
−
160
−
200
−
Abnormal Overcurrent Fault Propagation
Delay
Number of Consecutive Abnormal Overcurrent Faults to Enter Latch Mode
Overpower Protection Delay
VCS dv/dt = 1 V/ms, measured from
VOPP(MAX) to DRV falling edge
Overpower Signal Blanking Delay
Pull−Up Current Source
VCS = VILIM2 − 10 mV
JITTERING
Jitter Frequency
Versions xJxxx, xKxxx, xLxxx, xMxxx
Versions xAxxx, xBxxx, xCxxx, xDxxx
Versions xExxx, xFxxx, xGxxx, xHxxx
Versions xNxxx
fjitter
Peak Jitter Voltage
Versions xBxxx, xFxxx, xKxxx
Versions xAxxx, xExxx, xJxxx
Versions xDxxx, xHxxx, xMxxx
Versions xCxxx, xGxxx, xLxxx
Versions xNxxx
Vjitter
kHz
mV
FAULT PROTECTION
Measured from
1st DRV pulse to VCS = VILIM1
tSSTART
VCS = VILIM1
tOVLD
Overvoltage Protection (OVP) Threshold
VFault increasing
VFault(OVP)
2.79
3.00
3.21
V
OVP Detection Delay
VFault increasing
tdelay(OVP)
22.5
30
37.5
ms
Overtemperature Protection (OTP) Threshold (Note 2)
VFault decreasing
VFault(OTP_in)
380
400
420
mV
Overtemperature Protection (OTP) Exiting
Threshold (Note 2)
VFault increasing
VFault(OTP_out)
874
910
966
mV
VFault decreasing
tdelay(OTP)
22.5
30
37.5
ms
VFault = VFault(OTP_in) + 0.2 V
TJ = 25°C to 125°C
IOTP
43.75
45.00
46.25
mA
Fault Input Clamp Voltage
VFault(clamp)
1.15
1.7
2.25
V
Fault Input Clamp Series Resistor
RFault(clamp)
1.32
1.55
1.78
kW
trestart
1.8
2.0
2.2
s
Soft−Start Period
Flyback Overload Fault Timer
Other versions
Versions Exxxx, Fxxxx
OTP Detection Delay
OTP Pull−Up Current Source
Autorecovery Timer
2. NTC with R110 = 8.8 kW
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8
ms
ms
NCP1342
Table 6. ELECTRICAL CHARACTERISTICS: (VCC = 12 V, VHV = 120 V, VFault = open, VFB = 2.4 V, VCS = 0 V, VZCD = 0 V, VFMAX
= 0 V, CVCC = 100 nF , CDRV = 100 pF, for typical values TJ = 25°C, for min/max values, TJ is – 40°C to 125°C, unless otherwise noted)
Characteristics
Conditions
Symbol
Min
Typ
Max
Unit
fMIN
21.5
25
27.0
kHz
tDT(MAX)
32
−
−
ms
1.18
0.770
0.590
−
1.25
0.833
0.640
−
1.40
0.900
0.690
−
LIGHT/NO LOAD MANAGEMENT
Minimum Frequency Clamp
Dead−Time Added During Frequency
Foldback
VFB = 400 mV
Quiet−Skip Timer
Versions xxAxx
Versions xxBxx
Versions xxCxx
Versions xxDxx
tquiet
ms
Skip Threshold
VFB decreasing
Vskip
350
400
450
mV
Skip Hysteresis
VFB increasing
Vskip(HYS)
20
50
70
mV
340
300
250
200
−
400
350
300
250
−
460
400
350
300
−
780
−
800
−
820
−
730
−
750
−
770
−
0.85
−
1.00
−
1.05
−
RAPID FREQUENCY FOLDBACK
Minimum Peak Current Shift
Versions xxxxA
Versions xxxxB
Versions xxxxC
Versions xxxxD
Versions xxxxE
VMPCM(delta)
Entry Threshold
Versions xxxxA, xxxxB, xxxxC, xxxxD
Versions xxxxE
VMPCM(entry)
Exit Threshold
Versions xxxxA, xxxxB, xxxxC, xxxxD
Versions xxxxE
VMPCM(exit)
Transition Timer
Versions xxxxA, xxxxB, xxxxC, xxxxD
Versions xxxxE
tMPCM
mV
mV
mV
ms
THERMAL PROTECTION
Thermal Shutdown
Temperature increasing
TSHDN
–
140
–
°C
Thermal Shutdown Hysteresis
Temperature decreasing
TSHDN(HYS)
–
40
–
°C
2. NTC with R110 = 8.8 kW
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9
NCP1342
INTRODUCTION
The NCP1342 implements a quasi−resonant flyback
converter utilizing current−mode architecture where the
switch−off event is dictated by the peak current. This IC is
an ideal candidate where low parts count and cost
effectiveness are the key parameters, particularly in ac−dc
adapters, open−frame power supplies, etc. The NCP1342
incorporates all the necessary components normally needed
in modern power supply designs, bringing several
enhancements such as non−dissipative overpower
protection (OPP), brownout protection, and frequency
reduction management for optimized efficiency over the
entire power range. Accounting for the needs of extremely
low standby power requirements, the controller features
minimized current consumption and includes an automatic
X2 capacitor discharge circuit that eliminates the need to
install power−consuming resistors across the X2 input
capacitors.
• High−Voltage Start−Up Circuit: Low standby power
consumption cannot be obtained with the classic
resistive start−up circuit. The NCP1342 incorporates a
high−voltage current source to provide the necessary
current during start−up and then turns off during normal
operation.
• Internal Brownout Protection: The ac input voltage is
sensed via the high−voltage pin. When this voltage is
too low, the NCP1342 stops switching. No restart
attempt is made until the ac input voltage is back within
its normal range.
• X2−Capacitor Discharge Circuitry: Per the
IEC60950 standard, the time constant of the X2 input
capacitors and their associated discharge resistors must
be less than 1 s in order to avoid electrical shock when
the user unplugs the power supply and inadvertently
touches the ac input cord terminals. By providing an
automatic means to discharge the X2 capacitors, the
NCP1342 eliminates the need to install X2 discharge
resistors, thus reducing power consumption.
• Quasi−Resonant, Current−Mode Operation:
Quasi−Resonant (QR) mode is a highly efficient mode
of operation where the MOSFET turn−on is
synchronized with the point where its drain−source
voltage is at the minimum (valley). A drawback of this
mode of operation is that the operating frequency is
inversely proportional to the system load. The
NCP1342 incorporates a valley lockout (VLO) and
frequency foldback technique to eliminate this
drawback, thus maximizing the efficiency over the
entire power range.
• Valley Lockout: In order to limit the maximum
frequency while remaining in QR mode, one would
traditionally use a frequency clamp. Unfortunately, this
can cause the controller to jump back and forth between
two different valleys, which is often undesirable. The
•
•
•
•
•
•
•
NCP1342 patented VLO circuitry solves this issue by
determining the operating valley based on the system
load, and locking out other valleys unless a significant
change in load occurs.
Rapid Frequency Foldback: As the load continues to
decrease, it becomes beneficial to reduce the switching
frequency. When the load is light enough, the NCP1342
enters rapid frequency foldback mode. During this
mode, the minimum peak current is limited and
dead−time is added to the switching cycle, thus
reducing the frequency and switching operation to
discontinuous conduction mode (DCM). Dead−time
continues to be added until skip mode is reached, or the
switching frequency reaches its minimum level of 25
kHz.
Minimum Peak Current Modulation (MPCM): In
order to reduce the switching frequency even faster (for
high frequency designs), the NCP1342 uses MPCM to
increase the minimum peak current during frequency
foldback. It also reduces the minimum peak current
gradually as the load decreases to ensure optimum skip
mode entry.
Skip Mode: To further improve light or no−load power
consumption while avoiding audible noise, the
NCP1342 enters skip mode when the operating
frequency reaches its minimum value. To avoid
acoustic noise, the circuit prevents the switching
frequency from decaying below 25 kHz. This allows
regulation via bursts of pulses at 25 kHz or greater
instead of operating in the audible range.
Quiet−Skip: To further reduce acoustic noise, the
NCP1342 incorporates a novel circuit to prevent the
skip mode burst period from entering the audible range
as well.
Internal OPP: In order to limit power delivery at high
line, a scaled version of the negative voltage present on
the auxiliary winding during the on−time is routed to
the ZCD/OPP pin. This provides the designer with a
simple and non−dissipative means to reduce the
maximum power capability as the bulk voltage
increases.
Frequency Jittering: In order to reduce the EMI
signature, a low frequency triangular voltage waveform
is added to the input of the PWM comparator. This
helps by spreading out the energy peaks during noise
analysis.
Internal Soft−Start: The NCP1342 includes a 4 ms
soft−start to prevent the main power switch from being
overly stressed during start−up. Soft−start is activated
each time a new startup sequence occurs or during
auto−recovery mode.
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10
NCP1342
• Dedicated Fault Input: The NCP1342 includes a
•
•
clamp can be adjusted via an external resistor from the
FMAX Pin to ground. It can also be disabled by pulling
the FMAX pin above 4 V.
dedicated fault input. It can be used to sense an
overvoltage condition and latch off the controller by
pulling the pin above the overvoltage protection (OVP)
threshold. The controller is also disabled if the Fault pin
is pulled below the overtemperature protection (OTP)
threshold. The OTP threshold is configured for use with
a NTC thermistor.
Overload/Short−Circuit Protection: The NCP1342
implements overload protection by limiting the
maximum time duration for operation during overload
conditions. The overload timer operates whenever the
maximum peak current is reached. In addition to this,
special circuitry is included to prevent operation in
CCM during extreme overloads, such as an output
short−circuit.
Maximum Frequency Clamp: The 9−pin version of
NCP1342 includes a maximum frequency clamp. The
AC
CON
HIGH VOLTAGE START−UP
The NCP1342 contains a multi−functional high voltage
(HV) pin. While the primary purpose of this pin is to reduce
standby power while maintaining a fast start−up time, it also
incorporates brownout detection and line removal detection.
The HV pin must be connected directly to the ac line in
order for the X2 discharge circuit to function correctly. Line
and neutral should be diode “ORed” before connecting to the
HV pin as shown in Figure 4. The diodes prevent the pin
voltage from going below ground. A resistor in series with
the pin should be used to protect the pin during EMC or surge
testing. A low value resistor should be used (= 25 kHz
DRV
1.25 ms
Fsw >= 25 kHz
1.25 ms
Fsw >= 25 kHz
1.25 ms
Fsw >= 25 kHz
1.25 ms
Fsw >= 25 kHz
DRV
FB
DRV
FB
DRV
FB
DRV
FB
>1.25 ms
Fsw >= 25 kHz
DRV
MIN
Load
FB
Figure 16. Quiet−Skip Timing Diagram
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21
NCP1342
FAULT MANAGEMENT
external latch input. When the NCP1342 detects a latching
fault, the driver is immediately disabled. The operation
during a latching fault is identical to that of a non−latching
fault except the controller will not attempt to restart at the
next VCC(on), even if the fault is removed. In order to clear
the latch and resume normal operation, VCC must first be
allowed to drop below VCC(reset) or a line removal event
must be detected. This operation is shown in Figure 17.
The NCP1342 contains three separate fault modes.
Depending on the type of fault, the device will either latch
off, restart when the fault is removed, or resume operation
after the auto−recovery timer expires.
Latching Faults
Some faults will cause the NCP1342 to latch off. These
include the abnormal OCP (AOCP), VCC OVP, and the
Fault
Fault
Applied
Fault
Removed
time
V CC
V CC (on)
V CC (off)
time
FDRV
time
I HV
Istart 2
I start (off)
Figure 17. Operation During Latching Fault
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22
time
NCP1342
Non−Latching Faults
re−enabled when VCC reaches VCC(on) according to the
initial power−on sequence, provided VHV is above
VBO(start). This operation is shown in Figure 18. When VHV
is reaches VBO(start), VCC immediately charges to VCC(on).
If VCC is already above VCC(on) when the fault is removed,
the controller will start immediately as long as VHV is above
VBO(start).
When the NCP1342 detects a non−latching fault
(brownout or thermal shutdown), the drivers are disabled,
and VCC falls towards VCC(off) due to the IC internal current
consumption. Once VCC reaches VCC(off), the HV current
source turns on and CVCC begins to charge towards VCC(on).
When VCC, reaches VCC(on), the cycle repeats until the fault
is removed. Once the fault is removed, the NCP1342 is
Fault
Fault
Applied
Fault
Removed
Waits for next
V CC(on) before
starting
VCC
time
V CC (on )
V CC (off )
time
FDRV
time
IHV
Istart 2
Istart (off)
Figure 18. Operation During Non−Latching Fault
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23
time
NCP1342
Auto−recovery Timer Faults
running, the HV current source turns on and off to maintain
Vcc between Vcc(off) and Vcc(on). Once the auto−recovery
timer expires, the controller will attempt to start normally at
the next VCC(on) provided VHV is above VBO(start). This
operation is shown in Figure 19.
Some faults faults cause the NCP1342 auto−recovery
timer to run. If an auto−recovery fault is detected, the gate
drive is disabled and the auto−recovery timer, tautorec
(typically 1.2 s), starts. While the auto−recovery timer is
Fault
Applied
Fault
Removed
Fault
time
VCC
VCC(on)
VCC(off)
Restarts
At VCC(on)
(new burst
cycle if Fault
still present)
DRV
time
Controller
stops
time
Autorecovery
Timer
1.2 s
trestart
Figure 19. Operation During Auto−Recovery Fault
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24
time
NCP1342
PROTECTION FEATURES
Brownout Protection
Figure 20 shows the brownout detector waveforms during
a brownout.
When a brownout is detected, the controller stops
switching and enters non−latching fault mode (see
Figure 18). The HV current source alternatively turns on and
off to maintain VCC between VCC(on) and VCC(off) until the
input voltage is back above VBO(start).
A timer is enabled once VHV drops below its disable
threshold, VBO(stop) (typically 99 V). The controller is
disabled if VHV doesn’t exceed VBO(stop) before the
brownout timer, tBO (typically 54 ms), expires. The timer is
set long enough to ignore a two cycle dropout. The timer
starts counting once VHV drops below VBO(stop).
V HV
V BO (start )
V BO (stop )
time
Brownout
Timer
Brownout
detected
V CC
Starts
Charging
Immediately
V CC (on)
Fault
Cleared
Restarts at
next V CC(on)
time
V CC (off )
tdelay (start )
time
DRV
Figure 20. Operation During Brownout
Line Removal Detection and X2 Capacitor Discharge
time
discharge circuitry. A novel approach is used to reconfigure
the high voltage startup circuit to discharge the input filter
capacitors upon removal of the ac line voltage. The line
removal detection circuitry is always active to ensure safety
compliance.
The line removal is detected by digitally sampling the
voltage present at the HV pin, and monitoring the slope.
A timer, tline(removal) (typically 100 ms), is used to detect
when the slope of the input signal is negative or below the
resolution level. The timer is reset any time a positive slope
Safety agency standards require the input filter capacitors
to be discharged once the ac line voltage is removed. A
resistor network is the most common method to meet this
requirement. Unfortunately, the resistor network consumes
power across all operating modes and it is a major
contributor of input power losses during light−load and
no−load conditions.
The NCP1342 eliminates the need for external discharge
resistors by integrating active input filter capacitor
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25
NCP1342
is detected. Once the timer expires, a line removal condition
is acknowledged initiating an X2 capacitor discharge cycle,
and the controller is disabled.
If VCC is above VCC(on), it is first discharged to VCC(on).
A second timer, tline(discharge) (typically 32 ms), is used for
the time limiting of the discharge phase to protect the device
against overheating. Once the discharge phase is complete,
tline(discharge) is reused while the device checks to see if the
line voltage is reapplied. During the discharge phase, if VCC
drops to VCC(on), it is quickly recharged to VCC(X2_reg). The
discharging process is cyclic and continues until the ac line
is detected again or the voltage across the X2 capacitor is
lower than VHV(discharge) (30 V maximum). This feature
allows the device to discharge large X2 capacitors in the
input line filter to a safe level.
It is important to note that the HV pin cannot be
connected to any dc voltage due to this feature, i.e.
directly to the bulk capacitor.
X2 Capacitor
Discharge
VHV
VBO(start )
VBO(stop)
X2 Capacitor
Discharge
AC Line Unplug
VHV(discharge )
AC
Timer
Starts
Timer
tline(removal )
AC
Timer
Restarts
time
AC
Timer
Expires
No AC Detection
tline(discharge /detect )
tline(removal )
DRV
X2 Discharge
Current
tline(discharge )
tline(detect )
X2 Discharge
Device is stopped
Istart 2
ICC
ICC(discharge )
0
ICC3
Istart 2
VCC
VCC(X2_reg)
VCC(on)
Figure 21. Line Removal Timing
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26
tline(discharge )
X2 Discharge
time
NCP1342
X2 Capacitor
Discharge
VHV
VBO(start )
VBO(stop )
AC Line Unplug
VHV(discharge )
AC
Timer
Starts
Timer
tline (removal )
AC
Timer
Expires
AC
Timer
Restarts
AC Detected
time
tline(discharge /detect )
time
X2 Discharge
Device is stopped
X2 Discharge
Current
time
tline (discharge )
tline (removal )
DRV
tdelay (start )
Istart 2
time
ICC
ICC(discharge )
0
ICC3
Istart 2
time
VCC
VCC(X2_reg)
VCC(on)
Figure 22. Line Removal Timing with AC Reapplied
the lower fault threshold, VFault(OTP_in) (typically 0.4 V).
The lower threshold is normally used for detecting an
overtemperature fault. The controller operates normally
while the Fault pin voltage is maintained within the upper
and lower fault thresholds. Figure 23 shows the architecture
of the Fault input.
The Fault input signal is filtered to prevent noise from
triggering the fault detectors. Upper and lower fault detector
blanking delays, tdelay(OVP) and tdelay(OTP),are both
typically 30 ms. A fault is detected if the fault condition is
asserted for a period longer than the blanking delay.
An over temperature protection block monitors the
junction temperature during the discharge process to avoid
thermal runaway, in particular during open/short pins safety
tests. Please note that the X2 discharge capability is also
active at all times, including off−mode and before the
controller actually starts to pulse (e.g. if the user unplugs the
converter during the start−up sequence).
Dedicated Fault Input
The NCP1342 includes a dedicated fault input accessible
via the Fault pin (8−pin and 9−pin versions only). The
controller can be latched by pulling up the pin above the
upper fault threshold, VFault(OVP) (typically 3.0 V). The
controller is disabled if the Fault pin voltage is pulled below
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27
NCP1342
OVP
voltage drop across the thermistor. The resistance of the
NTC thermistor decreases at higher temperatures resulting
in a lower voltage across the thermistor. The controller
detects a fault once the thermistor voltage drops below
VFault(OTP_in).
The controller bias current is reduced during power up by
disabling most of the circuit blocks including IFault(OTP).
This current source is enabled once VCC reaches VCC(on). A
filter capacitor is typically connected between the Fault and
GND pins. This will result in a delay before VFault reaches
its steady state value once IFault(OTP) is enabled. Therefore,
the lower fault comparator (i.e. overtemperature detection)
is ignored during soft−start.
Version A latches off the controller after an
overtemperature fault is detected according to Figure 17. In
Version B, the controller is re−enabled once the fault is
removed such that VFault increases above VFault(OTP_out),
the auto−recovery timer expires, and VCC reaches VCC(on)
as shown in Figure 19.
An active clamp prevents the Fault pin voltage from
reaching the upper latch threshold if the pin is open. To reach
the upper threshold, the external pull−up current has to be
higher than the pull−down capability of the clamp (set by
RFault(clamp) at VFault(clamp)), i.e., approximately 1 mA.
The upper fault threshold is intended to be used for an
overvoltage fault using a zener diode and a resistor in series
from the auxiliary winding voltage. The controller is latched
once VFault exceeds VFault(OVP).
Once the controller is latched, it follows the behavior of
a latching fault according to Figure 17 and is only reset if
VCC is reduced to VCC(reset), or X2 discharge is activated. In
the typical application these conditions occur only if the ac
voltage is removed from the system.
OTP
The lower fault threshold is intended to be used to detect
an overtemperature fault using an NTC thermistor. A pull up
current source, IFault(OTP) (typically 45.0 mA), generates a
Figure 23. Fault Pin Internal Schematic
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28
NCP1342
• The controller latches off (version A) or
• Enters a safe, low duty−ratio auto−recovery mode
Overload Protection
The overload timer integrates the duration of the overload
fault. That is, the timer count increases while the fault is
present and reduces its count once it is removed. The
overload timer duration, tOVLD, is typically 160 ms. When
the overload timer expires, the controller detects an overload
condition does one of the following:
(version B).
Figure 24 shows the overload circuit schematic, while
Figure 25 and Figure 26 show operating waveforms for
latched and auto−recovery overload conditions.
V FB(open)
R FB
PWM
t OVLD
OCP + OPP
Count Down
KFB
FB
t LEB1
CS
VOPP
Count Up
V ILIM1
DRV Off
AOCP
Abnormal OCP
t LEB2
Count 4
V ILIM2
Figure 24. Overload Circuitry
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29
ZCD/OPP
NCP1342
Fault
Latch
Event
Latch
time
V CC
V CC(on)
V CC(off)
time
DRV
time
I HV
Istart2
IHV(off)
time
Figure 25. Latched Overload Operation
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30
NCP1342
Output Load
Fault
disappears
Overcurrent
applied
Max Load
time
Fault Flag
Fault
timer
starts
time
VCC
VCC(on)
VCC(off)
Restarts
At VCC(on)
(new burst
cycle if Fault
still present)
DRV
time
Controller
stops
time
Fault timer
160 ms
tOVLD
trestart
Figure 26. Auto−Recovery Overload Operation
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31
tdelay(start)
time
NCP1342
Abnormal Overcurrent Protection (AOCP)
core. Due to the valley timeout feature of the controller, the
flux level will quickly walk up until the core saturates. This
can cause excessive stress on the primary MOSFET and
secondary diode. This is not a problem for the NCP1342,
however, because the valley timeout timer is disabled while
the ZCD Pin voltage is above the arming threshold. Since the
leakage energy is high enough to arm the ZCD trigger, the
timeout timer is disabled and the next drive pulse is delayed
until demagnetization occurs.
Under some severe fault conditions, like a winding
short−circuit, the switch current can increase very rapidly
during the on−time. The current sense signal significantly
exceeds VILIM1, but because the current sense signal is
blanked by the LEB circuit during the switch turn−on, the
power switch current can become huge and cause severe
system damage.
The NCP1342 protects against this fault by adding an
additional comparator for Abnormal Overcurrent Fault
detection. The current sense signal is blanked with a shorter
LEB duration, tLEB2, typically 125 ns, before applying it to
the Abnormal Overcurrent Fault Comparator. The voltage
threshold of the comparator, VILIM2, typically 1.2 V, is set
50% higher than VILIM1, to avoid interference with normal
operation. Four consecutive Abnormal Overcurrent faults
cause the controller to enter latch mode. The count to 4
provides noise immunity during surge testing. The counter
is reset each time a DRV pulse occurs without activating the
Fault Overcurrent Comparator.
VCC Overvoltage Protection
An additional comparator on the VCC pin monitors the
VCC voltage. If VCC exceeds VCC(OVP), the gate drive is
disabled and the NCP1342 follows the operation of a
latching fault (see Figure 17).
Thermal Shutdown
An internal thermal shutdown circuit monitors the
junction temperature of the controller. The controller is
disabled if the junction temperature exceeds the thermal
shutdown threshold, TSHDN (typically 140°C). When a
thermal shutdown fault is detected, the controller enters a
non−latching fault mode as depicted in Figure 18. The
controller restarts at the next VCC(on) once the junction
temperature drops below below TSHDN by the thermal
shutdown hysteresis, TSHDN(HYS), typically 40°C.
The thermal shutdown is also cleared if VCC drops below
VCC(reset), or a line removal fault is detected. A new power
up sequence commences at the next VCC(on) once all the
faults are removed.
Current Sense Pin Failure Protection
A 1 mA (typically) pull−up current source, ICS, pulls up the
CS pin to disable the controller if the pin is left open.
Additionally, the maximum on−time, ton(MAX) (32 ms
typically), prevents the MOSFET from staying on
permanently if the CS Pin is shorted to GND.
Output Short Circuit Protection
During an output short−circuit, there is not enough
voltage across the secondary winding to demagnetize the
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32
NCP1342
TYPICAL CHARACTERISTICS
17.14
9
17.12
8.99
17.1
8.98
17.06
VCC(off) (V)
VCC(on) (V)
17.08
17.04
17.02
17
8.96
8.95
16.98
8.94
16.96
16.94
−40
8.97
−20
0
20
40
60
80
100
120
8.93
−40
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 27. VCC(on) vs. Temperature
Figure 28. VCC(off) vs. Temperature
0.6
120
5
4.5
0.5
4
3.5
Istart2 (mA)
0.4
Istart1 (mA)
−20
0.3
0.2
3
2.5
2
1.5
1
0.1
0.5
0
−40
−20
0
20
40
60
80
100
0
−40
120
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 29. Istart1 vs. Temperature
Figure 30. Istart2 vs. Temperature
120
9
8
6
7
IHV(off2) (mA)
5
IHV(off1) (mA)
0
TJ, JUNCTION TEMPERATURE (°C)
7
4
3
2
6
5
4
3
2
1
0
−40
−20
1
−20
0
20
40
60
80
100
120
0
−40
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 31. IHV(off1) vs. Temperature
Figure 32. IHV(off2) vs. Temperature
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33
120
NCP1342
TYPICAL CHARACTERISTICS
0.126
0.255
0.124
0.250
0.122
0.245
0.118
ICC2 (mA)
ICC1 (mA)
0.120
0.116
0.114
0.112
0.235
0.230
0.110
0.225
0.108
0.106
−40
0.240
−20
0
20
40
60
80
100
0.220
−40
120
−20
0
20
40
60
80
100
120
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 33. ICC1 vs. Temperature
Figure 34. ICC2 vs. Temperature
1.075
28.35
1.070
28.3
1.065
VCC(OVP) (V)
ICC3 (mA)
1.060
1.055
1.050
1.045
1.040
28.25
28.2
28.15
1.035
1.030
−40
−20
0
20
40
60
80
100
28.1
−40
120
20
40
60
80
TJ, JUNCTION TEMPERATURE (°C)
Figure 35. ICC3 vs. Temperature
Figure 36. VCC(OVP) vs. Temperature
19.8
112.6
112.4
19.4
112.2
19.2
19
VBO(start) (V)
ICC(discharge) (mA)
0
TJ, JUNCTION TEMPERATURE (°C)
19.6
18.8
18.6
18.4
18.2
112
111.8
111.6
111.4
111.2
18
110
17.8
17.6
−40
−20
−20
0
20
40
60
80
100
120
110.8
−40
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 37. ICC(discharge) vs. Temperature
Figure 38. VBO(start) vs. Temperature
www.onsemi.com
34
120
NCP1342
TYPICAL CHARACTERISTICS
98.2
90
80
97.8
97.6
97.4
−20
0
20
40
60
80
100
30
0
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 40. tDRV(rise) vs. Temperature
120
111.8
111.6
CDRV = 1 nF
111.4
fMAX1 (kHz)
30
25
20
15
10
111.2
111
110.8
110.6
CDRV = 100 pF
110.4
5
−20
0
20
40
60
80
100
110.2
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 41. tDRV(fall) vs. Temperature
Figure 42. fMAX1 vs. Temperature
367
120
73.45
73.4
366
73.35
365.5
73.3
fMAX3 (kHz)
366.5
365
364.5
364
73.25
73.2
73.15
363.5
73.1
363
73.05
362.5
−40
CDRV = 100 pF
TJ, JUNCTION TEMPERATURE (°C)
35
tDRV(fall) (ns)
40
Figure 39. VBO(stop) vs. Temperature
40
fMAX2 (kHz)
50
10
45
0
−40
60
20
97.2
97
−40
CDRV = 1 nF
70
tDRV(rise) (ns)
VBO(stop) (V)
98
−20
0
20
40
60
80
100
120
73
−40
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 43. fMAX2 vs. Temperature
Figure 44. fMAX3 vs. Temperature
www.onsemi.com
35
120
NCP1342
TYPICAL CHARACTERISTICS
32.5
63.6
32.4
63.5
VZCD(trig) (mV)
ton(MAX) (ms)
32.3
32.2
32.1
32
63.4
63.3
63.2
31.9
63.1
31.8
31.7
−40
−20
0
20
40
60
80
100
63
−40
120
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 46. VZCD(trig) vs. Temperature
120
12.95
12.9
25.55
VZCD(MAX) (V)
VZCD(HYS) (mV)
20
TJ, JUNCTION TEMPERATURE (°C)
25.6
25.5
25.45
12.85
12.8
12.75
25.4
−20
0
20
40
60
80
100
12.7
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 47. VZCD(HYS) vs. Temperature
Figure 48. VZCD(MAX) vs. Temperature
0
120
198.8
−0.1
198.6
−0.2
−0.3
Vfreeze (mV)
VZCD(MIN) (V)
0
Figure 45. ton(MAX) vs. Temperature
25.65
25.35
−40
−20
−0.4
−0.5
−0.6
−0.7
198.4
198.2
198
197.8
−0.8
−0.9
−40
−20
0
20
40
60
80
100
120
197.6
−40
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 49. VZCD(MIN) vs. Temperature
Figure 50. Vfreeze vs. Temperature
www.onsemi.com
36
120
NCP1342
TYPICAL CHARACTERISTICS
1.31
104.2
1.308
104
103.8
1.304
Vjitter (mV)
fjitter (kHz)
1.306
1.302
1.3
103.2
1.296
103
−40
−20
0
20
40
60
80
100
102.8
−40
120
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 52. Vjitter vs. Temperature
402.5
3.09
402
3.08
401.5
3.07
3.06
3.05
120
401
400.5
400
399.5
3.04
−20
0
20
40
60
80
100
399
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 53. VFault(OVP) vs. Temperature
Figure 54. VFault(OTP_in) vs. Temperature
920
45.1
918
45
120
44.9
916
IOTP (mA)
914
912
910
44.8
44.7
44.6
44.5
908
906
−40
0
TJ, JUNCTION TEMPERATURE (°C)
3.1
3.03
−40
−20
Figure 51. fjitter vs. Temperature
VFault(OTP_in) (mV)
VFault(OVP) (V)
103.4
1.298
1.294
VFault(OTP_out) (mV)
103.6
44.4
−20
0
20
40
60
80
100
120
44.3
−40
−20
0
20
40
60
80
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 55. VFault(OTP_out) vs. Temperature
Figure 56. IOTP vs. Temperature
www.onsemi.com
37
100
120
NCP1342
TYPICAL CHARACTERISTICS
1.731
1.55
1.545
1.54
RFault(clamp) (kW)
VFault(clamp) (V)
1.73
1.729
1.728
1.535
1.53
1.525
1.52
1.515
1.51
1.727
1.505
1.726
−40
1.495
−40
1.5
−20
0
20
40
60
80
100
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 57. VFault(clamp) vs. Temperature
Figure 58. RFault(clamp) vs. Temperature
24.5
120
1.39
24.45
1.385
24.4
24.3
tquiet (ms)
fMIN (kHz)
24.35
24.25
24.2
1.38
1.375
24.15
1.37
24.1
24.05
−20
0
20
40
60
80
100
1.365
−40
120
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 59. fMIN vs. Temperature
Figure 60. tquiet vs. Temperature
840
0.8
830
0.799
120
0.798
820
810
800
0.797
0.796
0.795
790
0.794
780
−40
−20
TJ, JUNCTION TEMPERATURE (°C)
VILIM1 (V)
tZCD(blank) (ns)
24
−40
−20
0
20
40
60
80
100
120
0.793
−40
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 61. tZCD(blank) vs. Temperature
Figure 62. VILIM1 vs. Temperature
www.onsemi.com
38
120
NCP1342
40
1.201
39.9
1.2
39.8
1.199
39.7
tDT(MAX) (ms)
1.202
1.198
1.197
1.196
39.6
39.5
39.4
1.195
39.3
1.194
39.2
1.193
−40
−20
0
20
40
60
80
100
120
39.1
−40
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 63. VILIM2 vs. Temperature
Figure 64. tDT(MAX) vs. Temperature
399
398.5
398
Vskip (mV)
VILIM2 (V)
TYPICAL CHARACTERISTICS
397.5
397
396.5
396
−40
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 65. Vskip vs. Temperature
www.onsemi.com
39
120
120
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−9 NB
CASE 751BP
ISSUE A
9
1
SCALE 1:1
DATE 21 NOV 2011
2X
0.10 C A-B
D
D
A
0.20 C
2X
4 TIPS
F
0.10 C A-B
10
6
H
E
1
5
0.20 C
9X
B
5 TIPS
L2
b
0.25
A3
L
DETAIL A
M
C
SEATING
PLANE
C A-B D
TOP VIEW
9X
h
0.10 C
0.10 C
X 45 _
M
A
e
A1
C
SIDE VIEW
SEATING
PLANE
DETAIL A
END VIEW
1
6.50
9X
1.18
1
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON52301E
SOIC−9 NB
MILLIMETERS
MIN
MAX
1.25
1.75
0.10
0.25
0.17
0.25
0.31
0.51
4.80
5.00
3.80
4.00
1.00 BSC
5.80
6.20
0.37 REF
0.40
1.27
0.25 BSC
0_
8_
9
1.00
PITCH
0.58
DIM
A
A1
A3
b
D
E
e
H
h
L
L2
M
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
9X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.10mm TOTAL IN EXCESS OF ’b’
AT MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15mm
PER SIDE. DIMENSIONS D AND E ARE DETERMINED AT DATUM F.
5. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM F.
6. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
XXXXX
ALYWX
G
XXXXX = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking. Pb−Free indicator, “G”, may
or not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
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and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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onsemi:
NCP1342DADBDD1R2G NCP1342ANDAAD1R2G NCP1342AMDCCDR2G NCP1342AMDCDAD1R2G
NCP1342AMAACD1R2G NCP1342BMDCDAD1R2G NCP1342ANACECD1R2G NCP1342BMDCDDD1R2G
NCP1342ANACED1R2G NCP1342ANDBDD1R2G NCP1342AMDCDD1R2G NCP1342ANACCED1R2G
NCP1342AMDADGD1R2G NCP1342AMDCDHD1R2G NCP1342BKDCDAD1R2G NCP1342ENACEFD1R2G
NCP1342BMDCDD1R2G NCP1342ENDCEAD1R2G
