CMOS Voltage Regulator,
Very Low Dropout Bias Rail,
500 mA
NCP135
The NCP135 is a 500 mA VLDO equipped with NMOS pass
transistor and a separate bias supply voltage (VBIAS). The device
provides very stable, accurate output voltage with low noise suitable
for space constrained, noise sensitive applications. In order to
optimize performance for battery operated portable applications, the
NCP135 features low IQ consumption. The NCP135 is offered in
WDFN6 2 mm x 2 mm package.
Features
•
•
•
•
•
•
•
•
•
•
•
Input Voltage Range: 0.4 V to 5.5 V
Bias Voltage Range: 2.5 V to 5.5 V
Fixed Output Voltage of 0.4 V and 0.75 V
±1% Accuracy over Temperature, 0.5% VOUT @ 25°C
Ultra−Low Dropout: Typ. 53 mV at 500 mA
Very Low Bias Input Current of Typ. 35 mA
Logic Level Enable Input for ON/OFF Control
Output Active Discharge Option Available
Stable with a 10 mF Ceramic Capacitor
Available in WDFN6 2 mm x 2 mm, 0.65 mm pitch Package
This is a Pb−Free Device
Typical Applications
• Battery−powered Equipment
• Smartphones, Tablets
• Cameras, DVRs, STB and Camcorders
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T
MARKING
DIAGRAM
1
XX M
WDFN6
CASE 511BR
XX = Specific Device Code
M = Date Code
PIN CONNECTIONS
IN
1
GND
2
BIAS
3
Thermal
Pad
6
OUT
5
SNS
4
EN
(Top View)
ORDERING INFORMATION
VIN
See detailed ordering, marking and shipping information on
page 10 of this data sheet.
NCP135
4.7 mF
IN
0.1 mF
EN
VOUT
0.4 V, 0.75 V up to 500 mA
OUT
BIAS
VBIAS
SNS
10 mF
GND
VEN
Figure 1. Typical Application Schematic
© Semiconductor Components Industries, LLC, 2017
September, 2020 − Rev. 2
1
Publication Order Number:
NCP135/D
NCP135
CURRENT
LIMIT
IN
EN
BIAS
OUT
ENABLE
BLOCK
150 W
*Active
DISCHARGE
UVLO
VOLTAGE
REFERENCE
+
−
THERMAL
LIMIT
SNS
GND
*Active output discharge function is present only in NCP135A option devices.
Figure 2. Simplified Schematic Block Diagram
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2
NCP135
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
1
VIN
Input Voltage Supply pin
Description
2
GND
Ground pin
3
VBIAS
4
EN
5
SNS
6
VOUT
Pad
Pad
Bias voltage supply for internal control circuits. This pin is monitored by internal Under-Voltage
Lockout Circuit.
Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into
shutdown mode.
Output voltage Sensing Input. Connect to Output voltage node on the PCB.
Regulated Output Voltage pin
Should be soldered to the ground plane for increased thermal performance.
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VIN
−0.3 to 6
V
VOUT
−0.3 to (VIN+0.3) ≤ 6
V
VEN, VBIAS, VSNS
−0.3 to 6
V
tSC
unlimited
s
Input Voltage (Note 1)
Output Voltage
Chip Enable, Bias and SNS Input
Output Short Circuit Duration
Maximum Junction Temperature
TJ
125
°C
TSTG
−55 to 150
°C
ESD Capability, Human Body Model (Note 2)
ESDHBM
2000
V
ESD Capability, Machine Model (Note 2)
ESDMM
200
V
Storage Temperature
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection (except OUT pin) and is tested by the following methods:
ESD Human Body Model tested per EIA/JESD22−A114
ESD Machine Model tested per EIA/JESD22−A115
Latchup Current Maximum Rating tested per JEDEC standard: JESD78.
THERMAL CHARACTERISTICS
Rating
Thermal Characteristics, WDFN6 2 mm x 2 mm
Thermal Resistance, Junction−to−Air (Note 3)
Symbol
Value
Unit
RqJA
97
°C/W
3. This data was derived by thermal simulations based on the JEDEC JESD51 series standards methodology. Only a single device mounted
at the center of a high K (2s2p) 3 in x 3 in multilayer board with 1−ounce internal planes and 1−ounce copper on top and bottom. Top copper
layer has a dedicated 25 sq mm copper area.
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3
NCP135
ELECTRICAL CHARACTERISTICS VOLTAGE VERSION − 0.4 V −40°C ≤ TJ ≤ 125°C; VBIAS = 2.7 V or (VOUT + 1.6 V),
whichever is greater, VIN = VOUT(NOM) + 0.3 V, IOUT = 1 mA, VEN = 1 V, CIN = 4.7 mF, COUT = 10 mF, CBIAS = 1 mF, unless otherwise noted.
Typical values are at TJ = +25°C. Min/Max values are for −40°C ≤ TJ ≤ 125°C unless otherwise noted. (Note 4)
Test Conditions
Symbol
Min
Operating Input Voltage
Range
VIN
Operating Bias Voltage
Range
VBIAS
Parameter
Typ
Max
Unit
VOUT +
VDO
5.5
V
(VOUT +
1.50) ≥ 2.5
5.5
V
Undervoltage Lock−out
VBIAS Rising
Hysteresis
UVLO
1.6
0.2
Nominal Output Voltage
TJ = +25°C
VOUT(NOM)
0.400
V
VOUT
±0.5
%
Output Voltage Accuracy
VOUT
Output Voltage Accuracy
−40°C ≤ TJ ≤ 125°C, VOUT(NOM) + 0.3 V ≤ VIN
≤ VOUT(NOM) + 1.0 V, 2.7 V or (VOUT(NOM) +
1.6 V), whichever is greater < VBIAS < 5.5 V,
1 mA < IOUT < 500 mA
VIN Line Regulation
VOUT(NOM) + 0.3 V ≤ VIN ≤ 5.0 V
LineReg
0.01
%/V
VBIAS Line Regulation
2.7 V or (VOUT(NOM) + 1.6 V), whichever is
greater < VBIAS < 5.5 V
LineReg
0.01
%/V
Load Regulation
IOUT = 1 mA to 500 mA
LoadReg
0.5
mV
VIN Dropout Voltage
IOUT = 500 mA (Note 5)
VDO
53
100
mV
Output Current Limit
VOUT = 90% VOUT(NOM)
ICL
SNS Pin Operating
Current
−1.0
V
600
+1.0
%
820
1200
mA
ISNS
0.01
0.5
mA
IBIASQ
35
55
mA
Bias Pin Quiescent
Current
VBIAS = 2.7 V, IOUT = 0 mA
Bias Pin Disable Current
VEN ≤ 0.4 V
IBIAS(DIS)
0.2
1
mA
Vinput Pin Disable
Current
VEN ≤ 0.4 V
IVIN(DIS)
0.01
1
mA
EN Pin Threshold Voltage EN Input Voltage “H”
VEN(H)
EN Input Voltage “L”
VEN(L)
V
0.9
0.4
EN Pull Down Current
VEN = 5.5 V
IEN
0.3
Turn−On Time
From assertion of VEN to VOUT =
98% VOUT(NOM)
tON
150
ms
Power Supply Rejection
Ratio
VIN to VOUT, f = 1 kHz, IOUT = 10 mA,
VIN ≥ VOUT +0.5 V
PSRR(VIN)
73
dB
VBIAS to VOUT, f = 1 kHz, IOUT = 10 mA,
VIN ≥ VOUT +0.5 V
PSRR(VBIAS)
90
dB
Output Noise Voltage
VIN = VOUT +0.5 V, f = 10 Hz to 100 kHz
VN
28.7
mVRMS
Thermal Shutdown
Threshold
Temperature increasing
160
°C
Temperature decreasing
140
Output Discharge
Pull−Down
VEN ≤ 0.4 V, VOUT = 0.4 V, NCP135A options
only
RDISCH
150
1
mA
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Performance guaranteed over the indicated operating temperature range by design and/or characterization. Production tested at TA = 25°C.
Low duty cycle pulse techniques are used during the testing to maintain the junction temperature as close to ambient as possible.
5. Dropout voltage is characterized when VOUT falls 3% below VOUT(NOM).
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4
NCP135
ELECTRICAL CHARACTERISTICS VOLTAGE VERSION − 0.75 V −40°C ≤ TJ ≤ 125°C; VBIAS = 2.7 V or (VOUT + 1.6 V),
whichever is greater, VIN = VOUT(NOM) + 0.3 V, IOUT = 1 mA, VEN = 1 V, CIN = 4.7 mF, COUT = 10 mF, CBIAS = 1 mF, unless otherwise noted.
Typical values are at TJ = +25°C. Min/Max values are for −40°C ≤ TJ ≤ 125°C unless otherwise noted. (Note 6)
Test Conditions
Symbol
Min
Operating Input Voltage
Range
VIN
Operating Bias Voltage
Range
VBIAS
Parameter
Typ
Max
Unit
VOUT +
VDO
5.5
V
(VOUT +
1.50) ≥ 2.5
5.5
V
Undervoltage Lock−out
VBIAS Rising
Hysteresis
UVLO
1.6
0.2
Nominal Output Voltage
TJ = +25°C
VOUT(NOM)
0.750
V
VOUT
±0.5
%
Output Voltage Accuracy
VOUT
Output Voltage Accuracy
−40°C ≤ TJ ≤ 125°C, VOUT(NOM) + 0.3 V ≤ VIN
≤ VOUT(NOM) + 1.0 V, 2.7 V or (VOUT(NOM) +
1.6 V), whichever is greater < VBIAS < 5.5 V,
1 mA < IOUT < 500 mA
VIN Line Regulation
VOUT(NOM) + 0.3 V ≤ VIN ≤ 5.0 V
LineReg
0.01
%/V
VBIAS Line Regulation
2.7 V or (VOUT(NOM) + 1.6 V), whichever is
greater < VBIAS < 5.5 V
LineReg
0.01
%/V
Load Regulation
IOUT = 1 mA to 500 mA
LoadReg
0.5
mV
VIN Dropout Voltage
IOUT = 500 mA (Note 7)
VDO
52
100
mV
Output Current Limit
VOUT = 90% VOUT(NOM)
ICL
SNS Pin Operating
Current
−1.0
V
600
+1.0
%
820
1200
mA
ISNS
0.01
0.5
mA
IBIASQ
35
55
mA
Bias Pin Quiescent
Current
VBIAS = 2.7 V, IOUT = 0 mA
Bias Pin Disable Current
VEN ≤ 0.4 V
IBIAS(DIS)
0.2
1
mA
Vinput Pin Disable
Current
VEN ≤ 0.4 V
IVIN(DIS)
0.01
1
mA
EN Pin Threshold Voltage EN Input Voltage “H”
VEN(H)
EN Input Voltage “L”
VEN(L)
V
0.9
0.4
EN Pull Down Current
VEN = 5.5 V
IEN
0.3
Turn−On Time
From assertion of VEN to VOUT =
98% VOUT(NOM)
tON
198
ms
Power Supply Rejection
Ratio
VIN to VOUT, f = 1 kHz, IOUT = 10 mA,
VIN ≥ VOUT +0.5 V
PSRR(VIN)
73
dB
VBIAS to VOUT, f = 1 kHz, IOUT = 10 mA,
VIN ≥ VOUT +0.5 V
PSRR(VBIAS)
100
dB
Output Noise Voltage
VIN = VOUT +0.5 V, f = 10 Hz to 100 kHz
VN
35.3
mVRMS
Thermal Shutdown
Threshold
Temperature increasing
160
°C
Temperature decreasing
140
Output Discharge
Pull−Down
VEN ≤ 0.4 V, VOUT = 0.4 V, NCP135A options
only
RDISCH
150
1
mA
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Performance guaranteed over the indicated operating temperature range by design and/or characterization. Production tested at TA = 25°C.
Low duty cycle pulse techniques are used during the testing to maintain the junction temperature as close to ambient as possible.
7. Dropout voltage is characterized when VOUT falls 3% below VOUT(NOM).
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NCP135
TYPICAL CHARACTERISTICS
90
80
+125°C
70
+85°C
60
+25°C
50
40
30
−40°C
20
10
0
0
100
200
400
300
25
VDO (VIN − VOUT) DROPOUT VOLTAGE (mV)
100
500
IOUT, OUTPUT CURRENT (mA)
IOUT = 100 mA
20
+125°C
15
60
50
40
30
20
+25°C
10
0
1.5
2.0
2.5
−40°C
3.0
3.5
4.0
4.5
5.0
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VBIAS − VOUT (V)
5.5
100
90
IOUT = 500 mA
+125°C
80
+85°C
70
60
50
40
30
+25°C
20
−40°C
10
0
1.5
VBIAS − VOUT (V)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VBIAS − VOUT (V)
50 mV/div
Figure 6. VIN Dropout Voltage vs. (VBIAS −
VOUT) and Temperature TJ
VOUT
200 mA/div
50 mV/div
−40°C
5
Figure 5. VIN Dropout Voltage vs. (VBIAS −
VOUT) and Temperature TJ
200 mA/div
+25°C
Figure 4. VIN Dropout Voltage vs. (VBIAS −
VOUT) and Temperature TJ
IOUT = 300 mA
+125°C
+85°C
+85°C
10
Figure 3. VIN Dropout Voltage vs. IOUT and
Temperature TJ
VDO (VIN − VOUT) DROPOUT VOLTAGE (mV)
VDO (VIN − VOUT) DROPOUT VOLTAGE (mV)
VDO (VIN − VOUT) DROPOUT VOLTAGE (mV)
At TJ = +25°C, VIN = VOUT(NOM) + 0.3 V, VBIAS = 2.7 V, VEN = 1.0 V, VOUT(NOM) = 0.4 V, IOUT = 500 mA,
CIN = 1 mF, CBIAS = 0.1 mF, and COUT = 10 mF (effective capacitance value), unless otherwise noted.
tR = tF = 1 ms
IOUT
VOUT
tR = tF = 1 ms
IOUT
50 ms/div
50 ms/div
Figure 7. Load Transient Response,
IOUT = 50 mA to 500 mA, COUT = 10 mF
Figure 8. Load Transient Response,
IOUT = 50 mA to 500 mA, COUT = 22 mF
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5.5
NCP135
TYPICAL CHARACTERISTICS
50 mV/div
VOUT
200 mA/div
VOUT
tR = tF = 1 ms
IOUT
tR = tF = 1 ms
IOUT
500 ms/div
Figure 10. Load Transient Response,
IOUT = 1 mA to 500 mA, COUT = 22 mF
10 mV/div
500 ms/div
Figure 9. Load Transient Response,
IOUT = 1 mA to 500 mA, COUT = 10 mF
VOUT
VOUT
tR = tF = 1 ms
10 mA/div
tR = tF = 1 ms
IOUT
IOUT
500 ms/div
500 ms/div
Figure 11. Load Transient Response,
IOUT = 1 mA to 20 mA, COUT = 10 mF
Figure 12. Load Transient Response,
IOUT = 1 mA to 20 mA, COUT = 22 mF
500 mV/div
500 mV/div
10 mA/div
10 mV/div
200 mA/div
50 mV/div
At TJ = +25°C, VIN = VOUT(NOM) + 0.3 V, VBIAS = 2.7 V, VEN = 1.0 V, VOUT(NOM) = 0.4 V, IOUT = 500 mA,
CIN = 1 mF, CBIAS = 0.1 mF, and COUT = 10 mF (effective capacitance value), unless otherwise noted.
VENABLE
VENABLE
VOUT
IOUT
200 mA/div
100 mV/div
100 mV/div
VOUT
100 ms/div
Figure 13. Enable Transient Response,
IOUT = 0 mA, COUT = 10 mF
100 ms/div
Figure 14. Enable Transient Response, Output
Resistive Load 500 mA, COUT = 22 mF
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NCP135
TYPICAL CHARACTERISTICS
20 mV/div
20 mV/div
At TJ = +25°C, VIN = VOUT(NOM) + 0.3 V, VBIAS = 2.7 V, VEN = 1.0 V, VOUT(NOM) = 0.4 V, IOUT = 500 mA,
CIN = 1 mF, CBIAS = 0.1 mF, and COUT = 10 mF (effective capacitance value), unless otherwise noted.
VOUT
VOUT
500 mV/div
VIN
tR = tF = 5 ms
VIN
50 ms/div
50 ms/div
Figure 15. VIN Line Transient Response,
VIN = 0.7 V to 1.7 V, IOUT = 100 mA, CIN = 0,
COUT = 10 mF
Figure 16. VIN Line Transient Response,
VIN = 0.7 V to 1.7 V, IOUT = 100 mA, CIN = 0,
COUT = 22 mF
−120
VIN = 0.9 V, VBIAS = 2.7 V, COUT = MLCC 1206
−110
−100
10 mA, COUT = 10 mF
−90
10 mA, COUT = 22 mF
−80
−70
−60
−50
−40
−30
−20
100 mA, COUT = 10 mF
−10
100 mA, COUT = 22 mF
0
10
100
1k
10k
100k
1M
10M
10
PSSR (dB)
PSSR (dB)
500 mV/div
tR = tF = 5 ms
−120
10 mA, COUT = 22 mF
−110
10 mA, COUT = 10 mF
−100
−90
−80
−70
−60
−50
−40
−30
100 mA, COUT = 10 mF
−20
100 mA, COUT = 22 mF
−10
0
10 VIN = 0.9 V, VBIAS = 2.7 V, COUT = MLCC 1206
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 17. VIN Power Supply Rejection Ratio
vs. Frequency
Figure 18. VBIAS Power Supply Rejection Ratio
vs. Frequency
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NCP135
TYPICAL CHARACTERISTICS
At TJ = +25°C, VIN = VOUT(NOM) + 0.3 V, VBIAS = 2.7 V, VEN = 1.0 V, VOUT(NOM) = 0.4 V, IOUT = 500 mA,
CIN = 1 mF, CBIAS = 0.1 mF, and COUT = 10 mF (effective capacitance value), unless otherwise noted.
OUTPUT NOISE (nV/√Hz)
10000
500 mA 22 mF
100 mA 22 mF
10 mA 22 mF
1 mA 22 mF
1 mA 10 mF
1000
RMS Output Noise Voltage (mV)
IOUT
COUT
10 Hz − 100 kHz
1 mA
10 mF
28.67
27.54
1 mA
22 mF
28.19
27.28
10 mA
22 mF
36.23
35.49
22 mF
45.44
44.87
22 mF
54.54
54.04
100
100 mA
10
1
10
500 mA
100 Hz − 100 kHz
VIN = 0.9 V, VBIAS = 2.7 V, COUT = MLCC 1206
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
Figure 19. Output Voltage Noise Spectral
Density at NCP135AMT040TBG
OUTPUT NOISE (nV/√Hz)
10000
1000
500 mA 22 mF
100 mA 22 mF
10 mA 22 mF
1 mA 22 mF
1 mA 10 mF
RMS Output Noise Voltage (mV)
IOUT
COUT
10 Hz − 100 kHz
10 mF
35.34
34.22
22 mF
33.39
32.22
10 mA
22 mF
41.85
40.91
100 mA
22 mF
51.70
50.98
500 mA
22 mF
59.78
59.16
1 mA
100
1 mA
10
VIN = 1.05 V, VBIAS = 2.7 V, COUT = MLCC 1206
1
1M
10
100
1k
10k
100k
FREQUENCY (Hz)
10M
Figure 20. Output Voltage Noise Spectral
Density at NCP135AMT075TBG
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9
100 Hz − 100 kHz
NCP135
APPLICATIONS INFORMATION
copper layer, not through vias having not negligible
impedance.
When using small ceramic capacitor, their capacitance is
not constant but varies with applied DC biasing voltage,
temperature and tolerance. The effective capacitance can be
much lower than their nominal capacitance value, most
importantly in negative temperatures and higher LDO
output voltages. That is why the recommended Output
capacitor capacitance value is specified as Effective value in
the specific application conditions.
The NCP135 dual−rail very low dropout voltage regulator
is using NMOS pass transistor for output voltage regulation
from VIN voltage. All the low current internal control
circuitry is powered from the VBIAS voltage.
The use of an NMOS pass transistor offers several
advantages in applications. Unlike PMOS topology devices,
the output capacitor has reduced impact on loop stability.
VIN to VOUT operating voltage difference can be very low
compared with standard PMOS regulators in very low Vin
applications.
When enabled from Enable (EN) input, the NCP135
offers smooth monotonic start-up. The controlled voltage
rising limits the inrush current.
The Enable (EN) input is equipped with internal
hysteresis.
Enable Operation
The enable pin will turn the regulator on or off. The
threshold limits are covered in the electrical characteristics
table in this data sheet. If the enable function is not to be used
then the pin should be connected to VIN or VBIAS.
Dropout Voltage
Current Limitation
The VIN Dropout voltage is the voltage difference (VIN –
VOUT) when VOUT starts to decrease by percent specified in
the Electrical Characteristics table with the VIN voltage
decreasing. VBIAS is high enough; specific value is
published in the Electrical Characteristics table.
The internal Current Limitation circuitry allows the
device to supply the full nominal current and surges but
protects the device against Current Overload or Short.
Thermal Protection
Internal thermal shutdown (TSD) circuitry is provided to
protect the integrated circuit in the event that the maximum
junction temperature is exceeded. When TSD activated, the
regulator output turns off. When cooling down under the low
temperature threshold, device output is activated again. This
TSD feature is provided to prevent failures from accidental
overheating.
Activation of the thermal protection circuit indicates
excessive power dissipation or inadequate heatsinking. For
reliable operation, junction temperature should be limited to
+125°C maximum.
Input and Output Capacitors
The device is designed to be stable for ceramic output
capacitors with Effective capacitance in the range from
10 mF to 22 mF. The device is also stable with multiple
capacitors in parallel, having the total effective capacitance
in the specified range.
In applications where no low input supplies impedance
available (PCB inductance in VIN and/or VBIAS inputs as
example), the recommended CIN = 1 mF and CBIAS = 0.1 mF
or greater. Ceramic capacitors are recommended. For the
best performance all the capacitors should be connected to
the NCP135 respective pins directly in the device PCB
ORDERING INFORMATION
Device
Marking
Option
NCP135AMT040TBG
KA
Output Active Discharge
NCP135BMT040TBG
KC
Non−Active Discharge
NCP135AMT075TBG
KG
Output Active Discharge
Package
Shipping†
WDFN6
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
To order other package and voltage variants, please contact your ON Semiconductor sales representative
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10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFN6 2x2, 0.65P
CASE 511BR
ISSUE C
DATE 01 DEC 2021
GENERIC
MARKING DIAGRAM*
1
XX M
XX = Specific Device Code
M = Date Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON55829E
WDFN6 2X2, 0.65P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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