LDO Regulator - Very Low
Dropout, CMOS, Bias Rail
700 mA
NCP136
The NCP136 is a 700 mA VLDO equipped with NMOS pass
transistor and a separate bias supply voltage (VBIAS). The device
provides very stable, accurate output voltage with low noise suitable
for space constrained, noise sensitive applications. In order to
optimize performance for battery operated portable applications, the
NCP136 features low IQ consumption. The WLCSP6 1.4 mm x
0.8 mm Chip Scale package is optimized for use in space constrained
applications.
Features
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Input Voltage Range: VOUT to 5.5 V
Bias Voltage Range: 2.5 V to 5.5 V
Fixed or Adjustable Voltage Version Available
Output Voltage Range: 0.4 V to 1.8 V (Fixed)
±1% Accuracy over Temperature, 0.5% VOUT @ 25°C
Ultra−Low Dropout: Typ. 40 mV at 700 mA
Very Low Bias Input Current of Typ. 80 mA
Very Low Bias Input Current in Disable Mode: Typ. 0.5 mA
Logic Level Enable Input for ON/OFF Control
Output Active Discharge Option Available
Stable with a 10 mF Ceramic Capacitor
Available in WLCSP6 − 1.4 mm x 0.8 mm, 0.4 mm pitch Package
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
• Battery−powered Equipment
• Smartphones, Tablets
• Cameras, DVRs, STB and Camcorders
WLCSP6, 1.4x0.8x0.37
CASE 567YU
WLCSP6, 1.4x0.8x0.33
CASE 567XK
MARKING DIAGRAM
XXM
XX = Specific Device Code
M = Month Code
PIN CONNECTIONS
1
2
A
OUT
IN
B
SNS/ADJ
EN
C
GND
BIAS
VBIAS
CBIAS
1 mF
BIAS
VIN
CIN
4.7 mF
VOUT
OUT
IN NCP136FIX
SNS
EN
GND
Top View
COUT
10 mF
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 12 of this data sheet.
OFF ON
Figure 1. Typical Application Schematic − Fixed Voltage Version
© Semiconductor Components Industries, LLC, 2019
January, 2021 − Rev. 5
1
Publication Order Number:
NCP136/D
NCP136
VBIAS
CBIAS
1 mF
VOUT
BIAS
VIN
IN
EN
CIN
4.7 mF
OUT
NCP136
0.4 V
ADJ
R1
CFF
GND
ON
COUT
10 mF
R2
OFF
Figure 2. Typical Application Schematic − Adjustable Voltage Version
CURRENT
LIMIT
IN
EN
BIAS
OUT
ENABLE
BLOCK
150 W
*Active
DISCHARGE
UVLO
VOLTAGE
REFERENCE
+
−
THERMAL
LIMIT
SNS/ADJ
GND
*Active output discharge function is present only in NCP136A and NCP136C option devices.
Figure 3. Simplified Schematic Block Diagram
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NCP136
PIN FUNCTION DESCRIPTION
Pin No.
WLCSP6
Pin Name
A1
OUT
A2
IN
B1
SNS/ADJ
Feedback / adjustable input pin (connect this pin directly to the OUT pin or to the resistor divider)
B2
EN
Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into
shutdown mode.
C1
GND
Ground pin
C2
BIAS
Bias voltage supply for internal control circuits. This pin is monitored by internal Under-Voltage
Lockout Circuit.
Description
Regulated Output Voltage pin
Input Voltage Supply pin
ABSOLUTE MAXIMUM RATINGS
Rating
Input Voltage (Note 1)
Output Voltage
Chip Enable, Bias and SNS Input
Symbol
Value
Unit
VIN
−0.3 to 6
V
VOUT
−0.3 to (VIN+0.3) ≤ 6
V
VEN, VBIAS, VSNS/ADJ
−0.3 to 6
V
Output Short Circuit Duration
tSC
unlimited
s
Maximum Junction Temperature
TJ
150
°C
TSTG
−55 to 150
°C
ESD Capability, Human Body Model (Note 2)
ESDHBM
2000
V
ESD Capability, Machine Model (Note 2)
ESDMM
200
V
Storage Temperature
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection (except OUT pin) and is tested by the following methods:
ESD Human Body Model tested per EIA/JESD22−A114
ESD Machine Model tested per EIA/JESD22−A115
Latchup Current Maximum Rating tested per JEDEC standard: JESD78.
THERMAL CHARACTERISTICS
Rating
Thermal Characteristics, WLCSP6 1.4 mm x 0.8 mm
Thermal Resistance, Junction−to−Air (Note 3)
Symbol
Value
Unit
RqJA
69
°C/W
3. This junction−to−ambient thermal resistance under natural convection was derived by thermal simulations based on the JEDEC JESD51
series standards methodology. Only a single device mounted at the center of a high_K (2s2p) 80 mm x 80 mm multilayer board with 1−ounce
internal planes and 2−ounce copper on top and bottom. Top copper layer has a dedicated 1.6 sqmm copper area.
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3
NCP136
ELECTRICAL CHARACTERISTICS −40°C ≤ TJ ≤ 85°C; VBIAS = 2.7 V or (VOUT + 1.6 V), whichever is greater,
VIN = VOUT(NOM) + 0.3 V, IOUT = 1 mA, VEN = 1 V, CIN = 4.7 mF, COUT = 10 mF, CBIAS = 1 mF, unless otherwise noted.
Typical values are at TJ = +25°C. Min/Max values are for −40°C ≤ TJ ≤ 85°C unless otherwise noted. (Note 4)
Parameter
Symbol
Min
Max
Unit
Operating Input Voltage
Range
VIN
VOUT +
VDO
5.5
V
Operating Bias Voltage
Range
VBIAS
(VOUT +
1.50) ≥ 2.5
5.5
V
Undervoltage Lock−out
Test Conditions
VBIAS Rising
Hysteresis
Output Voltage Accuracy
Typ
UVLO
1.6
0.2
V
VOUT
±0.5
%
Output Voltage Accuracy
−40°C ≤ TJ ≤ 85°C, VOUT(NOM) + 0.1 V ≤ VIN ≤ VOUT(NOM)
+ 1.0 V, 2.7 V or (VOUT(NOM) + 1.6 V), whichever is
greater < VBIAS < 5.5 V, 1 mA < IOUT < 700 mA
VOUT
VIN Line Regulation
VOUT(NOM) + 0.1 V ≤ VIN ≤ 5.0 V
LineReg
0.01
%/V
VBIAS Line Regulation
2.7 V or (VOUT(NOM) + 1.6 V), whichever is greater <
VBIAS < 5.5 V
LineReg
0.01
%/V
Load Regulation
IOUT = 1 mA to 700 mA
LoadReg
1.5
mV
VIN Dropout Voltage
IOUT = 700 mA (Note 5)
VDO
40
60
mV
VBIAS Dropout Voltage
IOUT = 700 mA, VIN = VBIAS (Notes 5, 6)
VDO
1.1
1.5
V
Output Current Limit
VOUT = 90% VOUT(NOM)
ICL
SNS/ADJ Pin Operating
Current
mA
0.5
mA
IBIASQ
70
110
mA
0.5
1
mA
0.5
1
mA
Bias Pin Disable Current
VEN ≤ 0.4 V
IBIAS(DIS)
Input Pin Disable Current
VEN ≤ 0.4 V
IVIN(DIS)
EN Pin Threshold Voltage
EN Input Voltage “H”
VEN(H)
EN Input Voltage “L”
VEN(L)
Power Supply Rejection
Ratio
1450 2000
%
0.1
VBIAS = 2.7 V, IOUT = 0 mA
VEN = 5.5 V
800
+1.0
ISNS
Bias Pin Quiescent
Current
EN Pull Down Current
−1.0
V
0.9
0.4
IEN
0.3
VIN to VOUT, f = 1 kHz, IOUT = 10 mA,
VIN ≥ VOUT +0.5 V, VOUT(NOM) = 1.2 V,
VBIAS = 3.0 V
PSRR(VIN)
75
dB
VBIAS to VOUT, f = 1 kHz, IOUT = 10 mA,
VIN ≥ VOUT +0.5 V, VOUT(NOM) = 1.2 V,
VBIAS = 3.0 V
PSRR(VBIAS)
80
dB
Output Noise Voltage
VIN = VOUT +0.5 V, f = 10 Hz to 100 kHz,
VOUT(NOM) = 1.2 V
VN
40
mVRMS
Thermal Shutdown
Threshold
Temperature increasing
160
°C
Output Discharge
Pull−Down
VEN ≤ 0.4 V, VOUT = 0.5 V,
NCP136A and NCP136C option
Temperature decreasing
1
mA
140
RDISCH
150
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Performance guaranteed over the indicated operating temperature range by design and/or characterization. Production tested at TA = 25°C.
Low duty cycle pulse techniques are used during the testing to maintain the junction temperature as close to ambient as possible.
5. Dropout voltage is characterized when VOUT falls 3% below VOUT(NOM).
6. For fixed output voltages below 1.5 V, VBIAS dropout does not apply due to a minimum Bias operating voltage of 2.5 V.
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NCP136
ELECTRICAL CHARACTERISTICS −40°C ≤ TJ ≤ 85°C; IOUT = 1 mA, VEN = 1 V, CIN = 4.7 μF, COUT = 10 μF, CBIAS = 1 μF.
Typical values are at TJ = +25°C. Min/Max values are for −40°C ≤ TJ ≤ 85°C unless otherwise noted. (Note 7)
Parameter
Test conditions
Symbol
Min
Typ
Max
Unit
NCP136xFCRC040T2G VBIAS = 3 V, VIN = 0.6 V
Delay time
From assertion of VEN to
output voltage increase
‘A’ option
tDELAY
73
Rise time
VOUT rise from 10% to 90% VOUT(NOM)
‘A’ option
tRISE
15
From assertion of VEN to
VOUT = 98% VOUT(NOM)
‘A’ option
tON
98
Turn−On Time
ms
NCP136xFCT080T2G & NCP136xFCRC080T2G VBIAS = 3 V, VIN = 1.0 V
Delay time
From assertion of VEN to
output voltage increase
‘A’ and ‘B’ option
tDELAY
55
Rise time
VOUT rise from 10% to 90% VOUT(NOM)
‘A’ and ‘B’ option
tRISE
17
From assertion of VEN to
VOUT = 98% VOUT(NOM)
‘A’ and ‘B’ option
tON
80
Turn−On Time
ms
NCP136xFCT088T2G VBIAS = 3 V, VIN = 1.1 V
Delay time
From assertion of VEN to
output voltage increase
‘A’ option
tDELAY
71
Rise time
VOUT rise from 10% to 90% VOUT(NOM)
‘A’ option
tRISE
16
From assertion of VEN to
VOUT = 98% VOUT(NOM)
‘A’ option
tON
97
Turn−On Time
ms
NCP136xFCT105T2G VBIAS = 3 V, VIN = 1.25 V
Delay time
From assertion of VEN to
output voltage increase
‘A’ option
tDELAY
71
Rise time
VOUT rise from 10% to 90% VOUT(NOM)
‘A’ option
tRISE
18
From assertion of VEN to
VOUT = 98% VOUT(NOM)
‘A’ option
tON
102
Turn−On Time
ms
NCP136xFCT110T2G VBIAS = 3 V, VIN = 1.3 V
Delay time
From assertion of VEN to
output voltage increase
‘A’ option
tDELAY
71
Rise time
VOUT rise from 10% to 90% VOUT(NOM)
‘A’ option
tRISE
19
From assertion of VEN to
VOUT = 98% VOUT(NOM)
‘A’ option
tON
105
‘A’ option
tON
70
Turn−On Time
ms
NCP136xFCT120T2G VBIAS = 3 V, VIN = 1.4 V
Delay time
Rise time
From assertion of VEN to
output voltage increase
‘C’ option
VOUT rise from 10% to 90% VOUT(NOM)
‘A’ option
80
tRISE
‘C’ option
Turn−On Time
From assertion of VEN to
VOUT = 98% VOUT(NOM)
‘A’ option
‘C’ option
ms
21
80
tON
108
210
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Performance guaranteed over the indicated operating temperature range by design and/or characterization. Production tested at TA = 25°C.
Low duty cycle pulse techniques are used during the testing to maintain the junction temperature as close to ambient as possible.
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NCP136
TYPICAL CHARACTERISTICS
At TJ = +25°C, VIN = VOUT(NOM) + 0.3 V, VBIAS = 2.8 V, VEN = VBIAS, VOUT(NOM) = 1.2 V, IOUT = 700 mA,
CIN = 4.7 mF, CBIAS = 1 mF, and COUT = 10 mF (effective capacitance), unless otherwise noted.
500
TJ = 85°C
60
VDO (VIN − VOUT),
DROPOUT VOLTAGE (mV)
VDO (VIN − VOUT),
DROPOUT VOLTAGE (mV)
70
TJ = 25°C
TJ = −40°C
50
40
30
20
10
0
0
100
200
300
400
500
600
TJ = 25°C
TJ = 85°C
350
300
250
200
150
100
50
0.5
1.5
2.5
3.5
4.5
IOUT, OUTPUT CURRENT (mA)
VBIAS − VOUT (V)
Figure 4. VIN Dropout Voltage vs. IOUT and TJ
Figure 5. VIN Dropout Voltage
vs. VBIAS − VOUT and TJ
90
TJ = −40°C
1400
IBIAS, BIAS PIN CURRENT (mA)
VDO (VBIAS − VOUT),
DROPOUT VOLTAGE (mV)
TJ = −40°C
400
0
700
1500
TJ = 25°C
TJ = 85°C
1300
1200
1100
1000
900
800
80
70
60
50
40
30
TJ = −40°C
TJ = 25°C
TJ = 85°C
20
10
0
0
100
200
300
400
500
600
0.1
700
1
10
100
1000
IOUT, OUTPUT CURRENT (mA)
Figure 6. VBIAS Dropout Voltage vs. IOUT and TJ
Figure 7. BIAS Pin Current vs. IOUT and TJ
PSRR,
POWER SUPPLY REJECTION RATIO [dB]
IOUT, OUTPUT CURRENT (mA)
100
IBIAS, BIAS PIN CURRENT (mA)
450
90
80
70
60
50
40
30
TJ = −40°C
20
TJ = 25°C
TJ = 85°C
10
0
2
2.5
3
3.5
4
4.5
5
100
VIN = 1.7 V + 100 mVPP
VBIAS = 3 V
COUT = 10 mF
90
80
70
60
50
40
30
IOUT = 10 mA
20
IOUT = 700 mA
10
0
VBIAS, BIAS VOLTAGE (V)
10
100
1k
10k
100k
1M
f, FREQUENCY [Hz]
Figure 8. BIAS Pin Current vs. VBIAS and TJ
Figure 9. VIN PSRR vs. Frequency
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10M
NCP136
100
SPECTRAL NOISE DENSITY [mV/sqrtHz]
PSRR,
POWER SUPPLY REJECTION RATIO [dB]
TYPICAL CHARACTERISTICS (continued)
At TJ = +25°C, VIN = VOUT(NOM) + 0.3 V, VBIAS = 2.8 V, VEN = VBIAS, VOUT(NOM) = 1.2 V, IOUT = 700 mA,
CIN = 4.7 mF, CBIAS = 1 mF, and COUT = 10 mF (effective capacitance), unless otherwise noted.
VIN = 1.7 V
VBIAS = 3 V + 100 mVPP
COUT = 10 mF
90
80
70
60
50
40
30
IOUT = 10 mA
20
IOUT = 700 mA
10
0
10
100
1k
10k
100k
1M
10M
10
VIN = 1.7 V
VBIAS = 2.8 V
COUT = 10 mF
1
0.1
IOUT = 1 mA
0.01
IOUT = 700 mA
0.001
10
100
10k
100k
1M
10M
FREQUENCY [Hz]
f, FREQUENCY [Hz]
Figure 10. VBIAS PSRR vs. Frequency
Figure 11. Output Voltage Spectral
Noise Density vs. Frequency
20 mV/div
100 mV/div
1k
VOUT
VOUT
1 mA
400 mA/div
400 mA/div
700 mA
IOUT
200 ms/div
700 mA
500 ms/div
Figure 13. Load Transient Response,
IOUT = 1 mA to 700 mA in 1 ms, COUT = 47 mF
40 mV/div
40 mV/div
Figure 12. Load Transient Response,
IOUT = 1 mA to 700 mA in 1 ms, COUT = 10 mF
VOUT
VOUT
350 mA
200 mA/div
200 mA/div
350 mA
1 mA
IOUT
1 mA
IOUT
100 ms/div
1 mA
Figure 14. Load Transient Response,
IOUT = 1 mA to 350 mA in 1 ms, COUT = 4.7 mF
IOUT
100 ms/div
Figure 15. Load Transient Response,
IOUT = 1 mA to 350 mA in 1 ms, COUT = 10 mF
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NCP136
VEN
2 V/div
20 mV/div
TYPICAL CHARACTERISTICS (continued)
At TJ = +25°C, VIN = VOUT(NOM) + 0.3 V, VBIAS = 2.8 V, VEN = VBIAS, VOUT(NOM) = 1.2 V, IOUT = 700 mA,
CIN = 4.7 mF, CBIAS = 1 mF, and COUT = 10 mF (effective capacitance), unless otherwise noted.
VOUT
VOUT
200 mV/div
200 mA/div
IOUT
200 mA/div
350 mA
IOUT
1 mA
20 ms/div
400 ms/div
Figure 16. Load Transient Response,
IOUT = 1 mA to 350 mA in 1 ms, COUT = 47 mF
Figure 17. Enable Transient Response, COUT = 10 mF,
IOUT = 700 mA − A Option (Normal)
2 V/div
2 V/div
VIN = 1.4 V
VBIAS = 3 V
VOUT(NOM) = 1.2 V
VEN
VEN
VOUT
200 mV/div
200 mA/div
200 mV/div
IOUT
VIN = 1.4 V
VBIAS = 3 V
VOUT(NOM) = 1.2 V
VOUT
20 ms/div
50 ms/div
Figure 19. Enable Transient Response,
COUT = 10 mF, IOUT = 700 mA − C Option (Slow)
Figure 18. Enable Transient Response, COUT = 10 mF,
IOUT = 0 mA − A Option (Normal)
1 V/div
VOUT
2.8 V
10 mV/div
200 mV/div
200 mA/div
2 V/div
3.8 V
VEN
VBIAS
VOUT
50 ms/div
10 ms/div
Figure 20. Enable Transient Response,
COUT = 10 mF, IOUT = 0 mA − C Option (Slow)
Figure 21. BIAS Line Transient Response,
VBIAS = 2.8 V to 3.8 V in 5 ms
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NCP136
TYPICAL CHARACTERISTICS (continued)
At TJ = +25°C, VIN = VOUT(NOM) + 0.3 V, VBIAS = 2.8 V, VEN = VBIAS, VOUT(NOM) = 1.2 V, IOUT = 700 mA,
CIN = 4.7 mF, CBIAS = 1 mF, and COUT = 10 mF (effective capacitance), unless otherwise noted.
10 mV/div
1 V/div
2.5 V
1.5 V
VIN
VOUT
10 ms/div
Figure 22. IN Line Transient Response,
VIN = 1.5 V to 2.5 V in 5 ms
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NCP136
APPLICATIONS INFORMATION
VBAT
NCP136
EN
Switch−mode DC/DC
VOUT = 1.5 V
EN
Processor
1.5 V
LX
IN
OUT
BIAS
IN
1.2 V
SNS
LOAD
GND
FB
GND
I/O
I/O
To other circuits
Figure 23. Typical Application: Low−Voltage DC/DC Post−Regulator with ON/OFF Functionality
Input and Output Capacitors
The NCP136 dual−rail very low dropout voltage regulator
is using NMOS pass transistor for output voltage regulation
from VIN voltage. All the low current internal control
circuitry is powered from the VBIAS voltage.
The use of an NMOS pass transistor offers several
advantages in applications. Unlike PMOS topology devices,
the output capacitor has reduced impact on loop stability.
Vin to Vout operating voltage difference can be very low
compared with standard PMOS regulators in very low Vin
applications.
The NCP136 offers smooth monotonic start-up. The
controlled voltage rising limits the inrush current.
The Enable (EN) input is equipped with internal
hysteresis. NCP136 Voltage linear regulator Fixed version
is available.
The NCP136 device is designed to be stable for ceramic
output capacitors with Effective capacitance in the range
from 4.7 mF to 47 mF. The device is also stable with multiple
capacitors in parallel, having the total effective capacitance
in the specified range.
In applications where no low input supplies impedance
available (PCB inductance in VIN and/or VBIAS inputs as
example), the recommended CIN = 1 mF and CBIAS = 0.1 mF
or greater. Ceramic capacitors are recommended. For the best
performance all the capacitors should be connected to the
NCP136 respective pins directly in the device PCB copper
layer, not through vias having not negligible impedance.
When using small ceramic capacitor, their capacitance is
not constant but varies with applied DC biasing voltage,
temperature and tolerance. The effective capacitance can be
much lower than their nominal capacitance value, most
importantly in negative temperatures and higher LDO
output voltages. That is why the recommended Output
capacitor capacitance value is specified as Effective value in
the specific application conditions.
Dropout Voltage
Because of two power supply inputs VIN and VBIAS and
one VOUT regulator output, there are two Dropout voltages
specified.
The first, the VIN Dropout voltage is the voltage
difference (VIN – VOUT) when VOUT starts to decrease by
percent specified in the Electrical Characteristics table.
VBIAS is high enough; specific value is published in the
Electrical Characteristics table.
The second, VBIAS dropout voltage is the voltage
difference (VBIAS – VOUT) when VIN and VBIAS pins are
joined together and VOUT starts to decrease.
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NCP136
VBIAS
CBIAS
1 mF
VOUT
BIAS
VIN
IN
EN
CIN
4.7 mF
OUT
NCP136
0.4 V
R1
ADJ
CFF
GND
ON
COUT
10 mF
R2
OFF
Figure 24. Typical Application Schematic − Adjustable
Output Voltage Adjustment
c. R1 = R2 = 51 kW
VOUT−ADJ = 0.4 ⋅ (1 + 51 kW/51 kW ) +
100 nA ⋅ 51 kW = 0.8051 V
Error − 0.63%
It is recommended to keep the total resistance of resistors
(R1 + R2) no greater than a few hundred kW. If total
resistance is too big the dynamic performance could get
worse due to PCB parasitic capacitance. Big resistors value
in combination with parasitic capacitance create low−pass
filter and virtually slow−down LDO control loop.
The required output voltage can be adjusted from 0.4 V to
1.8 V using two external resistors. Typical application
schematics is shown in Figure 24. Output voltage is
calculated according to equation 1. Generally, any voltage
option can used as adjustable, in the equation below
VOUT−ADJ is requested voltage and VOUT_NOM is nominal
VOUT as reference voltage. When resistor’s value is in kW
range last term (IADJ ⋅ R1) can be omitted because its effect
on output voltage accuracy is negligible. In other cases it
should be consider especially when tight output voltage
accuracy is requested.
ǒ
V OUT*ADJ + V OUT_NOM @ 1 )
Ǔ
R1
) I ADJ @ R 1
R2
Output Voltage Example:
(eq. 1)
Voltage Calculation Example − VOUT = 0.8 V:
a. R1 = R2 = 5.1 kW, no (IFB × R1)
VOUT−ADJ = 0.4 ⋅ (1 + 5.1 kW/5.1 kW ) = 0.8 V
Error − 0%
b. R1 = R2 = 5.1 kW
VOUT−ADJ = 0.4 ⋅ (1 + 5.1 kW/5.1 kW ) +
100 nA ⋅ 5.1 kW = 0.80051 V
Error − 0.06%
VOUT(V)
R1 (kW) (Note 1)
R2 (kW) (Note 1)
CFF (nF)
0.80
5.1
5.1
5.6
1.05
3.9
2.4
5.6
1.10
8.2
4.7
5.6
1. To increase power efficiency, current flows through resistor
divider can be reduced by multiply all resistor values by 10.
Feed Forward Capacitor CFF
Feedforward capacitor is recommended to improve
PSRR, load transient and noise performance.
Recommended value for NCP136 device is about 5.6 nF.
The capacitor can also improve LDO stability.
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NCP136
Enable Operation
current source with typ. value of 0.3 mA which assures that
the device is turned off when the EN pin is not connected.
The enable pin will turn the regulator on or off. The
threshold limits are covered in the electrical characteristics
table in this data sheet. To get the full functionality of Soft
Start, it is recommended to turn on the VIN and VBIAS supply
voltages first and activate the Enable pin no sooner than VIN
and VBIAS are on their nominal levels. If the enable function
is not to be used then the pin should be connected to VIN or
VBIAS.
If the EN pin voltage is < 0.4 V the device is guaranteed
to be disabled. The pass transistor is turned off so that there
is virtually no current flow between the IN and OUT. The
active discharge transistor is active (devices with Output
Active Discharge feature only) so that the output voltage
VOUT is pulled down to GND through a 150 W resistor. In
the disable state the device consumes as low as typ. 0.5 mA
from the VIN and 0.5 mA from VBIAS. If the EN pin voltage
> 0.9 V the device is guaranteed to be enabled. The NCP136
regulates the output voltage and the active discharge
transistor is turned off. The EN pin has internal pull−down
Current Limitation
The internal Current Limitation circuitry allows the
device to supply the full nominal current and surges but
protects the device against Current Overload or Short.
Thermal Protection
Internal thermal shutdown (TSD) circuitry is provided to
protect the integrated circuit in the event that the maximum
junction temperature is exceeded. When TSD activated , the
regulator output turns off. When cooling down under the low
temperature threshold, device output is activated again. This
TSD feature is provided to prevent failures from accidental
overheating.
Activation of the thermal protection circuit indicates
excessive power dissipation or inadequate heatsinking. For
reliable operation, junction temperature should be limited to
+105°C maximum.
ORDERING INFORMATION
Nominal Output
Voltage
Marking
Option
NCP136AFCT080T2G
0.80 V
7A
Output Active Discharge,
Normal Turn−On Slew Rate
NCP136BFCT080T2G
0.80 V
7H
Non*Active Discharge,
Normal Turn−On Slew Rate
NCP136AFCT088T2G
0.88 V
7J
Output Active Discharge,
Normal Turn−On Slew Rate
NCP136AFCT105T2G
1.05 V
7K
Output Active Discharge,
Normal Turn−On Slew Rate
NCP136AFCT110T2G
1.10 V
7L
Output Active Discharge,
Normal Turn−On Slew Rate
NCP136AFCT120T2G
1.20 V
7E
Output Active Discharge,
Normal Turn−On Slew Rate
NCP136CFCT120T2G
1.20 V
7C
Output Active Discharge,
Slow Turn−On Slew Rate
NCP136AFCRC040T2G
0.40 V
7M
Output Active Discharge,
Normal Turn−On Slew Rate
Back Side Coating
Device
NCP136AFCRC080T2G
0.80 V
7A
Output Active Discharge,
Normal Turn−On Slew Rate
Back Side Coating
Package
Shipping†
WLCSP6
Case 567XK
(Pb−Free)
5000 / Tape & Reel
WLCSP6
Case 567YU
(Pb−Free)
5000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
To order other package and voltage variants, please contact your ON Semiconductor sales representative.
www.onsemi.com
12
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WLCSP6 1.4x0.8x0.33
CASE 567XK
ISSUE O
DATE 15 JAN 2019
GENERIC
MARKING DIAGRAM*
XXM
XX = Specific Device Code
M = Month Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON03100H
WLCSP6 1.4x0.8x0.33
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WLCSP6 1.4x0.8x0.37
CASE 567YU
ISSUE O
DATE 14 NOV 2019
GENERIC
MARKING DIAGRAM*
XXM
XX = Specific Device Code
M = Month Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON14943H
WLCSP6 1.4x0.8x0.37
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
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vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
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