NCP1377, NCP1377B
PWM Current-Mode
Controller for Free-Running
Quasi-Resonant Operation
The NCP1377 combines a true current mode modulator and a
demagnetization detector which ensures full borderline/critical
Conduction Mode in any load/line conditions together with
minimum drain voltage switching (Quasi−Resonant operation). Due
to its inherent skip cycle capability, the controller enters burst mode
as soon as the power demand falls below a predetermined level. As
this happens at low peak current, no audible noise can be heard. For
NCP1377, an internal 8.0 ms timer prevents the free−run frequency to
exceed 100 kHz (therefore below the 150 kHz CISPR−22 EMI
starting limit), while the skip adjustment capability lets the user
select the frequency at which the burst foldback takes place. For
NC1377B, the internal timer duration is reduced to 3.0 ms to allow
operation at higher frequencies (up to 300 kHz).
The transformer core reset detection is done through an auxiliary
winding which, brought via a dedicated pin, also enables fast
Over Voltage Protection (OVP). Once an OVP has been detected, the
IC permanently latches off. The 1377 features a sampling time of
4.5 ms whereas it is 1.5 ms for the B version.
The NCP1377 also features an efficient protective circuitries
which, in presence of an overcurrent condition, disables the output
pulses and enters a safe burst mode, trying to restart. Once the default
has gone, the device auto−recovers. Finally an internal 1.0 ms
Soft−Start eliminates the traditional startup stress.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Free−Running Borderline/Critical Mode Quasi−Resonant Operation
Latched Overvoltage Protection
Auto−Recovery Short−Circuit Protection Via UVLO Crossover
External Latch Triggering, e.g. Via Overtemperature Signal
Current−Mode with Adjustable Skip Cycle Capability
Internal 1.0 ms Soft−Start
Internal Temperature Shutdown
Internal Leading Edge Blanking
500 mA Peak Current Source/Sink Capability
Under Voltage Lockout Level of 12.5 V (On) and 7.5 V (Min)
Direct Optocoupler Connection
SPICE Models Available for TRANsient Analysis
Internal Minimum TOFF
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
AC−DC Adapters for Notebooks, etc.
Offline Battery Chargers
Consumer Electronics (DVD Players, Set−Top Boxes, TVs, etc.)
Auxiliary Power Supplies (USB, Appliances, TVs, etc.)
© Semiconductor Components Industries, LLC, 2015
October, 2015 − Rev. 13
MARKING DIAGRAMS
8
8
8
1377
ALYW
G
1
SOIC−8
DR SUFFIX
CASE 751
1377B
ALYW
G
1
1
8
8
377D1
ALYW G
G
1
SOIC−7
D1 SUFFIX
CASE 751U
1
1377P
AWL
YYWWG
8
1
PDIP−7
P SUFFIX
CASE 626B
1
1377BP
AWL
YYWWG
1
A
= Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
Dmg 1
8 HV
FB 2
CS 3
6 VCC
GND 4
5 Drv
(Top View)
Typical Applications
•
•
•
•
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1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
Publication Order Number:
NCP1377/D
NCP1377, NCP1377B
R*
+
12 V @ 1 A
GND
OVP and
Demag
+
Universal
Network
NCP1377
1
8
2
7
3
6
4
5
+
*Please refer to the application information section.
Y1 Type
Figure 1. Typical Application Schematic
PIN FUNCTION DESCRIPTION
Pin
Symbol
Function
Description
1
Demag
Core reset detection and OVP
The auxiliary FLYBACK signal ensures discontinuous operation and offers a fixed
overvoltage detection level of 7.2 V.
2
FB
Sets the peak current setpoint
By connecting an optocoupler to this pin, the peak current setpoint is adjusted
accordingly to the output power demand. By bringing this pin below the internal
skip level, you shut off the device.
3
CS
Current sense input and skip
cycle level selection
This pin senses the primary current and routes it to the internal comparator via an
L.E.B. By inserting a resistor in series with the pin, you control the level at which
the skip operation takes place.
4
GND
The IC ground
−
5
Drv
Driving pulses
The driver’s output to an external MOSFET.
6
VCC
Supplies the IC
This pin is connected to an external bulk capacitor of typically 10 mF.
7
NC
−
8
HV
High−voltage pin
This unconnected pin ensures adequate creepage distance.
Connected to the high−voltage rail, this pin injects a constant current into the VCC
bulk capacitor and ensures a clean lossless startup sequence.
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2
NCP1377, NCP1377B
1.5 us for B Version
4.5 us
Delay
Demag
HV
OVP
Demag
+
8 us
Blanking
PON
4 mA
/1.44
5V
+
+
S
+
+
S
R
VCC
+
50 mV
3 us for
B Version
Q
Rint
VCC
Drv
Q
R
12.5 V
7.5 V
5.6 V (Fault)
To Internal
Supply
10 V
Driver src = 20 sink = 10
4.2 V
Fault
Mngt.
FB
/3
+
-
GND
1V
200 mA
when DRV
is OFF
Overload?
5 us
Timeout
380 ns
LEB
Time
Reset
CS
Demag
Figure 2. Internal Circuit Architecture
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VCC, Drv
18
V
VCC Pulse
25
V
Maximum Voltage on all other pins except Pin 8 (HV), Pin 6 (VCC) and Pin 5 (Drv)
−
−0.3 to 10
V
Maximum Current into all pins except VCC (6), HV (8) and Demag (1) when 10 V ESD diodes are activated
−
5.0
mA
Maximum Current in Pin 1
Idem
+3.0/−2.0
mA
Thermal Resistance, Junction−to−Case
RqJC
57
°C/W
Thermal Resistance, Junction−to−Air, SOIC Version
RqJA
178
°C/W
Thermal Resistance, Junction−to−Air, PDIP Version
RqJA
100
°C/W
TJMAX
150
°C
Temperature Shutdown
−
155
°C
Hysteresis in Shutdown
−
30
°C
Storage Temperature Range
−
−60 to +150
°C
ESD Capability, HBM Model (All pins except VCC and HV)
−
2.0
kV
ESD Capability, Machine Model
−
200
V
VHV
500
V
Continuous Power Supply or Drive Voltage
Transient Power Supply Voltage, Duration < 10 ms, IVCC < 20 mA
Maximum Junction Temperature
Maximum Voltage on Pin 8 (HV), Pin 6 (VCC) Decoupled to Ground with 10 mF
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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3
NCP1377, NCP1377B
ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 11 V unless otherwise noted.)
Characteristic
Pin
Symbol
Min
Typ
Max
Unit
VCC Increasing Level at which the Current Source Turns−Off
6
VCCON
11.6
12.5
13.7
V
Minimum Operating Voltage after Turn−On
6
VCCOFF
7.0
7.5
8.2
V
VCC Decreasing Level at which the Latchoff Phase Ends
6
VCClatch
−
5.6
−
V
Internal IC Consumption, No Output Load on Pin 5, FSW = 60 kHz
6
ICC1
−
1.0
1.3
(Note 1)
mA
Internal IC Consumption, 1.0 nF Output Load on Pin 5, FSW = 60 kHz
6
ICC2
−
1.6
2.0
(Note 1)
mA
Internal IC Consumption, Latchoff Phase, VCC = 6.0 V
6
ICC3
−
220
−
mA
High−Voltage Current Source, VCC = 10 V, Vpin8 = 50 V
8
IC1
2.4
4.0
6.0
mA
High−Voltage Current Source, VCC = 0 V, Vpin8 = 50 V
8
IC2
−
4.5
−
mA
Startup Leakage, Vpin8 = 500 V
8
IHVLeak
−
30
70
mA
High Voltage Minimum Startup, VCC = VCC(on)−0.2 V, ICC = 1 mA
8
HVmin
−
20
23.5
V
Output Voltage Rise−Time @ CL = 1.0 nF, 10−90% of Output Signal
5
Tr
−
40
−
ns
Output Voltage Fall−Time @ CL = 1.0 nF, 10−90% of Output Signal
5
Tf
−
20
−
ns
Source Resistance
5
ROH
12
20
36
W
Sink Resistance
5
ROL
5.0
10
19
W
Input Bias Current @ 1.0 V Input Level on Pin 3
3
IIB
−
0.02
−
mA
Maximum Internal Current Setpoint
3
ILimit
0.9
1.0
1.1
V
Propagation Delay from Current Detection to Gate OFF State
3
TDEL
−
100
160
ns
Leading Edge Blanking Duration
3
TLEB
−
380
−
ns
Internal Current Offset Injected on the CS Pin During OFF Time
3
Iskip
−
200
−
mA
1
1
Tsample
−
−
4.5
1.5
−
−
ms
1
Vref
6.4
7.2
8.0
V
Internal Pullup Resistor
2
Rup
−
20
−
kW
Pin 3 to Current Setpoint Division Ratio
−
Iratio
−
3.3
−
−
Internal Soft−Start
−
Tss
−
1.0
−
ms
Input Threshold Voltage (Vpin 1 Decreasing)
1
Vth
35
50
90
mV
Hysteresis (Vpin 1 Decreasing)
1
VH
−
20
−
mV
Input Clamp Voltage
High State (Ipin 1 = 3.0 mA)
Low State (Ipin 1 = −2.0 mA)
1
1
VCH
VCL
8.0
−0.9
10
−0.7
12
−0.5
Pin1 Internal Resistance
1
Rint
−
28
−
kW
Demag Propagation Delay
1
Tdem
−
210
−
ns
Timeout After Last Demag Transition
1
Tout
−
5.0
−
ms
1
Cpar
−
10
−
pF
1
1
Tblank
−
−
8.0
3.0
−
−
ms
SUPPLY SECTION
INTERNAL STARTUP CURRENT SOURCE
DRIVE OUTPUT
CURRENT COMPARATOR
OVERVOLTAGE SECTION
Sampling Delay After ON Time
NCP1377
NCP1377B
OVP Internal Reference Level
FEEDBACK SECTION
DEMAGNETIZATION DETECTION BLOCK
V
Internal Input Capacitance at Vpin 1 = 1.0 V
Minimum TOFF (Internal Blanking Delay After TON)
NCP1377
NCP1377B
1. Max value at Tj = −40°C, please see characterization curves.
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4
NCP1377, NCP1377B
TYPICAL CHARACTERISTICS
7.90
14.0
7.80
13.5
7.70
VCCOFF, (V)
VCCON, (V)
13.0
12.5
12.0
7.50
7.40
11.5
7.30
11.0
−50
−30
−10
10
30
50
70
90
110
7.20
−50
130
−30
−10
10
30
50
70
90
110
130
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 3. VCCON Threshold versus Temperature
Figure 4. VCCOFF Threshold versus Temperature
1.60
2.30
1.40
2.10
1.20
1.90
ICC2, (mA)
ICC1, (mA)
7.60
1.00
1.70
0.80
1.50
0.60
1.30
0.40
−50
−30
−10
10
30
50
70
90
110
1.10
−50
130
−30
−10
10
30
50
70
90
110
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 5. Current Consumption (No Load)
versus Temperature
Figure 6. Current Consumption (1.0 nF Load)
versus Temperature
130
1.10
6.0
5.5
1.05
4.5
Ilimit, (V)
IC1, (mA)
5.0
4.0
1.00
3.5
0.95
3.0
2.5
2.0
−50
−30
−10
10
30
50
70
90
110
130
0.90
−50
−30
−10
10
30
50
70
90
110
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. HV Current Source at VCC = 10 V
versus temperature
Figure 8. Maximum Current Setpoint versus
Temperature
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5
130
NCP1377, NCP1377B
TYPICAL CHARACTERISTICS
40.0
20.0
35.0
18.0
16.0
30.0
14.0
ROL, (W)
ROH, (W)
25.0
20.0
15.0
12.0
10.0
8.0
6.0
10.0
4.0
5.0
2.0
0.0
−50
−30
−10
10
30
50
70
90
110
0.0
−50
130
−30
−10
TEMPERATURE (°C)
50
70
90
110
130
Figure 10. Drive Sink Resistance versus
Temperature
120
7.8
100
7.6
7.4
Vref, (V)
80
VTH, (mV)
30
TEMPERATURE (°C)
Figure 9. Drive Source Resistance versus
Temperature
60
40
7.2
7.0
6.8
20
6.6
0
−50
−30
−10
10
30
50
70
90
110
6.4
−50
130
−30
−10
TEMPERATURE (°C)
9.5
6.80
9.0
6.30
Tout, (ms)
7.30
8.5
8.0
7.0
4.30
10
30
50
70
70
90
110
130
5.30
4.80
−10
50
5.80
7.5
−30
30
Figure 12. OVP Threshold versus Temperature
10.0
6.5
−50
10
TEMPERATURE (°C)
Figure 11. Demagnetization Detection Threshold
versus Temperature
Tblank, (ms)
10
90
110
130
3.80
−50
TEMPERATURE (°C)
−30
−10
10
30
50
70
90
110
130
TEMPERATURE (°C)
Figure 13. Minimum TOFF versus Temperature
Figure 14. Demagnetization Detection Timeout
versus Temperature
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6
NCP1377, NCP1377B
60
50
Rint kW
40
•
30
20
•
10
0
−50
−30
−10
10
30
50
70
90
110
130
TEMPERATURE (°C)
Figure 15. DMG Pin Internal Resistance versus
Temperature
•
APPLICATION INFORMATION
INTRODUCTION
The NCP1377 implements a standard current mode
architecture where the switch−off time is dictated by the
peak current setpoint, whereas the core reset detection
triggers the turn−on event. This component represents the
ideal candidate where low part−count is the key parameter,
particularly in low−cost AC−DC adapters, consumer
electronics, auxiliary supplies, etc. Due to its high−
performance high−voltage technology, the NCP1377
incorporates all the necessary components/features needed
to build a rugged and reliable Switchmode Power Supply
(SMPS):
• Transformer Core Reset Detection: Borderline/critical
operation is ensured whatever the operating conditions
are. As a result, there are virtually no primary switch
turn−on losses and no secondary diode recovery
losses. The converter also stays a first−order system
and accordingly eases the feedback loop design.
• Quasi−Resonant Operation: By delaying the turn−on
event, it is possible to restart the MOSFET in the
minimum of the drain−source wave, ensuring reduced
EMI/video noise perturbations. In nominal power
conditions, the NCP1377 operates in Borderline
Conduction Mode (BCM) also called Critical
Conduction Mode.
• Undervoltage Lockout (UVLO): When Vcc falls below
VCCoff pulses are stopped and the IC consumption
drops down to a few hundred of mA. When Vcc
reaches the latchoff level (5.6 V typical), the startup
current source is activated and brings Vcc back to
Vccon where the IC attempts to startup.
• Overvoltage Protection (OVP): By sampling the
plateau voltage on the demagnetization winding, the
NCP1377 goes into latched fault condition whenever
an overvoltage condition is detected. The controller
stays fully latched in this position until the Vcc is
cycled down to 4.0 V, e.g. when the user unplugs the
power supply from the mains outlet and replugs it.
External Latch Trip Point: By externally forcing a
level on the OVP greater than the internal setpoint, it
is possible to latchoff the IC, e.g. with a signal coming
from a temperature sensor.
Adjustable Skip Cycle Level: By offering the ability
to tailor the level at which the skip cycle takes place,
the designer can make sure that the skip operation
only occurs at low peak current. This point guarantees
a noise−free operation with cheap transformer. This
option also offers the ability to fix the maximum
switching frequency when entering light load conditions.
Overcurrent Protection (OCP): NCP1377 enters burst
mode as soon as the power supply undergoes an
overload which is detected through the sense of the
auxiliary voltage. As detailed above, as soon as Vcc
crosses the undervoltage lockout level (VCCoff in the
electrical table), all pulses are stopped and the device
enters a safe low power operation which prevents from
any lethal thermal runaway. By monitoring the Vcc
level, the startup current source is activated ON and
OFF to create a kind of burst mode where the SMPS
tries to restart. If the fault has gone, the SMPS
resumes operation. On the other hand, if the fault is
still there, the burst sequence starts again.
Startup Sequence
When the power supply is first powered from the mains
outlet, the internal current source (typically 4.0 mA) is
biased and charges up the Vcc capacitor. When the voltage
on this Vcc capacitor reaches the VccON level (typically
12.5 V), the current source turns off and no longer wastes
any power. At this time, the Vcc capacitor only supplies the
controller and the auxiliary supply is supposed to take over
before Vcc collapses below VCCoff. Figure 16 shows the
internal arrangement of this structure.
8
VccON/VccOFF
+
−
HV
IC1 or 0
6
CVCC
Aux
4
Figure 16. The Current Source Brings Vcc Above
VccON and Then Turns Off
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7
NCP1377, NCP1377B
Skipping Cycle Mode
Once the power supply has started, the VCC shall be
constrained below 18 V, which is the maximum rating on
pin 6. Figure 17 portrays a typical NCP1377 startup
sequence with a Vcc regulated at 12.5 V.
The NCP1377 automatically skips switching cycles
when the output power demand drops below a given level.
This is accomplished by monitoring the FB pin. In normal
operation, pin 2 imposes a peak current accordingly to the
load value. If the load demand decreases, the internal loop
asks for less peak current. When this setpoint reaches a
determined level, the IC prevents the current from
decreasing further down and starts to blank the output
pulses: the IC enters the so−called skip cycle mode, also
named controlled burst operation. The power transfer now
depends upon the width of the pulse bunches (Figure 18)
and
follows
the
following
formula:
13.5
12.5 V
Regulation
VCC
12.5
11.5
10.5
1 · Lp · Ip2 · Fsw · D
burst with:
2
Lp = Primary inductance
Fsw = Switching frequency within the burst
Ip = Peak current at which skip cycle occurs
9.50
Figure 17. A Typical Startup Sequence
for the NCP1377
Dburst = Burst width/burst recurrence
CURRENT SENSE SIGNAL (mV)
DRIVER
300
MAX PEAK
CURRENT
NORMAL CURRENT
MODE OPERATION
DRIVER = HIGH ? I = 0
DRIVER = LOW ? I = 200 mA
SKIP CYCLE
CURRENT LIMIT
200
Rskip
RESET
+
3
100
Rsense
2
0
WIDTH
+
RECURRENCE
Figure 18. The Skip Cycle Takes Place at Low Peak
Currents which Guarantees Noise−Free Operation
Figure 19. A Patented Method Allows for Skip
Level Selection via a Series Resistor Inserted in
Series with the Current
voltage is below Rskip level, then the current sense
comparator permanently resets the latch and the next clock
cycle (given by the demagnetization detection) is ignored:
we are skipping cycles as shown by Figure 18. As soon as
the feedback voltage goes up again, there can be two
situations: the recurrent period is small and a new
demagnetization detection (next wave) signal triggers the
NCP1377. To the opposite, in low output power conditions,
no more ringing waves are present on the drain and the
toggling of the current sense comparator alone initiates a
new cycle start. Figure 20 depicts these two different
situations.
The skip level selection is done through a simple resistor
inserted between the current sense input and the sense
element. Everytime the NCP1377 output driver goes low,
a 200 mA source forces a current to flow through the sense
pin (Figure 19): when the driver is high, the current source
is off and the current sense information is normally
processed. As soon as the driver goes low, the current
source delivers 200 mA and develops a ground referenced
voltage across Rskip. If this voltage is below the feedback
voltage, the current sense comparator stays in the low state
and the internal latch can be triggered by the next clock
cycle. Now, if because of a low load mode the feedback
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8
NCP1377, NCP1377B
Drain
Signal
Timeout
Signal
Demag Restart
Current Sense and Timeout Restart
Drain
Signal
Timeout
Signal
5 ms
5 ms
Figure 20. When the primary natural ringing becomes too low, the internal TimeOut
together with the sense comparator initiates a new cycle when FB passes the skip level.
maximum peak current). If anyway a lower skip threshold
is needed, care must be taken to select an optocoupler with
a Vce(sat) guaranteed to be below the chosen skip level
with enough margin.
An optocoupler is generally used to transfer the feedback
information to the FB pin while providing the necessary
isolation. It introduces a limitation in how low the skip
level can be adjusted since an optocoupler cannot pull the
FB voltage below its Vce(sat), which is usually around
150 mV. Therefore, in order to take into account
temperature and process variations, it is not recommended
to set up the skip level below 250 mV, which corresponds
to a minimum resistor Rskip of 420 W. The 150 mV is a
much lower level than what will usually be used (it sets the
peak current when entering skip mode at 5% of the
Demagnetization Detection
The core reset detection is done by monitoring the
voltage activity on the auxiliary winding. This voltage
features a FLYBACK polarity. The typical detection level
is fixed at 50 mV as exemplified by Figure 21.
DEMAG SIGNAL (V)
7.0
5.0
POSSIBLE
RESTARTS
TO INTERNAL
COMPARATOR
3.0
Resd
2
1.0
Rint
50 mV
0V
ESD2
Rdem
1
1
5
ESD1
4
−1.0
Resd + Rint = 28 k
Figure 21. Core Reset Detection is Done through
a Dedicated Auxiliary Winding Monitoring
Figure 22. Internal Pad Implementation
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9
4
Aux
3
NCP1377, NCP1377B
An internal timer prevents any restart within 8.0 ms
further to the driver going−low transition for NCP1377,
and 3.0 ms for NCP1377B. This prevents the switching
frequency to exceed (1.0/TON + Tblank) but also avoid false
leakage inductance tripping at turn−off. In some cases, the
leakage inductance kick is so energetic, that a slight
filtering is necessary.
The NCP1377 demagnetization detection pad features a
specific component arrangement as detailed by Figure 22.
In this picture, the zener diodes network protect the IC
against any potential ESD discharge that could appear on
the pins. The first ESD diode connected to the pad, exhibits
a parasitic capacitance. When this parasitic capacitance
(10 pF typically) is combined with Rdem, a restart delay
is created and the possibility to switch right in the
drain−source wave exists. This guarantees QR operation
with all the associated benefits (low EMI, no turn−on
losses etc.). Rdem should be calculated to limit the
maximum current flowing through pin 1 to less than
+3.0 mA/−2.0 mA: If during turn−on, the auxiliary
winding delivers 30 V (at the highest line level), then the
minimum Rdem value is defined by: 30 + 0.7/3.0 mA =
10.2 kW. This value will be further increased, e.g. to
introduce a restart delay and also a slight filtering in case
of high leakage energy.
Figure 23 portrays a typical Vds shot at nominal output
power.
for NCP1377 and 1.5 ms for NCP1377B guarantees a clean
plateau, providing that the leakage inductance ringing has
been fully damped. If this would not be the case, the
designer should install a small RC damper across the
transformer primary inductance connections. Figure 24
shows where the sampling occurs on the auxiliary winding.
SAMPLING HERE
DEMAG SIGNAL (V)
8.0
4.0
2.0
4.5 ms
0
Figure 24. A Voltage Sample is Taken 4.5 ms
After the Turn−Off Sequence
When an OVP condition has been detected, the
NCP1377 enters a latchoff phase and stops all switching
operations. The controller stays fully latched in this
position and the startup source being still active, it keeps
the Vcc going up and down between 12.5 V and 5.6 V. This
state lasts until the Vcc is cycled down to 4.0 V, e.g. when
the user unplugs the power supply from the mains outlet.
By default, the OVP comparator is biased to a 5.0 V
reference level and pin1 is routed via a divide by a 1.44
network. As a result, when Vpin1 reaches 7.2 V, the OVP
comparator is triggered. The threshold can thus be adjusted
by either modifying the power winding to auxiliary
winding turn ratios to match this 7.2 V level or insert a
resistor from pin1 to ground to cope with your design
requirement.
400
DRAIN VOLTAGE (V)
6.0
300
200
100
0
Latching Off the NCP1377
In certain cases, it can be very convenient to externally
shut down permanently the NCP1377 via a dedicated
signal, e.g. coming from a temperature sensor (Figure 25).
The reset occurs when the user unplugs the power supply
from the mains outlet. To trigger the latchoff by an external
signal, a simple PNP transistor can do the work, as
Figure 26 shows.
Figure 23. The NCP1377 Operates in
Borderline/Critical Operation
Overvoltage Protection
The overvoltage protection works by sampling the
plateau voltage after the turn−off sequence. A 4.5 ms delay
www.onsemi.com
10
NCP1377, NCP1377B
Thermistor
Rdem
NCP1377
Aux.
1
8
2
7
3
6
4
5
Aux.
Winding
ON/OFF
Figure 25. A simple arrangement triggers
the latchoff as soon as the temperature
exceeds a given setpoint.
NCP1377
3
2
10 nF
Q1
7
3
6
4
5
a low level, preventing a bias current to circulate in the
optocoupler LED. As a result, the auxiliary voltage also
decreases because it also operates in Flyback and thus
duplicates the output voltage, providing the leakage
inductance between windings is kept low. To account for
this situation and properly protect the power supply,
NCP1377 hosts a dedicated overload detection circuitry.
Once activated, this circuitry imposes to deliver pulses in
a burst manner with a low Duty Cycle. The system
auto−recovers when the fault condition disappears.
During the startup phase, the peak current is pushed to
the maximum until the output voltage reaches its target and
the feedback loop takes over. The auxiliary voltage takes
place after a few switching cycles and self−supplies the IC.
In presence of a short circuit on the output, the auxiliary
voltage will go down until it crosses the undervoltage
lockout level of typically 7.5 V. When this happens,
NCP1377 immediately stops the switching pulses and
unbiases all unnecessary logical blocks. The overall
consumption drops, while keeping the gate grounded, and
the Vcc slowly falls down. As soon as Vcc reaches typically
5.6 V, the startup source turns−on again and a new startup
sequence occurs, bringing Vcc toward 12.5 V as an attempt
to restart. If the default has gone, then the power supply
normally restarts. If not, a new protective burst is initiated,
shielding the SMPS from any runaway. Figure 28 portrays
the typical operating signals in short circuit.
Shutdown can easily be implemented through a simple
NPN bipolar transistor as depicted by Figure 27. When
OFF, Q1 is transparent to the operation. When forward
biased, the transistor pulls the FB pin to ground (Vcesat ≈
200 mV) and permanently disables the IC. A small time
constant on the transistor base will avoid false triggering
(Figure 27).
ON/OFF
2
Figure 26. A simple transistor arrangement
triggers the latchoff as soon as the
temperature exceeds a given setpoint.
Shutting Off the NCP1377
1
8
VCCcap
CVCC
10 k
1
1
8
2
7
3
6
4
5
Figure 27. A Simple Bipolar Transistor Totally
Disables the IC
Overload Operation
In applications where the output current is purposely not
controlled (e.g. wall adapters delivering raw DC level), it
is interesting to implement a true short−circuit protection.
A short−circuit actually forces the output voltage to be at
www.onsemi.com
11
NCP1377, NCP1377B
VccON
Vccoff
Vcc
Vcclatch
Driving Pulses
Figure 28. Typical Waveforms in Short Circuit Conditions
Soft−Start
15 ms. CVCC is calculated using the equation C +
The NCP1377 features an internal 1.0 ms Soft−Start to
soften the constraints occurring in the power supply during
startup. It is activated during the power on sequence. As
soon as Vcc reaches VccON , the peak current is gradually
increased from nearly zero up to the maximum clamping
level (e.g. 1.0 V). The Soft−Start is also activated during
the overcurrent burst (OCP) sequence. Every restart
attempt is followed by a Soft−Start activation. Generally
speaking, the Soft−Start will be activated when Vcc ramps
up either from zero (fresh power−on sequence) or 5.6 V, the
latchoff voltage occurring during OCP.
Dt · i
or
DV
C w 8.6 mF. Select a 22 mF/16 V and this will fit. During
the latchoff phase, the current consumption drops to ICC3
or 220 mA. We can now calculate how long this latchoff
phase will last: (7.5–5.6) x 22 m/220 u = 190 ms.
Protecting Pin 8 Against Negative Spikes
As any CMOS controller, NCP1377 is sensitive to
negative voltages that could appear on its pins. To avoid
any adverse latchup of the IC, we strongly recommend to
insert a resistor RHV in series with pin8. This resistor
prevents from adversely latching the controller in case of
negative spikes appearing on the bulk capacitor during the
power−off sequence. A typical value of 6.8 kW/0.5 W is
suitable. This resistor does not dissipate any power since it
only sees current during the startup sequence and during
overload. Calculations actually involve the minimum
voltage on pin8 necessary to fully activate the current
source. This minimum voltage being 40 V, therefore RHV
shall be less than: (Vbulkmin–40)/6.0 m.
Calculating the Vcc Capacitor
The Vcc capacitor can be calculated knowing the IC
consumption as soon as Vcc reaches VccON. Suppose that
a NCP1377 is used and drives a MOSFET with a 30 nC
total gate charge (Qg). The total average current is thus
made of Icc1 (1.0 mA) plus the driver current, Fsw x Qg or
1.8 mA. The total current is therefore 2.8 mA. The DV
available to fully startup the circuit (e.g. never reach the
7.5 V UVLO during power on) is 12.5 – 7.5 = 5.0 V. We
have a capacitor which then needs to supply the NCP1377
with 2.8 mA during a given time until the auxiliary supply
takes over. Suppose that this time was measured at around
Operating Shots
Following are some oscilloscope shots captured at
Vin = 120 VDC with a transformer featuring a 800 mH
primary inductance.
www.onsemi.com
12
NCP1377, NCP1377B
Figure 29. This plot gathers waveforms captured at three different operating points:
1st Upper Plot: Free run, valley switching operation, Pout = 26 W.
2nd Middle Plot: Min Toff clamps the switching frequency and selects
the second valley.
3rd Lowest Plot: The skip slices the second valley pattern and will
further expand the burst as Pout goes low.
Vrsense (200 mV/div)
Vgate (5 V/div)
200 mA x Rskip
Current Sense Pin (200 mV/pin)
Figure 30. This picture explains how the 200 mA internal offset
current creates the skip cycle level.
www.onsemi.com
13
NCP1377, NCP1377B
Vcc (5 V/div)
Vgate (5 V/div)
Latchoff Level
Figure 31. The short−circuit protection forces the IC to enter burst
in presence of a secondary overload.
ORDERING INFORMATION
Device
Package Type
Shipping†
NCP1377DR2G
SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCP1377BDR2G
SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCP1377D1R2G
SOIC−7
(Pb−Free)
2500 / Tape & Reel
NCP1377BD1R2G
SOIC−7
(Pb−Free)
2500 / Tape & Reel
NCP1377PG
PDIP−7
(Pb−Free)
50 Units / Rail
NCP1377BPG
PDIP−7
(Pb−Free)
50 Units / Rail
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
14
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−7 (PDIP−8 LESS PIN 7)
CASE 626B
ISSUE D
DATE 22 APR 2015
SCALE 1:1
D
A
E
H
8
5
E1
1
4
NOTE 8
b2
c
B
END VIEW
TOP VIEW
WITH LEADS CONSTRAINED
NOTE 5
A2
A
e/2
NOTE 3
L
SEATING
PLANE
A1
C
D1
M
e
8X
SIDE VIEW
b
0.010
eB
END VIEW
M
C A
M
B
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.355 0.400
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
9.02
10.16
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
NOTE 6
GENERIC
MARKING DIAGRAM*
STYLE 1:
PIN 1. AC IN
2. DC + IN
3. DC − IN
4. AC IN
5. GROUND
6. OUTPUT
7. NOT USED
8. VCC
XXXXXXXXX
AWL
YYWWG
XXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
98AON12198D
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PDIP−7 (PDIP−8 LESS PIN 7)
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−7
CASE 751U−01
ISSUE E
DATE 20 OCT 2009
SCALE 1:1
−A−
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B ARE DATUMS AND T
IS A DATUM SURFACE.
4. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
5. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5
−B− S
0.25 (0.010)
B
M
M
1
4
G
C
R
X 45 _
J
−T−
SEATING
PLANE
H
0.25 (0.010)
K
M
D 7 PL
M
T B
S
A
DIM
A
B
C
D
G
H
J
K
M
N
S
INCHES
MIN MAX
0.189 0.197
0.150 0.157
0.053 0.069
0.013 0.020
0.050 BSC
0.004 0.010
0.007 0.010
0.016 0.050
0_
8_
0.010 0.020
0.228 0.244
S
GENERIC
MARKING DIAGRAM
SOLDERING FOOTPRINT*
8
1.52
0.060
7.0
0.275
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
1
XXX
A
L
Y
W
G
4.0
0.155
0.6
0.024
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
1.270
0.050
SCALE 6:1
XXXXX
ALYWX
G
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
98AON12199D
DESCRIPTION:
7−LEAD SOIC
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−7
CASE 751U−01
ISSUE E
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6.
7. NOT USED
8. EMITTER
DATE 20 OCT 2009
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. NOT USED
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. NOT USED
8. SOURCE, #1
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5.
6.
7. NOT USED
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6.
7. NOT USED
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. NOT USED
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR (DIE 1)
2. BASE (DIE 1)
3. BASE (DIE 2)
4. COLLECTOR (DIE 2)
5. COLLECTOR (DIE 2)
6. EMITTER (DIE 2)
7. NOT USED
8. COLLECTOR (DIE 1)
STYLE 9:
PIN 1. EMITTER (COMMON)
2. COLLECTOR (DIE 1)
3. COLLECTOR (DIE 2)
4. EMITTER (COMMON)
5. EMITTER (COMMON)
6. BASE (DIE 2)
7. NOT USED
8. EMITTER (COMMON)
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. NOT USED
8. GROUND
STYLE 11:
PIN 1. SOURCE (DIE 1)
2. GATE (DIE 1)
3. SOURCE (DIE 2)
4. GATE (DIE 2)
5. DRAIN (DIE 2)
6. DRAIN (DIE 2)
7. NOT USED
8. DRAIN (DIE 1)
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. NOT USED
8. COMMON CATHODE
DOCUMENT NUMBER:
98AON12199D
DESCRIPTION:
7−LEAD SOIC
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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