NCP1378

NCP1378 PWM Current−Mode Controller for Free−Running Quasi−Resonant Operation The NCP1378 combines a true current mode modulator and a demagnetization detector to ensure full borderline/critical Conduction Mode in any load/line conditions and minimum drain voltage switching (Quasi−Resonant operation). Due to its inherent skip cycle capability, the controller enters burst mode as soon as the power demand falls below a predetermined level. As this happens at low peak current, no audible noise can be heard. An internal 8.0 ms timer prevents the free−run frequency to exceed 100 kHz (therefore below the 150 kHz CISPR−22 EMI starting limit), while the skip adjustment capability lets the user select the frequency at which the burst foldback takes place. The transformer core reset detection is done through an auxiliary winding which, brought via a dedicated pin, also enables fast Over Voltage Protection (OVP). Once an OVP has been detected, the IC permanently latches off. The NCP1378 also features an efficient protective circuitry that, in presence of an overcurrent condition, disables the output pulses and enters a safe burst mode, trying to restart. Once the default has gone, the device auto−recovers. Finally an internal 1.0 ms Soft−Start eliminates the traditional startup stress. The NCP1378 is tailored for low voltage applications having UVLO thresholds of 8.4 V (on) and 7.5 V (off). Features http://onsemi.com MARKING DIAGRAMS 8 8 1 SOIC−8 D SUFFIX CASE 751 1 1378 ALYW 8 1 PDIP−7 P SUFFIX CASE 626B 1 A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week 1378P AWL YYWW • • • • • • • • • • • • • Pb−Free Package is Available* Free−Running Borderline/Critical Mode Quasi−Resonant Operation Latched Overvoltage Protection Auto−Recovery Short−Circuit Protection Via UVLO Crossover Current−Mode with Adjustable Skip Cycle Capability Internal 1.0 ms Soft−Start Internal Temperature Shutdown Internal Leading Edge Blanking 500 mA Peak Current Source/Sink Capability External Latch Triggering, e.g. Via Overtemperature Signal Direct Optocoupler Connection SPICE Models Available for TRANsient Analysis Internal 8.0 ms Minimum TOFF PIN CONNECTIONS Dmg 1 FB 2 CS 3 GND 4 (Top View) 6 VCC 5 Drv 8 HV ORDERING INFORMATION Device NCP1378DR2 Package SOIC−8 PDIP−7 PDIP−7 (Pb−Free) Shipping† 2500 Tape & Reel 50 Units/Tube 50 Units/Tube Typical Applications • Battery−Based Operations NCP1378P NCP1378PG *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2004 †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 1 October, 2004 − Rev. 1 Publication Order Number: NCP1378/D NCP1378 R* + 12 V @ 1 A GND + Universal Network OVP and Demag NCP1378 1 2 3 4 8 7 6 5 + *Please refer to the application information section. Y1 Type Figure 1. Typical Application Schematic PIN FUNCTION DESCRIPTION Pin 1 2 Symbol Demag FB Function Core reset detection and OVP Sets the peak current setpoint Description The auxiliary FLYBACK signal ensures discontinuous operation and offers a fixed overvoltage detection level of 5.2 V. By connecting an optocoupler to this pin, the peak current setpoint is adjusted accordingly to the output power demand. By bringing this pin below the internal skip level, you shut off the device. This pin senses the primary current and routes it to the internal comparator via an L.E.B. By inserting a resistor in series with the pin, you control the level at which the skip operation takes place. − The driver’s output to an external MOSFET. This pin is connected to an external bulk capacitor of typically 47 mF. This unconnected pin ensures adequate creepage distance. Connected to the high−voltage rail, this pin injects a constant current into the VCC bulk capacitor and ensures a clean lossless startup sequence. 3 CS Current sense input and skip cycle level selection The IC ground Driving pulses Supplies the IC − High−voltage pin 4 5 6 7 8 GND Drv VCC NC HV http://onsemi.com 2 NCP1378 4.5 ms Delay HV Demag 4 mA + + VCC 8.4 V 7.5 V 5.6 V (Fault) Fault Mngt. + − OVP + PON 5.2 V + S Q VCC Drv 8 ms Blanking + + 50 mV 10 V Resd Demag S* Q R* R Driver src = 20 sink = 10 4.2 V To Internal Supply Soft−Start = 1 ms /3 1V 200 mA when DRV is OFF Timeout Reset 340 ns LEB Demag FB GND Overload? 5 ms Timeout CS *S and R are level triggered whereas S is edge triggered. R has priority over the other inputs. Figure 2. Internal Circuit Architecture MAXIMUM RATINGS Rating Power Supply Voltage Maximum Voltage on all other pins except Pin 8 (HV), Pin 6 (VCC) and Pin 5 (Drv) Maximum Current into all pins except VCC (6), HV (8) and Demag (1) when 10 V ESD diodes are activated Maximum Current in Pin 1 Thermal Resistance, Junction−to−Case Thermal Resistance, Junction−to−Air, SOIC Version Thermal Resistance, Junction−to−Air, PDIP Version Maximum Junction Temperature Temperature Shutdown Hysteresis in Shutdown Storage Temperature Range ESD Capability, HBM Model (All pins except VCC and HV) ESD Capability, Machine Model Maximum Voltage on Pin 8 (HV), Pin 6 (VCC) Decoupled to Ground with 10 mF Symbol VCC, Drv − − Idem RqJC RqJA RqJA TJMAX − − − − − VHV Value 16 −0.3 to 10 5.0 +3.0/−2.0 57 178 100 150 155 30 −60 to +150 2.0 200 500 Unit V V mA mA °C/W °C/W °C/W °C °C °C °C kV V V Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. http://onsemi.com 3 NCP1378 ELECTRICAL CHARACTERISTICS (For typical values Tj = 25°C, for min/max values Tj = 0°C to +125°C, Max Tj = 150°C, VCC = 11 V unless otherwise noted.) Characteristic SUPPLY SECTION VCC Increasing Level at which the Current Source Turns−Off VCC Decreasing Level at which the Current Source Turns−On VCC Excursion between VCCON and VCCmin VCC Decreasing Level at which the Latchoff Phase Ends Internal IC Consumption, No Output Load on Pin 5, FSW = 60 kHz Internal IC Consumption, 1.0 nF Output Load on Pin 5, FSW = 60 kHz Internal IC Consumption, Latchoff Phase, VCC = 6.0 V INTERNAL STARTUP CURRENT SOURCE (Tj u 0°C) High−Voltage Current Source, VCC = 7.8 V High−Voltage Current Source, VCC = 0 DRIVE OUTPUT Output Voltage Rise−Time @ CL = 1.0 nF, 10−90% of Output Signal Output Voltage Fall−Time @ CL = 1.0 nF, 10−90% of Output Signal Source Resistance Sink Resistance CURRENT COMPARATOR (Pin 5 not loaded) Input Bias Current @ 1.0 V Input Level on Pin 3 Maximum Internal Current Setpoint Propagation Delay from Current Detection to Gate OFF State Leading Edge Blanking Duration Internal Current Offset Injected on the CS Pin During OFF Time OVERVOLTAGE SECTION (VCC = 11 V) Sampling Delay After ON Time OVP Internal Reference Level FEEDBACK SECTION (VCC = 11 V, Pin 5 loaded by 1.0 kW) Internal Pullup Resistor Pin 3 to Current Setpoint Division Ratio Internal Soft−Start DEMAGNETIZATION DETECTION BLOCK Input Threshold Voltage (Vpin 1 Decreasing) Hysteresis (Vpin 1 Decreasing) Input Clamp Voltage High State (Ipin 1 = 3.0 mA) Low State (Ipin 1 = −2.0 mA) Demag Propagation Delay Internal Input Capacitance at Vpin 1 = 1.0 V Internal Blanking Delay after TON 1. Max value at Tj = 0°C, please see characterization curves. 1 1 1 1 1 1 1 Vth VH VCH VCL Tdem Cpar Tblank 30 − 8.0 −0.9 − − − 50 20 10 −0.7 240 10 8.0 90 − 12 −0.5 − − − ns pF ms mV mV V 2 − − Rup Iratio Tss − − − 20 3.3 1.0 − − − kW − ms 1 1 Tsample Vref − 4.6 4.5 5.2 − 6.3 ms V 3 3 3 3 3 IIB ILimit TDEL TLEB Iskip − 0.9 − − − 0.02 1.0 110 340 200 − 1.1 160 − − mA V ns ns mA 5 5 5 5 Tr Tf ROH ROL − − 10 4.0 40 20 20 10 − − 36 20 ns ns W W 8 8 IC1 IC2 2.4 − 4.0 4.5 6.0 − mA mA 6 6 6 6 6 6 6 VCCON VCCmin VCChyst VCClatch ICC1 ICC2 ICC3 7.8 7.0 0.8 − − − − 8.4 7.5 − 5.5 1.0 1.6 220 9.0 8.2 − − 1.3 (Note 1) 2.0 (Note 1) − V V − V mA mA mA Pin Symbol Min Typ Max Unit http://onsemi.com 4 NCP1378 TYPICAL CHARACTERISTICS 8.0 8.8 8.6 VCCMIN, (V) VCCON, (V) 7.8 8.4 7.6 8.2 7.4 8.0 7.2 7.0 −25 7.8 −25 0 25 50 75 100 125 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 3. VCCON Threshold versus Temperature 1.6 1.4 1.2 ICC1, (mA) 1.0 0.8 0.6 0.4 −25 ICC2, (mA) 2.2 2.0 1.8 1.6 1.4 1.2 Figure 4. VCCMIN Threshold versus Temperature 0 25 50 75 100 125 1.0 −25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 5. Current Consumption (No Load) versus Temperature 8 7 6 IC1, (mA) Ilimit, (V) 5 4 3 2 1 0 −25 0 25 50 75 100 125 0.95 1.05 1.10 Figure 6. Current Consumption (1.0 nF Load) versus Temperature 1.00 0.90 −25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 7. HV Current Source at VCC = 10 V versus temperature Figure 8. Maximum Current Setpoint versus Temperature http://onsemi.com 5 NCP1378 TYPICAL CHARACTERISTICS 40 35 30 ROH, (W) ROL, (W) 0 25 50 75 100 125 25 20 15 10 5 0 −25 20 18 16 14 12 10 8 6 4 2 0 −25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 9. Drive Source Resistance versus Temperature 120 100 80 VTH, (mV) 60 40 20 0 −25 Vref, (V) 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 −25 Figure 10. Drive Sink Resistance versus Temperature 0 25 50 75 100 125 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 11. Demagnetization Detection Threshold versus Temperature 10.0 9.5 9.0 8.5 8.0 7.5 7.0 6.5 −25 TOUT, (ms) TOFF, (ms) 7.0 6.5 6.0 5.5 5.0 4.5 4.0 Figure 12. OVP Threshold versus Temperature 0 25 50 75 100 125 3.5 −25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 13. Minimum TOFF versus Temperature Figure 14. Demagnetization Detection Timeout versus Temperature http://onsemi.com 6 NCP1378 APPLICATION INFORMATION INTRODUCTION • Adjustable Skip Cycle Level: By offering the ability to tailor the level at which the skip cycle takes place, the designer can make sure that the skip operation only occurs at low peak current. This point guarantees a noise−free operation with cheap transformer. This option also offers the ability to fix the maximum switching frequency when entering light load conditions. Overcurrent Protection (OCP): NCP1378 enters burst mode as soon as the power supply undergoes an overload, which is detected through the sense of the auxiliary voltage. As detailed above, as soon as VCC crosses the UVLO level (called VCCmin in the electrical table), all pulses are stopped and the device enters a safe low power operation that prevents from any lethal thermal runaway. By monitoring the VCC level, the startup current source is activated ON and OFF to create a kind of burst mode where the SMPS tries to restart. If the fault has gone, the SMPS resumes operation. On the other hand, if the fault is still there, the burst sequence starts again. The NCP1378 implements a standard current mode architecture where the switch−off time is dictated by the peak current setpoint, whereas the core reset detection triggers the turn−on event . This component represents the ideal candidate where low part−count is the key parameter in applications supplied by a battery. Due to its high− performance High−Voltage technology, the NCP1378 incorporates all the necessary components/features needed to build a rugged and reliable Switchmode Power Supply (SMPS): • Transformer Core Reset Detection: Borderline/critical operation is ensured whatever the operating conditions are. As a result, there are virtually no primary switch turn−on losses and no secondary diode recovery losses. The converter also stays a first−order system and accordingly eases the feedback loop design. • Quasi−Resonant Operation: By delaying the turn−on event, it is possible to restart the MOSFET in the minimum of the drain−source wave, ensuring reduced EMI/video noise perturbations. In nominal power conditions, the NCP1378 operates in Borderline Conduction Mode (BCM) also called Critical Conduction Mode. • Undervoltage Lockout (UVLO): When VCC falls below UVLO, all pulses are stopped and the IC consumption drops down to a few hundreds of mA (ICC3 data). When VCC reaches the latchoff level (5.5 V typical), the startup current source is activated and brings VCC back to VCCON where the IC attempts to startup. • Overvoltage Protection (OVP): By sampling the plateau voltage on the demagnetization winding, the NCP1378 goes into latched fault condition whenever an over−voltage condition is detected. The controller stays fully latched in this position until the VCC is cycled down to 4.0 V, e.g. when the user unplugs the power supply from the mains outlet and replugs it. • External LatchTrip Point: By externally forcing a level on the OVP greater than the internal setpoint, it is possible to latchoff the IC, e.g. with a signal coming from a temperature sensor. • Startup Sequence When the power supply is first powered from the mains outlet, the internal current source (typically 4.0 mA) is biased and charges up the VCC capacitor. When the voltage on this VCC capacitor reaches the VCCON level (typically 8.4 V), the current source turns off and no longer wastes any power. At this time, the VCC capacitor only supplies the controller and the auxiliary supply is supposed to take over before VCC collapses below VCCmin. Figure 15 shows the internal arrangement of this structure. VCCON/VCCmin 8 + − IC1 or 0 6 HV SVCC 4 Aux Figure 15. The Current Source Brings Vcc Above VccON and Then Turns Off http://onsemi.com 7 NCP1378 Once the power supply has started, the Vcc shall be constrained below 16 V, which is the maximum rating on pin 6. Figure 16 portrays a typical NCP1378 startup sequence with a Vcc regulated at 8.0 V. Skipping Cycle Mode 9.0 8.4 V 8.0 VCC Regulation 7.0 The NCP1378 automatically skips switching cycles when the output power demand drops below a given level. This is accomplished by monitoring the FB pin. In normal operation, pin 2 imposes a peak current accordingly to the load value. If the load demand decreases, the internal loop asks for less peak current. When this setpoint reaches a determined level, the IC prevents the current from decreasing further down and starts to blank the output pulses: the IC enters the so−called skip cycle mode, also named controlled burst operation. The power transfer now depends upon the width of the pulse bunches (Figure 17) and follows the following formula: 1 · Lp · Ip2 · Fsw · D burst with: 2 6.0 5.0 3.00M 8.00M 13.0M time in secs 18.0M 23.0M Lp = Primary inductance Fsw = Switching frequency within the burst Ip = Peak current at which skip cycle occurs Dburst = Burst width/burst recurrence Figure 16. A Typical Startup Sequence for the NCP1378 Normal Current Mode Operation MAX PEAK CURRENT CURRENT SENSE SIGNAL (mV) 300 200 SKIP CYCLE CURRENT LIMIT RESET − + 3 DRIVER = HIGH ? I = 0 DRIVER = LOW ? I = 200 mA Rskip 100 Rsense 2 0 WIDTH + RECURRENCE Figure 17. The Skip Cycle Takes Place at Low Peak Currents which Guarantees Noise−Free Operation Figure 18. A Patented Method Allows for Skip Level Selection via a Series Resistor Inserted in Series with the Current The skip level selection is done through a simple resistor inserted between the current sense input and the sense element. Every time the NCP1378 output driver goes low, a 200 mA source forces a current to flow through the sense pin (Figure 18): when the driver is high, the current source is off and the current sense information is normally processed. As soon as the driver goes low, the current source delivers 200 mA and develops a ground referenced voltage across Rskip. If this voltage is below the feedback voltage, the current sense comparator stays in the low state and the internal latch can be triggered by the next clock cycle. Now, if because of a low load mode the feedback voltage is below Rskip level, then the current sense comparator permanently resets the latch and the next clock cycle (given by the demagnetization detection) is ignored: we are skipping cycles as shown by Figure 17. As soon as the feedback voltage goes up again, there can be two situations: the recurrent period is small and a new demagnetization detection (next wave) signal triggers the NCP1378. To the opposite, in low output power conditions, no more ringing waves are present on the drain and the toggling of the current sense comparator alone initiates a new cycle start. Figure 19 depicts these two different situations. http://onsemi.com 8 NCP1378 Drain Signal Timeout Signal Demag RESTART Current Sense and Timeout Restart Drain Signal Timeout Signal 5 ms 5 ms Figure 19. When the primary natural ringing becomes too low, the current sense initiates a new cycle when FB passes the skip level. Demagnetization Detection The core reset detection is done by monitoring the voltage activity on the auxiliary winding. This voltage features a FLYBACK polarity. The typical detection level is fixed at 50 mV as exemplified by Figure 20. 7.0 DEMAG SIGNAL (V) POSSIBLE RESTARTS 5.0 3.0 TO INTERNAL COMPARATOR 3 Resd 2k 4 Rdem 1 5 2 1.0 0V 50 mV ESD ESD 4 Aux −1.0 1 Figure 20. Core Reset Detection is Done through a Dedicated Auxiliary Winding Monitoring Figure 21. Internal Pad Implementation An internal timer prevents any restart within 8.0 ms further to the driver going−low transition. This prevents the switching frequency to exceed (1.0/TON + 8.0 ms) but also avoid false leakage inductance tripping at turn−off. In some cases, the leakage inductance kick is so energetic, that a slight filtering is necessary. http://onsemi.com 9 NCP1378 The NCP1378 demagnetization detection pad features a specific component arrangement as detailed by Figure 21. In this picture, the zener diodes network protect the IC against any potential ESD discharge that could appear on the pins. The first ESD diode connected to the pad, exhibits a parasitic capacitance. When this parasitic capacitance (10 pF typically) is combined with Rdem, a restart delay is created and the possibility to switch right in the drain−source wave exists. This guarantees QR operation with all the associated benefits (low EMI, no turn−on losses etc.). Rdem should be calculated to limit the maximum current flowing through pin 1 to less than +3.0 mA/−2.0 mA: If during turn−on, the auxiliary winding delivers 30 V (at the highest line level), then the minimum Rdem value is defined by: 30 + 0.7/3.0 mA = 10.2 kW. This value will be further increased e.g. to introduce a restart delay and also a slight filtering in case of high leakage energy. Figure 22 portrays a typical VDS shot at nominal output power. Figure 23 shows where the sampling occurs on the auxiliary winding. SAMPLING HERE 8.0 DEMAG SIGNAL (V) 6.0 4.0 2.0 4.5 ms 0 Figure 23. A Voltage Sample is Taken 4.5 ms After the Turn−Off Sequence 400 DRAIN VOLTAGE (V) 300 200 100 0 Figure 22. The NCP1378 Operates in Borderline/Critical Operation Overvoltage Protection When an OVP condition has been detected, the NCP1378 enters a latchoff phase and stops all switching operations. The controller stays fully latched in this position and the startup source being still active, it keeps the VCC going up and down between 8.4 V and 5.5 V. This state lasts until the VCC is cycled down to 4.0 V, e.g. when the user unplugs the power supply from the mains outlet. By default, the OVP comparator is biased to a 5.2 V reference level and pin1 is directly routed to the comparator. As a result, when Vpin1 reaches 5.2 V, the OVP comparator is triggered. The threshold can thus be adjusted by either modifying the power winding to auxiliary winding turn ratios to match this 5.2 V level or insert a resistor from pin1 to ground to cope with your design requirement. Latching Off the NCP1378 The overvoltage protection works by sampling the plateau voltage 4.5 ms after the turn−off sequence. This delay guarantees a clean plateau, providing that the leakage inductance ringing has been fully damped. If this would not be the case, the designer should install a small RC damper across the transformer primary inductance connections. In certain cases, it can be very convenient to externally shut down permanently the NCP1378 via a dedicated signal, e.g. coming from a temperature sensor (Figure 24). The reset occurs when the user unplugs the power supply from the mains outlet. To trigger the latchoff by an external signal, a simple PNP transistor can do the work, as Figure 25 shows. http://onsemi.com 10 NCP1378 CTN NCP1378 Aux. 1 NCP1378 1 2 3 4 8 7 6 5 Aux. ON/OFF 2 3 4 8 7 6 5 VCCcap Figure 24. A simple CTN triggers the latchoff as soon as the temperature exceeds a given setpoint. Shutting Off the NCP1378 Figure 25. A simple transistor arrangement allows to trigger the latchoff by an external signal. Shutdown can easily be implemented through a simple NPN bipolar transistor as depicted by Figure 6. When OFF, Q1 is transparent to the operation. When forward biased, the transistor pulls the FB pin to ground (Vcesat [ 200 mV) and permanently disables the IC. A small time constant on the transistor base will avoid false triggering (Figure 26). NCP1378 1 1 2 10 nF Q1 2 3 4 8 7 6 5 10 k ON/OFF 3 Figure 26. A Simple Bipolar Transistor Totally Disables the IC Overload Operation In applications where the output current is purposely not controlled (e.g. wall adapters delivering raw DC level), it is interesting to implement a true short−circuit protection. A short−circuit actually forces the output voltage to be at a low level, preventing a bias current to circulate in the optocoupler LED. As a result, the auxiliary voltage also decreases because it also operates in Flyback and thus duplicates the output voltage, providing the leakage inductance between windings is kept low. To account for this situation and properly protect the power supply, NCP1378 hosts a dedicated overload detection circuitry. Once activated, this circuitry imposes to deliver pulses in a burst manner with a low Duty Cycle. The system auto−recovers when the fault condition disappears. During the startup phase, the peak current is pushed to the maximum until the output voltage reaches its target and the feedback loop takes over. The auxiliary voltage takes place after a few switching cycles and self−supplies the IC. In presence of a short circuit on the output, the auxiliary voltage will go down until it crosses the undervoltage lockout level of typically 7.5 V. When this happens, NCP1378 immediately stops the switching pulses and unbiases all unnecessary logical blocks. The overall consumption drops, while keeping the gate grounded, and the VCC slowly falls down. As soon as VCC reaches typically 5.5 V, the startup source turns−on again and a new startup sequence occurs, bringing VCC toward 8.4 V as an attempt to restart. If the default has gone, then the power supply normally restarts. If not, a new protective burst is initiated, shielding the SMPS from any runaway. Figure 27 portrays the typical operating signals in short circuit. http://onsemi.com 11 NCP1378 VccON Vccmin Vcc Vcclatch Driving Pulses Figure 27. Typical Waveforms in Short Circuit Conditions Soft−Start over. Suppose that this time was measured at around 10 ms. CVCC is calculated using the equation C + Dt · i or C w 31.1 mF. Select a 47 mF/25 V and this will fit. During the latchoff phase, the current consumption drops to 220 mA. We can now calculate how long this latchoff phase will last: (7.5–5.5) x 47 m/220 u = 427 ms. Protecting Pin 8 Against Negative Spikes DV The NCP1378 features an internal 1.0 ms Soft−Start to soften the constraints occurring in the power supply during startup. It is activated during the power on sequence. As soon as VCC reaches VCCON, the peak current is gradually increased from nearly zero up to the maximum clamping level (e.g. 1.0 V). The Soft−Start is also activated during the overcurrent burst (OCP) sequence. Every restart attempt is followed by a Soft−Start activation. Generally speaking, the Soft−Start will be activated when VCC ramps up either from zero (fresh power–on sequence) or 5.5 V, the latch–off voltage occurring during OCP. Calculating the Vcc Capacitor The VCC capacitor can be calculated knowing the IC consumption as soon as VCC reaches VCCON. Suppose that a NCP1378 is used and drives a MOSFET with a 30 nC total gate charge (Qg). The total average current is thus made of ICC1 (1.0 mA) plus the driver current, Fsw x Qg or 1.8 mA. The total current is therefore 2.8 mA. The DV available to fully startup the circuit (e.g. never reach the 7.5 V UVLO during power on) is 8.4 – 7.5 = 0.9 V. We have a capacitor that then needs to supply the NCP1378 with 2.8 mA during a given time until the auxiliary supply takes As any CMOS controller, NCP1378 is sensitive to negative voltages that could appear on its pins. To avoid any adverse latchup of the IC, we strongly recommend to insert a resistor in series with pin8. This resistor prevents from adversely latching the controller in case of negative spikes appearing on the bulk capacitor during the power−off sequence. A typical value of 6.8 kW/0.5 W is suitable. This resistor does not dissipate any power since it only sees current during the startup sequence and during overload. Operating Shots Below are some oscilloscope shots captured at Vin = 120 VDC with a transformer featuring a 800 mH primary inductance. http://onsemi.com 12 NCP1378 Figure 28. This plot gathers waveforms captured at three different operating points: 1st Upper Plot: Free run, valley switching operation, Pout = 26 W. 2nd Middle Plot: Min Toff clamps the switching frequency and selects the second valley. 3rd Lowest Plot: The skip slices the second valley pattern and will further expand the burst as Pout goes low. Vrsense (200 mV/div) Vgate 200 mA x Rskip Current Sense Pin (200 mV/pin) Figure 29. This picture explains how the 200 mA internal offset current creates the skip cycle level. http://onsemi.com 13 NCP1378 PACKAGE DIMENSIONS SOIC−8 D SUFFIX CASE 751−07 ISSUE AC −X− A 8 5 B 1 4 S 0.25 (0.010) M Y M −Y− G C −Z− H D 0.25 (0.010) M SEATING PLANE K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 N X 45 _ 0.10 (0.004) M J ZY S X S DIM A B C D G H J K M N S SOLDERING FOOTPRINT 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches http://onsemi.com 14 NCP1378 PACKAGE DIMENSIONS PDIP−7 P SUFFIX CASE 626B−01 ISSUE A NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 5. DIMENSIONS A AND B ARE DATUMS. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC −−− 10 ° 0.76 1.01 J 8 5 M B L 1 4 F NOTE 2 A C −T− SEATING PLANE N D G K B M H 0.13 (0.005) M TA M http://onsemi.com 15 NCP1378 The product described herein (NCP1378), may be covered by one or more of the following U.S. patents: 6,362,067, 6,385,060, 6,385,061, 6,429,709, 6,587,357, 6,633,193. There may be other patents pending. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Phone: 81−3−5773−3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. http://onsemi.com 16 NCP1378/D